[deliverable/linux.git] / arch / arm / mach-s3c2412 / dma.c

/* linux/arch/arm/mach-s3c2412/dma.c
 *
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2412 DMA selection
 *
 * http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>

#include <asm/dma.h>
#include <asm/arch/dma.h>
#include <asm/io.h>

#include <asm/plat-s3c24xx/dma.h>
#include <asm/plat-s3c24xx/cpu.h>

#include <asm/plat-s3c/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/plat-s3c/regs-ac97.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>
#include <asm/arch/regs-sdi.h>
#include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
#include <asm/plat-s3c24xx/regs-iis.h>
#include <asm/plat-s3c24xx/regs-spi.h>

#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }

static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
	[DMACH_XD0] = {
		.name		= "xdreq0",
		.channels	= MAP(S3C2412_DMAREQSEL_XDREQ0),
	},
	[DMACH_XD1] = {
		.name		= "xdreq1",
		.channels	= MAP(S3C2412_DMAREQSEL_XDREQ1),
	},
	[DMACH_SDI] = {
		.name		= "sdi",
		.channels	= MAP(S3C2412_DMAREQSEL_SDI),
		.hw_addr.to	= S3C2410_PA_SDI + S3C2410_SDIDATA,
		.hw_addr.from	= S3C2410_PA_SDI + S3C2410_SDIDATA,
	},
	[DMACH_SPI0] = {
		.name		= "spi0",
		.channels	= MAP(S3C2412_DMAREQSEL_SPI0TX),
		.hw_addr.to	= S3C2410_PA_SPI + S3C2410_SPTDAT,
		.hw_addr.from	= S3C2410_PA_SPI + S3C2410_SPRDAT,
	},
	[DMACH_SPI1] = {
		.name		= "spi1",
		.channels	= MAP(S3C2412_DMAREQSEL_SPI1TX),
		.hw_addr.to	= S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
		.hw_addr.from	= S3C2410_PA_SPI + S3C2412_SPI1  + S3C2410_SPRDAT,
	},
	[DMACH_UART0] = {
		.name		= "uart0",
		.channels	= MAP(S3C2412_DMAREQSEL_UART0_0),
		.hw_addr.to	= S3C2410_PA_UART0 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART0 + S3C2410_URXH,
	},
	[DMACH_UART1] = {
		.name		= "uart1",
		.channels	= MAP(S3C2412_DMAREQSEL_UART1_0),
		.hw_addr.to	= S3C2410_PA_UART1 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART1 + S3C2410_URXH,
	},
      	[DMACH_UART2] = {
		.name		= "uart2",
		.channels	= MAP(S3C2412_DMAREQSEL_UART2_0),
		.hw_addr.to	= S3C2410_PA_UART2 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART2 + S3C2410_URXH,
	},
	[DMACH_UART0_SRC2] = {
		.name		= "uart0",
		.channels	= MAP(S3C2412_DMAREQSEL_UART0_1),
		.hw_addr.to	= S3C2410_PA_UART0 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART0 + S3C2410_URXH,
	},
	[DMACH_UART1_SRC2] = {
		.name		= "uart1",
		.channels	= MAP(S3C2412_DMAREQSEL_UART1_1),
		.hw_addr.to	= S3C2410_PA_UART1 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART1 + S3C2410_URXH,
	},
      	[DMACH_UART2_SRC2] = {
		.name		= "uart2",
		.channels	= MAP(S3C2412_DMAREQSEL_UART2_1),
		.hw_addr.to	= S3C2410_PA_UART2 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART2 + S3C2410_URXH,
	},
	[DMACH_TIMER] = {
		.name		= "timer",
		.channels	= MAP(S3C2412_DMAREQSEL_TIMER),
	},
	[DMACH_I2S_IN] = {
		.name		= "i2s-sdi",
		.channels	= MAP(S3C2412_DMAREQSEL_I2SRX),
		.hw_addr.from	= S3C2410_PA_IIS + S3C2412_IISRXD,
	},
	[DMACH_I2S_OUT] = {
		.name		= "i2s-sdo",
		.channels	= MAP(S3C2412_DMAREQSEL_I2STX),
		.hw_addr.to	= S3C2410_PA_IIS + S3C2412_IISTXD,
	},
	[DMACH_USB_EP1] = {
		.name		= "usb-ep1",
		.channels	= MAP(S3C2412_DMAREQSEL_USBEP1),
	},
	[DMACH_USB_EP2] = {
		.name		= "usb-ep2",
		.channels	= MAP(S3C2412_DMAREQSEL_USBEP2),
	},
	[DMACH_USB_EP3] = {
		.name		= "usb-ep3",
		.channels	= MAP(S3C2412_DMAREQSEL_USBEP3),
	},
	[DMACH_USB_EP4] = {
		.name		= "usb-ep4",
		.channels	= MAP(S3C2412_DMAREQSEL_USBEP4),
	},
};

static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
			       struct s3c24xx_dma_map *map)
{
	writel(map->channels[0] | S3C2412_DMAREQSEL_HW,
	       chan->regs + S3C2412_DMA_DMAREQSEL);
}

static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
	.select		= s3c2412_dma_select,
	.dcon_mask	= 0,
	.map		= s3c2412_dma_mappings,
	.map_size	= ARRAY_SIZE(s3c2412_dma_mappings),
};

static int __init s3c2412_dma_add(struct sys_device *sysdev)
{
	s3c2410_dma_init();
	return s3c24xx_dma_init_map(&s3c2412_dma_sel);
}

static struct sysdev_driver s3c2412_dma_driver = {
	.add	= s3c2412_dma_add,
};

static int __init s3c2412_dma_init(void)
{
	return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
}

arch_initcall(s3c2412_dma_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2412/dma.c
34348012	2	*
c16f7bd8	3	* Copyright (c) 2006 Simtec Electronics
34348012 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2412 DMA selection
	7	*
	8	* http://armlinux.simtec.co.uk/
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/sysdev.h>
b6d1f542	18	#include <linux/serial_core.h>
34348012 BD	19
	20	#include <asm/dma.h>
	21	#include <asm/arch/dma.h>
	22	#include <asm/io.h>
	23
a21765a7 BD	24	#include <asm/plat-s3c24xx/dma.h>
a21765a7 BD	25	#include <asm/plat-s3c24xx/cpu.h>
34348012	26
531b617c	27	#include <asm/plat-s3c/regs-serial.h>
34348012	28	#include <asm/arch/regs-gpio.h>
06cfa556	29	#include <asm/plat-s3c/regs-ac97.h>
34348012 BD	30	#include <asm/arch/regs-mem.h>
	31	#include <asm/arch/regs-lcd.h>
	32	#include <asm/arch/regs-sdi.h>
d45c30cb	33	#include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
06cfa556 BD	34	#include <asm/plat-s3c24xx/regs-iis.h>
06cfa556 BD	35	#include <asm/plat-s3c24xx/regs-spi.h>
34348012 BD	36
	37	#define MAP(x) { (x)\| DMA_CH_VALID, (x)\| DMA_CH_VALID, (x)\| DMA_CH_VALID, (x)\| DMA_CH_VALID }
	38
	39	static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
	40	[DMACH_XD0] = {
	41	.name = "xdreq0",
	42	.channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
	43	},
	44	[DMACH_XD1] = {
	45	.name = "xdreq1",
	46	.channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
	47	},
	48	[DMACH_SDI] = {
	49	.name = "sdi",
	50	.channels = MAP(S3C2412_DMAREQSEL_SDI),
d45c30cb BD	51	.hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
d45c30cb BD	52	.hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
34348012 BD	53	},
	54	[DMACH_SPI0] = {
	55	.name = "spi0",
	56	.channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
	57	.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
	58	.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
	59	},
	60	[DMACH_SPI1] = {
	61	.name = "spi1",
	62	.channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
e903382c SSP	63	.hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
e903382c SSP	64	.hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
34348012 BD	65	},
	66	[DMACH_UART0] = {
	67	.name = "uart0",
	68	.channels = MAP(S3C2412_DMAREQSEL_UART0_0),
	69	.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
	70	.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
	71	},
	72	[DMACH_UART1] = {
	73	.name = "uart1",
	74	.channels = MAP(S3C2412_DMAREQSEL_UART1_0),
	75	.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
	76	.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
	77	},
	78	[DMACH_UART2] = {
	79	.name = "uart2",
	80	.channels = MAP(S3C2412_DMAREQSEL_UART2_0),
	81	.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
	82	.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
	83	},
	84	[DMACH_UART0_SRC2] = {
	85	.name = "uart0",
	86	.channels = MAP(S3C2412_DMAREQSEL_UART0_1),
	87	.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
	88	.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
	89	},
	90	[DMACH_UART1_SRC2] = {
	91	.name = "uart1",
	92	.channels = MAP(S3C2412_DMAREQSEL_UART1_1),
	93	.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
	94	.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
	95	},
	96	[DMACH_UART2_SRC2] = {
	97	.name = "uart2",
	98	.channels = MAP(S3C2412_DMAREQSEL_UART2_1),
	99	.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
	100	.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
	101	},
	102	[DMACH_TIMER] = {
	103	.name = "timer",
	104	.channels = MAP(S3C2412_DMAREQSEL_TIMER),
	105	},
	106	[DMACH_I2S_IN] = {
	107	.name = "i2s-sdi",
	108	.channels = MAP(S3C2412_DMAREQSEL_I2SRX),
d45c30cb	109	.hw_addr.from = S3C2410_PA_IIS + S3C2412_IISRXD,
34348012 BD	110	},
	111	[DMACH_I2S_OUT] = {
	112	.name = "i2s-sdo",
	113	.channels = MAP(S3C2412_DMAREQSEL_I2STX),
d45c30cb	114	.hw_addr.to = S3C2410_PA_IIS + S3C2412_IISTXD,
34348012 BD	115	},
	116	[DMACH_USB_EP1] = {
	117	.name = "usb-ep1",
	118	.channels = MAP(S3C2412_DMAREQSEL_USBEP1),
	119	},
	120	[DMACH_USB_EP2] = {
	121	.name = "usb-ep2",
	122	.channels = MAP(S3C2412_DMAREQSEL_USBEP2),
	123	},
	124	[DMACH_USB_EP3] = {
	125	.name = "usb-ep3",
	126	.channels = MAP(S3C2412_DMAREQSEL_USBEP3),
	127	},
	128	[DMACH_USB_EP4] = {
	129	.name = "usb-ep4",
	130	.channels = MAP(S3C2412_DMAREQSEL_USBEP4),
	131	},
	132	};
	133
	134	static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
	135	struct s3c24xx_dma_map *map)
	136	{
b9d1902c BD	137	writel(map->channels[0] \| S3C2412_DMAREQSEL_HW,
b9d1902c BD	138	chan->regs + S3C2412_DMA_DMAREQSEL);
34348012 BD	139	}
	140
	141	static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
	142	.select = s3c2412_dma_select,
	143	.dcon_mask = 0,
	144	.map = s3c2412_dma_mappings,
	145	.map_size = ARRAY_SIZE(s3c2412_dma_mappings),
	146	};
	147
f2c10d6c	148	static int __init s3c2412_dma_add(struct sys_device *sysdev)
34348012	149	{
48adbcf3	150	s3c2410_dma_init();
34348012 BD	151	return s3c24xx_dma_init_map(&s3c2412_dma_sel);
	152	}
	153
	154	static struct sysdev_driver s3c2412_dma_driver = {
	155	.add = s3c2412_dma_add,
	156	};
	157
	158	static int __init s3c2412_dma_init(void)
	159	{
	160	return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
	161	}
	162
	163	arch_initcall(s3c2412_dma_init);