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a21765a7 | 1 | /* linux/arch/arm/mach-s3c2412/s3c2412.c |
68d9ab39 BD |
2 | * |
3 | * Copyright (c) 2006 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * http://armlinux.simtec.co.uk/. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
68d9ab39 BD |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
eca8c242 | 19 | #include <linux/delay.h> |
68d9ab39 | 20 | #include <linux/sysdev.h> |
b6d1f542 | 21 | #include <linux/serial_core.h> |
68d9ab39 | 22 | #include <linux/platform_device.h> |
fced80c7 | 23 | #include <linux/io.h> |
68d9ab39 BD |
24 | |
25 | #include <asm/mach/arch.h> | |
26 | #include <asm/mach/map.h> | |
27 | #include <asm/mach/irq.h> | |
28 | ||
a09e64fb | 29 | #include <mach/hardware.h> |
c84cbb24 | 30 | #include <asm/proc-fns.h> |
68d9ab39 BD |
31 | #include <asm/irq.h> |
32 | ||
a09e64fb RK |
33 | #include <mach/reset.h> |
34 | #include <mach/idle.h> | |
c84cbb24 | 35 | |
a09e64fb | 36 | #include <mach/regs-clock.h> |
a2b7ba9c | 37 | #include <plat/regs-serial.h> |
a09e64fb RK |
38 | #include <mach/regs-power.h> |
39 | #include <mach/regs-gpio.h> | |
40 | #include <mach/regs-gpioj.h> | |
41 | #include <mach/regs-dsc.h> | |
13622708 | 42 | #include <plat/regs-spi.h> |
a09e64fb | 43 | #include <mach/regs-s3c2412.h> |
68d9ab39 | 44 | |
d5120ae7 | 45 | #include <plat/s3c2412.h> |
a2b7ba9c BD |
46 | #include <plat/cpu.h> |
47 | #include <plat/devs.h> | |
d5120ae7 | 48 | #include <plat/clock.h> |
a2b7ba9c | 49 | #include <plat/pm.h> |
e24b864a | 50 | #include <plat/pll.h> |
68d9ab39 BD |
51 | |
52 | #ifndef CONFIG_CPU_S3C2412_ONLY | |
53 | void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; | |
50dedf16 BD |
54 | |
55 | static inline void s3c2412_init_gpio2(void) | |
56 | { | |
57 | s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10; | |
58 | } | |
59 | #else | |
60 | #define s3c2412_init_gpio2() do { } while(0) | |
68d9ab39 BD |
61 | #endif |
62 | ||
63 | /* Initial IO mappings */ | |
64 | ||
65 | static struct map_desc s3c2412_iodesc[] __initdata = { | |
66 | IODESC_ENT(CLKPWR), | |
68d9ab39 | 67 | IODESC_ENT(TIMER), |
68d9ab39 BD |
68 | IODESC_ENT(WATCHDOG), |
69 | }; | |
70 | ||
71 | /* uart registration process */ | |
72 | ||
73 | void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
74 | { | |
75 | s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no); | |
76 | ||
77 | /* rename devices that are s3c2412/s3c2413 specific */ | |
78 | s3c_device_sdi.name = "s3c2412-sdi"; | |
72d70d06 | 79 | s3c_device_lcd.name = "s3c2412-lcd"; |
68d9ab39 | 80 | s3c_device_nand.name = "s3c2412-nand"; |
e903382c | 81 | |
f3fb5a55 BD |
82 | /* alter IRQ of SDI controller */ |
83 | ||
84 | s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI; | |
85 | s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI; | |
86 | ||
e903382c SSP |
87 | /* spi channel related changes, s3c2412/13 specific */ |
88 | s3c_device_spi0.name = "s3c2412-spi"; | |
89 | s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24; | |
90 | s3c_device_spi1.name = "s3c2412-spi"; | |
91 | s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1; | |
92 | s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24; | |
93 | ||
68d9ab39 BD |
94 | } |
95 | ||
c84cbb24 BD |
96 | /* s3c2412_idle |
97 | * | |
98 | * use the standard idle call by ensuring the idle mode | |
99 | * in power config, then issuing the idle co-processor | |
100 | * instruction | |
101 | */ | |
102 | ||
103 | static void s3c2412_idle(void) | |
104 | { | |
105 | unsigned long tmp; | |
106 | ||
107 | /* ensure our idle mode is to go to idle */ | |
108 | ||
109 | tmp = __raw_readl(S3C2412_PWRCFG); | |
110 | tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK; | |
111 | tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; | |
112 | __raw_writel(tmp, S3C2412_PWRCFG); | |
113 | ||
114 | cpu_do_idle(); | |
115 | } | |
116 | ||
eca8c242 BD |
117 | static void s3c2412_hard_reset(void) |
118 | { | |
119 | /* errata "Watch-dog/Software Reset Problem" specifies that | |
120 | * this reset must be done with the SYSCLK sourced from | |
121 | * EXTCLK instead of FOUT to avoid a glitch in the reset | |
122 | * mechanism. | |
123 | * | |
124 | * See the watchdog section of the S3C2412 manual for more | |
125 | * information on this fix. | |
126 | */ | |
127 | ||
128 | __raw_writel(0x00, S3C2412_CLKSRC); | |
129 | __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST); | |
130 | ||
131 | mdelay(1); | |
132 | } | |
133 | ||
68d9ab39 BD |
134 | /* s3c2412_map_io |
135 | * | |
136 | * register the standard cpu IO areas, and any passed in from the | |
137 | * machine specific initialisation. | |
138 | */ | |
139 | ||
74b265d4 | 140 | void __init s3c2412_map_io(void) |
68d9ab39 BD |
141 | { |
142 | /* move base of IO */ | |
143 | ||
50dedf16 | 144 | s3c2412_init_gpio2(); |
68d9ab39 | 145 | |
c84cbb24 BD |
146 | /* set our idle function */ |
147 | ||
148 | s3c24xx_idle = s3c2412_idle; | |
149 | ||
eca8c242 BD |
150 | /* set custom reset hook */ |
151 | ||
152 | s3c24xx_reset_hook = s3c2412_hard_reset; | |
153 | ||
68d9ab39 BD |
154 | /* register our io-tables */ |
155 | ||
156 | iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); | |
68d9ab39 BD |
157 | } |
158 | ||
159 | void __init s3c2412_init_clocks(int xtal) | |
160 | { | |
161 | unsigned long tmp; | |
162 | unsigned long fclk; | |
163 | unsigned long hclk; | |
164 | unsigned long pclk; | |
165 | ||
166 | /* now we've got our machine bits initialised, work out what | |
167 | * clocks we've got */ | |
168 | ||
e24b864a | 169 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); |
68d9ab39 | 170 | |
cca851d7 BD |
171 | clk_mpll.rate = fclk; |
172 | ||
68d9ab39 BD |
173 | tmp = __raw_readl(S3C2410_CLKDIVN); |
174 | ||
175 | /* work out clock scalings */ | |
176 | ||
177 | hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); | |
1017be88 | 178 | hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); |
68d9ab39 BD |
179 | pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); |
180 | ||
181 | /* print brieft summary of clocks, etc */ | |
182 | ||
183 | printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | |
184 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | |
185 | ||
186 | /* initialise the clocks here, to allow other things like the | |
187 | * console to use them | |
188 | */ | |
189 | ||
190 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | |
191 | s3c2412_baseclk_add(); | |
192 | } | |
193 | ||
194 | /* need to register class before we actually register the device, and | |
195 | * we also need to ensure that it has been initialised before any of the | |
196 | * drivers even try to use it (even if not on an s3c2412 based system) | |
197 | * as a driver which may support both 2410 and 2440 may try and use it. | |
198 | */ | |
199 | ||
68d9ab39 | 200 | struct sysdev_class s3c2412_sysclass = { |
af5ca3f4 | 201 | .name = "s3c2412-core", |
68d9ab39 BD |
202 | }; |
203 | ||
204 | static int __init s3c2412_core_init(void) | |
205 | { | |
206 | return sysdev_class_register(&s3c2412_sysclass); | |
207 | } | |
208 | ||
209 | core_initcall(s3c2412_core_init); | |
210 | ||
211 | static struct sys_device s3c2412_sysdev = { | |
212 | .cls = &s3c2412_sysclass, | |
213 | }; | |
214 | ||
215 | int __init s3c2412_init(void) | |
216 | { | |
217 | printk("S3C2412: Initialising architecture\n"); | |
218 | ||
219 | return sysdev_register(&s3c2412_sysdev); | |
220 | } |