[deliverable/linux.git] / arch / arm / mach-s3c2416 / clock.c

/* linux/arch/arm/mach-s3c2416/clock.c
 *
 * Copyright (c) 2010 Simtec Electronics
 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
 *
 * S3C2416 Clock control support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/clk.h>

#include <plat/s3c2416.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/cpu.h>

#include <plat/cpu-freq.h>
#include <plat/pll.h>

#include <asm/mach/map.h>

#include <mach/regs-clock.h>
#include <mach/regs-s3c2443-clock.h>

/* armdiv
 *
 * this clock is sourced from msysclk and can have a number of
 * divider values applied to it to then be fed into armclk.
 * The real clock definition is done in s3c2443-clock.c,
 * only the armdiv divisor table must be defined here.
*/

static unsigned int armdiv[8] = {
	[0] = 1,
	[1] = 2,
	[2] = 3,
	[3] = 4,
	[5] = 6,
	[7] = 8,
};

static struct clksrc_clk hsspi_eplldiv = {
	.clk = {
		.name	= "hsspi-eplldiv",
		.parent	= &clk_esysclk.clk,
		.ctrlbit = (1 << 14),
		.enable = s3c2443_clkcon_enable_s,
	},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
};

static struct clk *hsspi_sources[] = {
	[0] = &hsspi_eplldiv.clk,
	[1] = NULL, /* to fix */
};

static struct clksrc_clk hsspi_mux = {
	.clk	= {
		.name	= "hsspi-if",
	},
	.sources = &(struct clksrc_sources) {
		.sources = hsspi_sources,
		.nr_sources = ARRAY_SIZE(hsspi_sources),
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
};

static struct clksrc_clk hsmmc_div[] = {
	[0] = {
		.clk = {
			.name	= "hsmmc-div",
			.devname	= "s3c-sdhci.0",
			.parent	= &clk_esysclk.clk,
		},
		.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
	},
	[1] = {
		.clk = {
			.name	= "hsmmc-div",
			.devname	= "s3c-sdhci.1",
			.parent	= &clk_esysclk.clk,
		},
		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
	},
};

static struct clksrc_clk hsmmc_mux0 = {
	.clk	= {
		.name		= "hsmmc-if",
		.devname	= "s3c-sdhci.0",
		.ctrlbit	= (1 << 6),
		.enable		= s3c2443_clkcon_enable_s,
	},
	.sources	= &(struct clksrc_sources) {
		.nr_sources	= 2,
		.sources	= (struct clk * []) {
			[0]	= &hsmmc_div[0].clk,
			[1]	= NULL, /* to fix */
		},
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
};

static struct clksrc_clk hsmmc_mux1 = {
	.clk	= {
		.name		= "hsmmc-if",
		.devname	= "s3c-sdhci.1",
		.ctrlbit	= (1 << 12),
		.enable		= s3c2443_clkcon_enable_s,
	},
	.sources	= &(struct clksrc_sources) {
		.nr_sources	= 2,
		.sources	= (struct clk * []) {
			[0]	= &hsmmc_div[1].clk,
			[1]	= NULL, /* to fix */
		},
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
};

static struct clk hsmmc0_clk = {
	.name		= "hsmmc",
	.devname	= "s3c-sdhci.0",
	.parent		= &clk_h,
	.enable		= s3c2443_clkcon_enable_h,
	.ctrlbit	= S3C2416_HCLKCON_HSMMC0,
};

void __init_or_cpufreq s3c2416_setup_clocks(void)
{
	s3c2443_common_setup_clocks(s3c2416_get_pll);
}


static struct clksrc_clk *clksrcs[] __initdata = {
	&hsspi_eplldiv,
	&hsspi_mux,
	&hsmmc_div[0],
	&hsmmc_div[1],
	&hsmmc_mux0,
	&hsmmc_mux1,
};

static struct clk_lookup s3c2416_clk_lookup[] = {
	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
};

void __init s3c2416_init_clocks(int xtal)
{
	u32 epllcon = __raw_readl(S3C2443_EPLLCON);
	u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
	int ptr;

	/* s3c2416 EPLL compatible with s3c64xx */
	clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);

	clk_epll.parent = &clk_epllref.clk;

	s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
				   armdiv, ARRAY_SIZE(armdiv),
				   S3C2416_CLKDIV0_ARMDIV_MASK);

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_register_clksrc(clksrcs[ptr], 1);

	s3c24xx_register_clock(&hsmmc0_clk);
	clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));

	s3c_pwmclk_init();

}
Commit	Line	Data
8d6f8658 BD	1	/* linux/arch/arm/mach-s3c2416/clock.c
	2	*
	3	* Copyright (c) 2010 Simtec Electronics
	4	* Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
	5	*
	6	* S3C2416 Clock control support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/clk.h>
	16
	17	#include <plat/s3c2416.h>
8d6f8658 BD	18	#include <plat/clock.h>
	19	#include <plat/clock-clksrc.h>
	20	#include <plat/cpu.h>
	21
	22	#include <plat/cpu-freq.h>
8d6f8658 BD	23	#include <plat/pll.h>
	24
	25	#include <asm/mach/map.h>
	26
	27	#include <mach/regs-clock.h>
	28	#include <mach/regs-s3c2443-clock.h>
	29
efb1fb48 HS	30	/* armdiv
	31	*
	32	* this clock is sourced from msysclk and can have a number of
	33	* divider values applied to it to then be fed into armclk.
	34	* The real clock definition is done in s3c2443-clock.c,
	35	* only the armdiv divisor table must be defined here.
	36	*/
	37
8d6f8658 BD	38	static unsigned int armdiv[8] = {
	39	[0] = 1,
	40	[1] = 2,
	41	[2] = 3,
	42	[3] = 4,
	43	[5] = 6,
	44	[7] = 8,
	45	};
	46
4a43c666 HS	47	static struct clksrc_clk hsspi_eplldiv = {
	48	.clk = {
	49	.name = "hsspi-eplldiv",
	50	.parent = &clk_esysclk.clk,
	51	.ctrlbit = (1 << 14),
	52	.enable = s3c2443_clkcon_enable_s,
	53	},
	54	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
	55	};
	56
	57	static struct clk *hsspi_sources[] = {
	58	[0] = &hsspi_eplldiv.clk,
	59	[1] = NULL, /* to fix */
	60	};
	61
	62	static struct clksrc_clk hsspi_mux = {
	63	.clk = {
	64	.name = "hsspi-if",
	65	},
	66	.sources = &(struct clksrc_sources) {
	67	.sources = hsspi_sources,
	68	.nr_sources = ARRAY_SIZE(hsspi_sources),
	69	},
	70	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
	71	};
	72
8d6f8658 BD	73	static struct clksrc_clk hsmmc_div[] = {
	74	[0] = {
	75	.clk = {
	76	.name = "hsmmc-div",
e83626f2	77	.devname = "s3c-sdhci.0",
8d6f8658 BD	78	.parent = &clk_esysclk.clk,
	79	},
	80	.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
	81	},
	82	[1] = {
	83	.clk = {
	84	.name = "hsmmc-div",
e83626f2	85	.devname = "s3c-sdhci.1",
8d6f8658 BD	86	.parent = &clk_esysclk.clk,
	87	},
	88	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
	89	},
	90	};
	91
a361d10a RS	92	static struct clksrc_clk hsmmc_mux0 = {
	93	.clk = {
	94	.name = "hsmmc-if",
	95	.devname = "s3c-sdhci.0",
	96	.ctrlbit = (1 << 6),
	97	.enable = s3c2443_clkcon_enable_s,
8d6f8658	98	},
a361d10a RS	99	.sources = &(struct clksrc_sources) {
	100	.nr_sources = 2,
	101	.sources = (struct clk * []) {
	102	[0] = &hsmmc_div[0].clk,
	103	[1] = NULL, /* to fix */
8d6f8658	104	},
a361d10a RS	105	},
	106	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
	107	};
	108
	109	static struct clksrc_clk hsmmc_mux1 = {
	110	.clk = {
	111	.name = "hsmmc-if",
	112	.devname = "s3c-sdhci.1",
	113	.ctrlbit = (1 << 12),
	114	.enable = s3c2443_clkcon_enable_s,
	115	},
	116	.sources = &(struct clksrc_sources) {
	117	.nr_sources = 2,
	118	.sources = (struct clk * []) {
	119	[0] = &hsmmc_div[1].clk,
	120	[1] = NULL, /* to fix */
8d6f8658	121	},
8d6f8658	122	},
a361d10a	123	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
8d6f8658 BD	124	};
8d6f8658 BD	125
95d6791b YK	126	static struct clk hsmmc0_clk = {
95d6791b YK	127	.name = "hsmmc",
e83626f2	128	.devname = "s3c-sdhci.0",
95d6791b YK	129	.parent = &clk_h,
	130	.enable = s3c2443_clkcon_enable_h,
	131	.ctrlbit = S3C2416_HCLKCON_HSMMC0,
	132	};
8d6f8658	133
8d6f8658 BD	134	void __init_or_cpufreq s3c2416_setup_clocks(void)
8d6f8658 BD	135	{
33ccedfd	136	s3c2443_common_setup_clocks(s3c2416_get_pll);
8d6f8658 BD	137	}
	138
	139
	140	static struct clksrc_clk *clksrcs[] __initdata = {
4a43c666 HS	141	&hsspi_eplldiv,
4a43c666 HS	142	&hsspi_mux,
8d6f8658 BD	143	&hsmmc_div[0],
8d6f8658 BD	144	&hsmmc_div[1],
a361d10a RS	145	&hsmmc_mux0,
	146	&hsmmc_mux1,
	147	};
	148
	149	static struct clk_lookup s3c2416_clk_lookup[] = {
	150	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
	151	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
	152	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
8d6f8658 BD	153	};
	154
	155	void __init s3c2416_init_clocks(int xtal)
	156	{
	157	u32 epllcon = __raw_readl(S3C2443_EPLLCON);
	158	u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
	159	int ptr;
	160
	161	/* s3c2416 EPLL compatible with s3c64xx */
	162	clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
	163
	164	clk_epll.parent = &clk_epllref.clk;
	165
33ccedfd	166	s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
d9a3bfbd HS	167	armdiv, ARRAY_SIZE(armdiv),
d9a3bfbd HS	168	S3C2416_CLKDIV0_ARMDIV_MASK);
8d6f8658 BD	169
	170	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
	171	s3c_register_clksrc(clksrcs[ptr], 1);
	172
95d6791b	173	s3c24xx_register_clock(&hsmmc0_clk);
a361d10a	174	clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
95d6791b	175
8d6f8658 BD	176	s3c_pwmclk_init();
	177
	178	}