[deliverable/linux.git] / arch / arm / mach-s3c2440 / mach-anubis.c

/* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
 * Copyright (c) 2003-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>

#include <linux/sm501.h>
#include <linux/sm501-regs.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/arch/anubis-map.h>
#include <asm/arch/anubis-irq.h>
#include <asm/arch/anubis-cpld.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <asm/plat-s3c/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>
#include <asm/plat-s3c/nand.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <net/ax88796.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>

#define COPYRIGHT ", (c) 2005 Simtec Electronics"

static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */

  {
	.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	.pfn		= __phys_to_pfn(0x0),
	.length		= SZ_4M,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)S3C24XX_VA_ISA_WORD,
	.pfn		= __phys_to_pfn(0x0),
	.length 	= SZ_4M,
	.type		= MT_DEVICE,
  },

  /* we could possibly compress the next set down into a set of smaller tables
   * pagetables, but that would mean using an L2 section, and it still means
   * we cannot actually feed the same register to an LDR due to 16K spacing
   */

  /* CPLD control registers */

  {
	.virtual	= (u32)ANUBIS_VA_CTRL1,
	.pfn		= __phys_to_pfn(ANUBIS_PA_CTRL1),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)ANUBIS_VA_IDREG,
	.pfn		= __phys_to_pfn(ANUBIS_PA_IDREG),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
	[1] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
};

/* NAND Flash on Anubis board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition anubis_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition anubis_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Anubis has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set anubis_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
};

static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	tmp |= slot;

	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);

	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}

static struct s3c2410_platform_nand anubis_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),
	.sets		= anubis_nand_sets,
	.select_chip	= anubis_nand_select,
};

/* IDE channels */

struct pata_platform_info anubis_ide_platdata = {
	.ioport_shift	= 5,
};

static struct resource anubis_ide0_resource[] = {
	{
		.start	= S3C2410_CS3,
		.end	= S3C2410_CS3 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS3 + (1<<26) + (6*32),
		.end	= S3C2410_CS3 + (1<<26) + (7*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide0 = {
	.name		= "pata_platform",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_ide0_resource),
	.resource	= anubis_ide0_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

static struct resource anubis_ide1_resource[] = {
	{
		.start	= S3C2410_CS4,
		.end	= S3C2410_CS4 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS4 + (1<<26) + (6*32),
		.end	= S3C2410_CS4 + (1<<26) + (7*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide1 = {
	.name		= "pata_platform",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(anubis_ide1_resource),
	.resource	= anubis_ide1_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data anubis_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource anubis_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5,
		.end   = S3C2410_CS5 + (0x20 * 0x20) -1,
		.flags = IORESOURCE_MEM
	},
	[1] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device anubis_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_asix_resource),
	.resource	= anubis_asix_resource,
	.dev		= {
		.platform_data = &anubis_asix_platdata,
	}
};

/* SM501 */

static struct resource anubis_sm501_resource[] = {
	[0] = {
		.start	= S3C2410_CS2,
		.end	= S3C2410_CS2 + SZ_8M,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= S3C2410_CS2 + SZ_64M - SZ_2M,
		.end	= S3C2410_CS2 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[2] = {
		.start	= IRQ_EINT0,
		.end	= IRQ_EINT0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct sm501_initdata anubis_sm501_initdata = {
	.gpio_high	= {
		.set	= 0x3F000000,		/* 24bit panel */
		.mask	= 0x0,
	},
	.misc_timing	= {
		.set	= 0x010100,		/* SDRAM timing */
		.mask	= 0x1F1F00,
	},
	.misc_control	= {
		.set	= SM501_MISC_PNL_24BIT,
		.mask	= 0,
	},

	/* set the SDRAM and bus clocks */
	.mclk		= 72 * MHZ,
	.m1xclk		= 144 * MHZ,
};

static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	[0] = {
		.pin_scl	= 44,
		.pin_sda	= 45,
	},
	[1] = {
		.pin_scl	= 40,
		.pin_sda	= 41,
	},
};

static struct sm501_platdata anubis_sm501_platdata = {
	.init		= &anubis_sm501_initdata,
	.gpio_i2c	= anubis_sm501_gpio_i2c,
	.gpio_i2c_nr	= ARRAY_SIZE(anubis_sm501_gpio_i2c),
};

static struct platform_device anubis_device_sm501 = {
	.name		= "sm501",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_sm501_resource),
	.resource	= anubis_sm501_resource,
	.dev		= {
		.platform_data = &anubis_sm501_platdata,
	},
};

/* Standard Anubis devices */

static struct platform_device *anubis_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&anubis_device_ide0,
	&anubis_device_ide1,
	&anubis_device_asix,
	&anubis_device_sm501,
};

static struct clk *anubis_clocks[] = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static void __init anubis_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));

	s3c_device_nand.dev.platform_data = &anubis_nand_info;

	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
		printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
		       __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
		anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
		anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	} else {
		/* ensure that the GPIO is setup */
		s3c2410_gpio_setpin(S3C2410_GPA0, 1);
	}
}

static void __init anubis_init(void)
{
	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
}


MACHINE_START(ANUBIS, "Simtec-Anubis")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= anubis_map_io,
	.init_machine	= anubis_init,
	.init_irq	= s3c24xx_init_irq,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-anubis.c
7efb833d BD	2	*
	3	* Copyright (c) 2003-2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
7efb833d BD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
7efb833d BD	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
b6d1f542	18	#include <linux/serial_core.h>
d052d1be	19	#include <linux/platform_device.h>
b9db83af	20	#include <linux/ata_platform.h>
7efb833d	21
8a9ccb7f BD	22	#include <linux/sm501.h>
	23	#include <linux/sm501-regs.h>
	24
7efb833d BD	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/map.h>
	27	#include <asm/mach/irq.h>
	28
	29	#include <asm/arch/anubis-map.h>
	30	#include <asm/arch/anubis-irq.h>
	31	#include <asm/arch/anubis-cpld.h>
	32
	33	#include <asm/hardware.h>
	34	#include <asm/io.h>
	35	#include <asm/irq.h>
	36	#include <asm/mach-types.h>
	37
531b617c	38	#include <asm/plat-s3c/regs-serial.h>
7efb833d BD	39	#include <asm/arch/regs-gpio.h>
	40	#include <asm/arch/regs-mem.h>
	41	#include <asm/arch/regs-lcd.h>
531b617c	42	#include <asm/plat-s3c/nand.h>
7efb833d BD	43
	44	#include <linux/mtd/mtd.h>
	45	#include <linux/mtd/nand.h>
	46	#include <linux/mtd/nand_ecc.h>
	47	#include <linux/mtd/partitions.h>
	48
eac1d8da BD	49	#include <net/ax88796.h>
eac1d8da BD	50
a21765a7 BD	51	#include <asm/plat-s3c24xx/clock.h>
	52	#include <asm/plat-s3c24xx/devs.h>
	53	#include <asm/plat-s3c24xx/cpu.h>
7efb833d BD	54
	55	#define COPYRIGHT ", (c) 2005 Simtec Electronics"
	56
	57	static struct map_desc anubis_iodesc[] __initdata = {
	58	/* ISA IO areas */
	59
8dd52311 BD	60	{
	61	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	62	.pfn = __phys_to_pfn(0x0),
	63	.length = SZ_4M,
705630db	64	.type = MT_DEVICE,
8dd52311 BD	65	}, {
	66	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	67	.pfn = __phys_to_pfn(0x0),
705630db BD	68	.length = SZ_4M,
705630db BD	69	.type = MT_DEVICE,
8dd52311	70	},
7efb833d BD	71
	72	/* we could possibly compress the next set down into a set of smaller tables
	73	* pagetables, but that would mean using an L2 section, and it still means
	74	* we cannot actually feed the same register to an LDR due to 16K spacing
	75	*/
	76
	77	/* CPLD control registers */
	78
8dd52311 BD	79	{
	80	.virtual = (u32)ANUBIS_VA_CTRL1,
	81	.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
	82	.length = SZ_4K,
705630db	83	.type = MT_DEVICE,
8dd52311	84	}, {
6c1640d5 BD	85	.virtual = (u32)ANUBIS_VA_IDREG,
6c1640d5 BD	86	.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
8dd52311	87	.length = SZ_4K,
705630db	88	.type = MT_DEVICE,
8dd52311	89	},
7efb833d BD	90	};
	91
	92	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	93	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	94	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	95
	96	static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	97	[0] = {
	98	.name = "uclk",
	99	.divisor = 1,
	100	.min_baud = 0,
	101	.max_baud = 0,
	102	},
	103	[1] = {
	104	.name = "pclk",
	105	.divisor = 1,
	106	.min_baud = 0,
705630db	107	.max_baud = 0,
7efb833d BD	108	}
	109	};
	110
	111
66a9b49a	112	static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
7efb833d BD	113	[0] = {
	114	.hwport = 0,
	115	.flags = 0,
	116	.ucon = UCON,
	117	.ulcon = ULCON,
	118	.ufcon = UFCON,
	119	.clocks = anubis_serial_clocks,
705630db	120	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	121	},
	122	[1] = {
	123	.hwport = 2,
	124	.flags = 0,
	125	.ucon = UCON,
	126	.ulcon = ULCON,
	127	.ufcon = UFCON,
	128	.clocks = anubis_serial_clocks,
705630db	129	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	130	},
	131	};
	132
	133	/* NAND Flash on Anubis board */
	134
	135	static int external_map[] = { 2 };
	136	static int chip0_map[] = { 0 };
	137	static int chip1_map[] = { 1 };
	138
9f693d7b	139	static struct mtd_partition anubis_default_nand_part[] = {
7efb833d BD	140	[0] = {
	141	.name = "Boot Agent",
	142	.size = SZ_16K,
705630db	143	.offset = 0,
7efb833d BD	144	},
	145	[1] = {
	146	.name = "/boot",
	147	.size = SZ_4M - SZ_16K,
	148	.offset = SZ_16K,
	149	},
	150	[2] = {
	151	.name = "user1",
	152	.offset = SZ_4M,
	153	.size = SZ_32M - SZ_4M,
	154	},
	155	[3] = {
	156	.name = "user2",
	157	.offset = SZ_32M,
	158	.size = MTDPART_SIZ_FULL,
	159	}
	160	};
	161
ad3613f4 BD	162	static struct mtd_partition anubis_default_nand_part_large[] = {
	163	[0] = {
	164	.name = "Boot Agent",
	165	.size = SZ_128K,
	166	.offset = 0,
	167	},
	168	[1] = {
	169	.name = "/boot",
	170	.size = SZ_4M - SZ_128K,
	171	.offset = SZ_128K,
	172	},
	173	[2] = {
	174	.name = "user1",
	175	.offset = SZ_4M,
	176	.size = SZ_32M - SZ_4M,
	177	},
	178	[3] = {
	179	.name = "user2",
	180	.offset = SZ_32M,
	181	.size = MTDPART_SIZ_FULL,
	182	}
	183	};
	184
7efb833d BD	185	/* the Anubis has 3 selectable slots for nand-flash, the two
	186	* on-board chip areas, as well as the external slot.
	187	*
	188	* Note, there is no current hot-plug support for the External
	189	* socket.
	190	*/
	191
	192	static struct s3c2410_nand_set anubis_nand_sets[] = {
	193	[1] = {
	194	.name = "External",
	195	.nr_chips = 1,
	196	.nr_map = external_map,
	197	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	198	.partitions = anubis_default_nand_part,
7efb833d BD	199	},
	200	[0] = {
	201	.name = "chip0",
	202	.nr_chips = 1,
	203	.nr_map = chip0_map,
	204	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	205	.partitions = anubis_default_nand_part,
7efb833d BD	206	},
	207	[2] = {
	208	.name = "chip1",
	209	.nr_chips = 1,
	210	.nr_map = chip1_map,
	211	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	212	.partitions = anubis_default_nand_part,
7efb833d BD	213	},
	214	};
	215
	216	static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
	217	{
	218	unsigned int tmp;
	219
	220	slot = set->nr_map[slot] & 3;
	221
	222	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
	223	slot, set, set->nr_map);
	224
	225	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	226	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	227	tmp \|= slot;
	228
	229	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
	230
	231	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
	232	}
	233
	234	static struct s3c2410_platform_nand anubis_nand_info = {
	235	.tacls = 25,
661e6acf BD	236	.twrph0 = 55,
661e6acf BD	237	.twrph1 = 40,
7efb833d BD	238	.nr_sets = ARRAY_SIZE(anubis_nand_sets),
	239	.sets = anubis_nand_sets,
	240	.select_chip = anubis_nand_select,
	241	};
	242
bf1c56a3 BD	243	/* IDE channels */
bf1c56a3 BD	244
b9db83af BD	245	struct pata_platform_info anubis_ide_platdata = {
	246	.ioport_shift = 5,
	247	};
	248
bf1c56a3 BD	249	static struct resource anubis_ide0_resource[] = {
	250	{
	251	.start = S3C2410_CS3,
	252	.end = S3C2410_CS3 + (8*32) - 1,
	253	.flags = IORESOURCE_MEM,
	254	}, {
b9db83af BD	255	.start = S3C2410_CS3 + (1<<26) + (6*32),
b9db83af BD	256	.end = S3C2410_CS3 + (1<<26) + (7*32) - 1,
bf1c56a3 BD	257	.flags = IORESOURCE_MEM,
	258	}, {
	259	.start = IRQ_IDE0,
	260	.end = IRQ_IDE0,
	261	.flags = IORESOURCE_IRQ,
	262	},
	263	};
	264
	265	static struct platform_device anubis_device_ide0 = {
b9db83af	266	.name = "pata_platform",
bf1c56a3 BD	267	.id = 0,
	268	.num_resources = ARRAY_SIZE(anubis_ide0_resource),
	269	.resource = anubis_ide0_resource,
b9db83af BD	270	.dev = {
	271	.platform_data = &anubis_ide_platdata,
	272	.coherent_dma_mask = ~0,
	273	},
bf1c56a3 BD	274	};
	275
	276	static struct resource anubis_ide1_resource[] = {
	277	{
	278	.start = S3C2410_CS4,
	279	.end = S3C2410_CS4 + (8*32) - 1,
	280	.flags = IORESOURCE_MEM,
	281	}, {
b9db83af BD	282	.start = S3C2410_CS4 + (1<<26) + (6*32),
b9db83af BD	283	.end = S3C2410_CS4 + (1<<26) + (7*32) - 1,
bf1c56a3 BD	284	.flags = IORESOURCE_MEM,
	285	}, {
	286	.start = IRQ_IDE0,
	287	.end = IRQ_IDE0,
	288	.flags = IORESOURCE_IRQ,
	289	},
	290	};
	291
bf1c56a3	292	static struct platform_device anubis_device_ide1 = {
b9db83af	293	.name = "pata_platform",
bf1c56a3 BD	294	.id = 1,
	295	.num_resources = ARRAY_SIZE(anubis_ide1_resource),
	296	.resource = anubis_ide1_resource,
b9db83af BD	297	.dev = {
	298	.platform_data = &anubis_ide_platdata,
	299	.coherent_dma_mask = ~0,
	300	},
bf1c56a3	301	};
7efb833d	302
eac1d8da BD	303	/* Asix AX88796 10/100 ethernet controller */
	304
	305	static struct ax_plat_data anubis_asix_platdata = {
	306	.flags = AXFLG_MAC_FROMDEV,
	307	.wordlength = 2,
	308	.dcr_val = 0x48,
	309	.rcr_val = 0x40,
	310	};
	311
	312	static struct resource anubis_asix_resource[] = {
	313	[0] = {
	314	.start = S3C2410_CS5,
	315	.end = S3C2410_CS5 + (0x20 * 0x20) -1,
	316	.flags = IORESOURCE_MEM
	317	},
	318	[1] = {
	319	.start = IRQ_ASIX,
	320	.end = IRQ_ASIX,
	321	.flags = IORESOURCE_IRQ
	322	}
	323	};
	324
	325	static struct platform_device anubis_device_asix = {
	326	.name = "ax88796",
	327	.id = 0,
	328	.num_resources = ARRAY_SIZE(anubis_asix_resource),
	329	.resource = anubis_asix_resource,
	330	.dev = {
	331	.platform_data = &anubis_asix_platdata,
	332	}
	333	};
	334
8a9ccb7f BD	335	/* SM501 */
	336
	337	static struct resource anubis_sm501_resource[] = {
	338	[0] = {
	339	.start = S3C2410_CS2,
	340	.end = S3C2410_CS2 + SZ_8M,
	341	.flags = IORESOURCE_MEM,
	342	},
	343	[1] = {
	344	.start = S3C2410_CS2 + SZ_64M - SZ_2M,
	345	.end = S3C2410_CS2 + SZ_64M - 1,
	346	.flags = IORESOURCE_MEM,
	347	},
	348	[2] = {
	349	.start = IRQ_EINT0,
	350	.end = IRQ_EINT0,
	351	.flags = IORESOURCE_IRQ,
	352	},
	353	};
	354
	355	static struct sm501_initdata anubis_sm501_initdata = {
	356	.gpio_high = {
	357	.set = 0x3F000000, /* 24bit panel */
	358	.mask = 0x0,
	359	},
	360	.misc_timing = {
	361	.set = 0x010100, /* SDRAM timing */
	362	.mask = 0x1F1F00,
	363	},
	364	.misc_control = {
	365	.set = SM501_MISC_PNL_24BIT,
	366	.mask = 0,
	367	},
	368
	369	/* set the SDRAM and bus clocks */
	370	.mclk = 72 * MHZ,
	371	.m1xclk = 144 * MHZ,
	372	};
	373
	374	static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	375	[0] = {
	376	.pin_scl = 44,
	377	.pin_sda = 45,
	378	},
	379	[1] = {
	380	.pin_scl = 40,
	381	.pin_sda = 41,
	382	},
	383	};
	384
	385	static struct sm501_platdata anubis_sm501_platdata = {
	386	.init = &anubis_sm501_initdata,
	387	.gpio_i2c = anubis_sm501_gpio_i2c,
	388	.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
	389	};
	390
	391	static struct platform_device anubis_device_sm501 = {
	392	.name = "sm501",
	393	.id = 0,
	394	.num_resources = ARRAY_SIZE(anubis_sm501_resource),
	395	.resource = anubis_sm501_resource,
	396	.dev = {
	397	.platform_data = &anubis_sm501_platdata,
	398	},
399	};
400
7efb833d BD	401	/* Standard Anubis devices */
	402
	403	static struct platform_device *anubis_devices[] __initdata = {
	404	&s3c_device_usb,
	405	&s3c_device_wdt,
	406	&s3c_device_adc,
	407	&s3c_device_i2c,
	408	&s3c_device_rtc,
	409	&s3c_device_nand,
bf1c56a3 BD	410	&anubis_device_ide0,
bf1c56a3 BD	411	&anubis_device_ide1,
eac1d8da	412	&anubis_device_asix,
8a9ccb7f	413	&anubis_device_sm501,
7efb833d BD	414	};
	415
	416	static struct clk *anubis_clocks[] = {
	417	&s3c24xx_dclk0,
	418	&s3c24xx_dclk1,
	419	&s3c24xx_clkout0,
	420	&s3c24xx_clkout1,
	421	&s3c24xx_uclk,
	422	};
	423
5fe10ab1	424	static void __init anubis_map_io(void)
7efb833d BD	425	{
	426	/* initialise the clocks */
	427
d96a9804	428	s3c24xx_dclk0.parent = &clk_upll;
7efb833d BD	429	s3c24xx_dclk0.rate = 1210001000;
7efb833d BD	430
d96a9804	431	s3c24xx_dclk1.parent = &clk_upll;
7efb833d BD	432	s3c24xx_dclk1.rate = 2410001000;
	433
	434	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	435	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	436
	437	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	438
ce89c206 BD	439	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
ce89c206 BD	440
7efb833d BD	441	s3c_device_nand.dev.platform_data = &anubis_nand_info;
	442
	443	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	444	s3c24xx_init_clocks(0);
	445	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
7efb833d	446
ad3613f4 BD	447	/* check for the newer revision boards with large page nand */
	448
	449	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
	450	printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
	451	__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
	452	anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
	453	anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	454	} else {
	455	/* ensure that the GPIO is setup */
	456	s3c2410_gpio_setpin(S3C2410_GPA0, 1);
	457	}
7efb833d BD	458	}
7efb833d BD	459
57e5171c BD	460	static void __init anubis_init(void)
	461	{
	462	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
	463	}
	464
	465
7efb833d BD	466	MACHINE_START(ANUBIS, "Simtec-Anubis")
7efb833d BD	467	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
7efb833d BD	468	.phys_io = S3C2410_PA_UART,
	469	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	470	.boot_params = S3C2410_SDRAM_PA + 0x100,
	471	.map_io = anubis_map_io,
57e5171c	472	.init_machine = anubis_init,
7efb833d BD	473	.init_irq = s3c24xx_init_irq,
	474	.timer = &s3c24xx_timer,
	475	MACHINE_END