[deliverable/linux.git] / arch / arm / mach-s3c2440 / mach-anubis.c

/* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
 * Copyright (c) 2003-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>

#include <linux/sm501.h>
#include <linux/sm501-regs.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/arch/anubis-map.h>
#include <asm/arch/anubis-irq.h>
#include <asm/arch/anubis-cpld.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <asm/arch/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>
#include <asm/arch/nand.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <net/ax88796.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>

#define COPYRIGHT ", (c) 2005 Simtec Electronics"

static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */

  {
	.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	.pfn		= __phys_to_pfn(0x0),
	.length		= SZ_4M,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)S3C24XX_VA_ISA_WORD,
	.pfn		= __phys_to_pfn(0x0),
	.length 	= SZ_4M,
	.type		= MT_DEVICE,
  },

  /* we could possibly compress the next set down into a set of smaller tables
   * pagetables, but that would mean using an L2 section, and it still means
   * we cannot actually feed the same register to an LDR due to 16K spacing
   */

  /* CPLD control registers */

  {
	.virtual	= (u32)ANUBIS_VA_CTRL1,
	.pfn		= __phys_to_pfn(ANUBIS_PA_CTRL1),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)ANUBIS_VA_IDREG,
	.pfn		= __phys_to_pfn(ANUBIS_PA_IDREG),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
	[1] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
};

/* NAND Flash on Anubis board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition anubis_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Anubis has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set anubis_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
};

static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	tmp |= slot;

	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);

	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}

static struct s3c2410_platform_nand anubis_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),
	.sets		= anubis_nand_sets,
	.select_chip	= anubis_nand_select,
};

/* IDE channels */

static struct resource anubis_ide0_resource[] = {
	{
		.start	= S3C2410_CS3,
		.end	= S3C2410_CS3 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS3 + (1<<26),
		.end	= S3C2410_CS3 + (1<<26) + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide0 = {
	.name		= "simtec-ide",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_ide0_resource),
	.resource	= anubis_ide0_resource,
};

static struct resource anubis_ide1_resource[] = {
	{
		.start	= S3C2410_CS4,
		.end	= S3C2410_CS4 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS4 + (1<<26),
		.end	= S3C2410_CS4 + (1<<26) + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};


static struct platform_device anubis_device_ide1 = {
	.name		= "simtec-ide",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(anubis_ide1_resource),
	.resource	= anubis_ide1_resource,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data anubis_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource anubis_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5,
		.end   = S3C2410_CS5 + (0x20 * 0x20) -1,
		.flags = IORESOURCE_MEM
	},
	[1] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device anubis_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_asix_resource),
	.resource	= anubis_asix_resource,
	.dev		= {
		.platform_data = &anubis_asix_platdata,
	}
};

/* SM501 */

static struct resource anubis_sm501_resource[] = {
	[0] = {
		.start	= S3C2410_CS2,
		.end	= S3C2410_CS2 + SZ_8M,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= S3C2410_CS2 + SZ_64M - SZ_2M,
		.end	= S3C2410_CS2 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[2] = {
		.start	= IRQ_EINT0,
		.end	= IRQ_EINT0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct sm501_initdata anubis_sm501_initdata = {
	.gpio_high	= {
		.set	= 0x3F000000,		/* 24bit panel */
		.mask	= 0x0,
	},
	.misc_timing	= {
		.set	= 0x010100,		/* SDRAM timing */
		.mask	= 0x1F1F00,
	},
	.misc_control	= {
		.set	= SM501_MISC_PNL_24BIT,
		.mask	= 0,
	},

	/* set the SDRAM and bus clocks */
	.mclk		= 72 * MHZ,
	.m1xclk		= 144 * MHZ,
};

static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	[0] = {
		.pin_scl	= 44,
		.pin_sda	= 45,
	},
	[1] = {
		.pin_scl	= 40,
		.pin_sda	= 41,
	},
};

static struct sm501_platdata anubis_sm501_platdata = {
	.init		= &anubis_sm501_initdata,
	.gpio_i2c	= anubis_sm501_gpio_i2c,
	.gpio_i2c_nr	= ARRAY_SIZE(anubis_sm501_gpio_i2c),
};

static struct platform_device anubis_device_sm501 = {
	.name		= "sm501",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_sm501_resource),
	.resource	= anubis_sm501_resource,
	.dev		= {
		.platform_data = &anubis_sm501_platdata,
	},
};

/* Standard Anubis devices */

static struct platform_device *anubis_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&anubis_device_ide0,
	&anubis_device_ide1,
	&anubis_device_asix,
	&anubis_device_sm501,
};

static struct clk *anubis_clocks[] = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static void __init anubis_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = NULL;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = NULL;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));

	s3c_device_nand.dev.platform_data = &anubis_nand_info;

	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));

	/* ensure that the GPIO is setup */
	s3c2410_gpio_setpin(S3C2410_GPA0, 1);
}

static void __init anubis_init(void)
{
	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
}


MACHINE_START(ANUBIS, "Simtec-Anubis")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= anubis_map_io,
	.init_machine	= anubis_init,
	.init_irq	= s3c24xx_init_irq,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-anubis.c
7efb833d BD	2	*
	3	* Copyright (c) 2003-2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
7efb833d BD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
7efb833d BD	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
b6d1f542	18	#include <linux/serial_core.h>
d052d1be	19	#include <linux/platform_device.h>
7efb833d	20
8a9ccb7f BD	21	#include <linux/sm501.h>
	22	#include <linux/sm501-regs.h>
	23
7efb833d BD	24	#include <asm/mach/arch.h>
	25	#include <asm/mach/map.h>
	26	#include <asm/mach/irq.h>
	27
	28	#include <asm/arch/anubis-map.h>
	29	#include <asm/arch/anubis-irq.h>
	30	#include <asm/arch/anubis-cpld.h>
	31
	32	#include <asm/hardware.h>
	33	#include <asm/io.h>
	34	#include <asm/irq.h>
	35	#include <asm/mach-types.h>
	36
	37	#include <asm/arch/regs-serial.h>
	38	#include <asm/arch/regs-gpio.h>
	39	#include <asm/arch/regs-mem.h>
	40	#include <asm/arch/regs-lcd.h>
	41	#include <asm/arch/nand.h>
	42
	43	#include <linux/mtd/mtd.h>
	44	#include <linux/mtd/nand.h>
	45	#include <linux/mtd/nand_ecc.h>
	46	#include <linux/mtd/partitions.h>
	47
eac1d8da BD	48	#include <net/ax88796.h>
eac1d8da BD	49
a21765a7 BD	50	#include <asm/plat-s3c24xx/clock.h>
	51	#include <asm/plat-s3c24xx/devs.h>
	52	#include <asm/plat-s3c24xx/cpu.h>
7efb833d BD	53
	54	#define COPYRIGHT ", (c) 2005 Simtec Electronics"
	55
	56	static struct map_desc anubis_iodesc[] __initdata = {
	57	/* ISA IO areas */
	58
8dd52311 BD	59	{
	60	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	61	.pfn = __phys_to_pfn(0x0),
	62	.length = SZ_4M,
705630db	63	.type = MT_DEVICE,
8dd52311 BD	64	}, {
	65	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	66	.pfn = __phys_to_pfn(0x0),
705630db BD	67	.length = SZ_4M,
705630db BD	68	.type = MT_DEVICE,
8dd52311	69	},
7efb833d BD	70
	71	/* we could possibly compress the next set down into a set of smaller tables
	72	* pagetables, but that would mean using an L2 section, and it still means
	73	* we cannot actually feed the same register to an LDR due to 16K spacing
	74	*/
	75
	76	/* CPLD control registers */
	77
8dd52311 BD	78	{
	79	.virtual = (u32)ANUBIS_VA_CTRL1,
	80	.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
	81	.length = SZ_4K,
705630db	82	.type = MT_DEVICE,
8dd52311	83	}, {
6c1640d5 BD	84	.virtual = (u32)ANUBIS_VA_IDREG,
6c1640d5 BD	85	.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
8dd52311	86	.length = SZ_4K,
705630db	87	.type = MT_DEVICE,
8dd52311	88	},
7efb833d BD	89	};
	90
	91	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	92	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	93	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	94
	95	static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	96	[0] = {
	97	.name = "uclk",
	98	.divisor = 1,
	99	.min_baud = 0,
	100	.max_baud = 0,
	101	},
	102	[1] = {
	103	.name = "pclk",
	104	.divisor = 1,
	105	.min_baud = 0,
705630db	106	.max_baud = 0,
7efb833d BD	107	}
	108	};
	109
	110
66a9b49a	111	static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
7efb833d BD	112	[0] = {
	113	.hwport = 0,
	114	.flags = 0,
	115	.ucon = UCON,
	116	.ulcon = ULCON,
	117	.ufcon = UFCON,
	118	.clocks = anubis_serial_clocks,
705630db	119	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	120	},
	121	[1] = {
	122	.hwport = 2,
	123	.flags = 0,
	124	.ucon = UCON,
	125	.ulcon = ULCON,
	126	.ufcon = UFCON,
	127	.clocks = anubis_serial_clocks,
705630db	128	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	129	},
	130	};
	131
	132	/* NAND Flash on Anubis board */
	133
	134	static int external_map[] = { 2 };
	135	static int chip0_map[] = { 0 };
	136	static int chip1_map[] = { 1 };
	137
9f693d7b	138	static struct mtd_partition anubis_default_nand_part[] = {
7efb833d BD	139	[0] = {
	140	.name = "Boot Agent",
	141	.size = SZ_16K,
705630db	142	.offset = 0,
7efb833d BD	143	},
	144	[1] = {
	145	.name = "/boot",
	146	.size = SZ_4M - SZ_16K,
	147	.offset = SZ_16K,
	148	},
	149	[2] = {
	150	.name = "user1",
	151	.offset = SZ_4M,
	152	.size = SZ_32M - SZ_4M,
	153	},
	154	[3] = {
	155	.name = "user2",
	156	.offset = SZ_32M,
	157	.size = MTDPART_SIZ_FULL,
	158	}
	159	};
	160
	161	/* the Anubis has 3 selectable slots for nand-flash, the two
	162	* on-board chip areas, as well as the external slot.
	163	*
	164	* Note, there is no current hot-plug support for the External
	165	* socket.
	166	*/
	167
	168	static struct s3c2410_nand_set anubis_nand_sets[] = {
	169	[1] = {
	170	.name = "External",
	171	.nr_chips = 1,
	172	.nr_map = external_map,
	173	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	174	.partitions = anubis_default_nand_part,
7efb833d BD	175	},
	176	[0] = {
	177	.name = "chip0",
	178	.nr_chips = 1,
	179	.nr_map = chip0_map,
	180	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	181	.partitions = anubis_default_nand_part,
7efb833d BD	182	},
	183	[2] = {
	184	.name = "chip1",
	185	.nr_chips = 1,
	186	.nr_map = chip1_map,
	187	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	188	.partitions = anubis_default_nand_part,
7efb833d BD	189	},
	190	};
	191
	192	static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
	193	{
	194	unsigned int tmp;
	195
	196	slot = set->nr_map[slot] & 3;
	197
	198	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
	199	slot, set, set->nr_map);
	200
	201	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	202	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	203	tmp \|= slot;
	204
	205	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
	206
	207	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
	208	}
	209
	210	static struct s3c2410_platform_nand anubis_nand_info = {
	211	.tacls = 25,
661e6acf BD	212	.twrph0 = 55,
661e6acf BD	213	.twrph1 = 40,
7efb833d BD	214	.nr_sets = ARRAY_SIZE(anubis_nand_sets),
	215	.sets = anubis_nand_sets,
	216	.select_chip = anubis_nand_select,
	217	};
	218
bf1c56a3 BD	219	/* IDE channels */
	220
	221	static struct resource anubis_ide0_resource[] = {
	222	{
	223	.start = S3C2410_CS3,
	224	.end = S3C2410_CS3 + (8*32) - 1,
	225	.flags = IORESOURCE_MEM,
	226	}, {
	227	.start = S3C2410_CS3 + (1<<26),
	228	.end = S3C2410_CS3 + (1<<26) + (8*32) - 1,
	229	.flags = IORESOURCE_MEM,
	230	}, {
	231	.start = IRQ_IDE0,
	232	.end = IRQ_IDE0,
	233	.flags = IORESOURCE_IRQ,
	234	},
	235	};
	236
	237	static struct platform_device anubis_device_ide0 = {
	238	.name = "simtec-ide",
	239	.id = 0,
	240	.num_resources = ARRAY_SIZE(anubis_ide0_resource),
	241	.resource = anubis_ide0_resource,
	242	};
	243
	244	static struct resource anubis_ide1_resource[] = {
	245	{
	246	.start = S3C2410_CS4,
	247	.end = S3C2410_CS4 + (8*32) - 1,
	248	.flags = IORESOURCE_MEM,
	249	}, {
	250	.start = S3C2410_CS4 + (1<<26),
	251	.end = S3C2410_CS4 + (1<<26) + (8*32) - 1,
	252	.flags = IORESOURCE_MEM,
	253	}, {
	254	.start = IRQ_IDE0,
	255	.end = IRQ_IDE0,
	256	.flags = IORESOURCE_IRQ,
	257	},
	258	};
	259
	260
	261	static struct platform_device anubis_device_ide1 = {
	262	.name = "simtec-ide",
	263	.id = 1,
	264	.num_resources = ARRAY_SIZE(anubis_ide1_resource),
	265	.resource = anubis_ide1_resource,
	266	};
7efb833d	267
eac1d8da BD	268	/* Asix AX88796 10/100 ethernet controller */
	269
	270	static struct ax_plat_data anubis_asix_platdata = {
	271	.flags = AXFLG_MAC_FROMDEV,
	272	.wordlength = 2,
	273	.dcr_val = 0x48,
	274	.rcr_val = 0x40,
	275	};
	276
	277	static struct resource anubis_asix_resource[] = {
	278	[0] = {
	279	.start = S3C2410_CS5,
	280	.end = S3C2410_CS5 + (0x20 * 0x20) -1,
	281	.flags = IORESOURCE_MEM
	282	},
	283	[1] = {
	284	.start = IRQ_ASIX,
	285	.end = IRQ_ASIX,
	286	.flags = IORESOURCE_IRQ
	287	}
	288	};
	289
	290	static struct platform_device anubis_device_asix = {
	291	.name = "ax88796",
	292	.id = 0,
	293	.num_resources = ARRAY_SIZE(anubis_asix_resource),
	294	.resource = anubis_asix_resource,
	295	.dev = {
	296	.platform_data = &anubis_asix_platdata,
	297	}
	298	};
	299
8a9ccb7f BD	300	/* SM501 */
	301
	302	static struct resource anubis_sm501_resource[] = {
	303	[0] = {
	304	.start = S3C2410_CS2,
	305	.end = S3C2410_CS2 + SZ_8M,
	306	.flags = IORESOURCE_MEM,
	307	},
	308	[1] = {
	309	.start = S3C2410_CS2 + SZ_64M - SZ_2M,
	310	.end = S3C2410_CS2 + SZ_64M - 1,
	311	.flags = IORESOURCE_MEM,
	312	},
	313	[2] = {
	314	.start = IRQ_EINT0,
	315	.end = IRQ_EINT0,
	316	.flags = IORESOURCE_IRQ,
	317	},
	318	};
	319
	320	static struct sm501_initdata anubis_sm501_initdata = {
	321	.gpio_high = {
	322	.set = 0x3F000000, /* 24bit panel */
	323	.mask = 0x0,
	324	},
	325	.misc_timing = {
	326	.set = 0x010100, /* SDRAM timing */
	327	.mask = 0x1F1F00,
	328	},
	329	.misc_control = {
	330	.set = SM501_MISC_PNL_24BIT,
	331	.mask = 0,
	332	},
	333
	334	/* set the SDRAM and bus clocks */
	335	.mclk = 72 * MHZ,
	336	.m1xclk = 144 * MHZ,
	337	};
	338
	339	static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	340	[0] = {
	341	.pin_scl = 44,
	342	.pin_sda = 45,
	343	},
	344	[1] = {
	345	.pin_scl = 40,
	346	.pin_sda = 41,
	347	},
	348	};
	349
	350	static struct sm501_platdata anubis_sm501_platdata = {
	351	.init = &anubis_sm501_initdata,
	352	.gpio_i2c = anubis_sm501_gpio_i2c,
	353	.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
	354	};
	355
	356	static struct platform_device anubis_device_sm501 = {
	357	.name = "sm501",
	358	.id = 0,
	359	.num_resources = ARRAY_SIZE(anubis_sm501_resource),
	360	.resource = anubis_sm501_resource,
	361	.dev = {
	362	.platform_data = &anubis_sm501_platdata,
	363	},
364	};
365
7efb833d BD	366	/* Standard Anubis devices */
	367
	368	static struct platform_device *anubis_devices[] __initdata = {
	369	&s3c_device_usb,
	370	&s3c_device_wdt,
	371	&s3c_device_adc,
	372	&s3c_device_i2c,
	373	&s3c_device_rtc,
	374	&s3c_device_nand,
bf1c56a3 BD	375	&anubis_device_ide0,
bf1c56a3 BD	376	&anubis_device_ide1,
eac1d8da	377	&anubis_device_asix,
8a9ccb7f	378	&anubis_device_sm501,
7efb833d BD	379	};
	380
	381	static struct clk *anubis_clocks[] = {
	382	&s3c24xx_dclk0,
	383	&s3c24xx_dclk1,
	384	&s3c24xx_clkout0,
	385	&s3c24xx_clkout1,
	386	&s3c24xx_uclk,
	387	};
	388
5fe10ab1	389	static void __init anubis_map_io(void)
7efb833d BD	390	{
	391	/* initialise the clocks */
	392
	393	s3c24xx_dclk0.parent = NULL;
	394	s3c24xx_dclk0.rate = 1210001000;
	395
	396	s3c24xx_dclk1.parent = NULL;
	397	s3c24xx_dclk1.rate = 2410001000;
	398
	399	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	400	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	401
	402	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	403
ce89c206 BD	404	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
ce89c206 BD	405
7efb833d BD	406	s3c_device_nand.dev.platform_data = &anubis_nand_info;
	407
	408	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	409	s3c24xx_init_clocks(0);
	410	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
7efb833d BD	411
	412	/* ensure that the GPIO is setup */
	413	s3c2410_gpio_setpin(S3C2410_GPA0, 1);
	414	}
	415
57e5171c BD	416	static void __init anubis_init(void)
	417	{
	418	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
	419	}
	420
	421
7efb833d BD	422	MACHINE_START(ANUBIS, "Simtec-Anubis")
7efb833d BD	423	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
7efb833d BD	424	.phys_io = S3C2410_PA_UART,
	425	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	426	.boot_params = S3C2410_SDRAM_PA + 0x100,
	427	.map_io = anubis_map_io,
57e5171c	428	.init_machine = anubis_init,
7efb833d BD	429	.init_irq = s3c24xx_init_irq,
	430	.timer = &s3c24xx_timer,
	431	MACHINE_END