[deliverable/linux.git] / arch / arm / mach-s3c2440 / mach-anubis.c

/* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
 * Copyright (c) 2003-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/arch/anubis-map.h>
#include <asm/arch/anubis-irq.h>
#include <asm/arch/anubis-cpld.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <asm/arch/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>
#include <asm/arch/nand.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <net/ax88796.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>

#define COPYRIGHT ", (c) 2005 Simtec Electronics"

static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */

  {
	.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	.pfn		= __phys_to_pfn(0x0),
	.length		= SZ_4M,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)S3C24XX_VA_ISA_WORD,
	.pfn		= __phys_to_pfn(0x0),
	.length 	= SZ_4M,
	.type		= MT_DEVICE,
  },

  /* we could possibly compress the next set down into a set of smaller tables
   * pagetables, but that would mean using an L2 section, and it still means
   * we cannot actually feed the same register to an LDR due to 16K spacing
   */

  /* CPLD control registers */

  {
	.virtual	= (u32)ANUBIS_VA_CTRL1,
	.pfn		= __phys_to_pfn(ANUBIS_PA_CTRL1),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)ANUBIS_VA_IDREG,
	.pfn		= __phys_to_pfn(ANUBIS_PA_IDREG),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
	[1] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
};

/* NAND Flash on Anubis board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition anubis_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Anubis has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set anubis_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
};

static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	tmp |= slot;

	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);

	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}

static struct s3c2410_platform_nand anubis_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),
	.sets		= anubis_nand_sets,
	.select_chip	= anubis_nand_select,
};

/* IDE channels */

static struct resource anubis_ide0_resource[] = {
	{
		.start	= S3C2410_CS3,
		.end	= S3C2410_CS3 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS3 + (1<<26),
		.end	= S3C2410_CS3 + (1<<26) + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide0 = {
	.name		= "simtec-ide",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_ide0_resource),
	.resource	= anubis_ide0_resource,
};

static struct resource anubis_ide1_resource[] = {
	{
		.start	= S3C2410_CS4,
		.end	= S3C2410_CS4 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS4 + (1<<26),
		.end	= S3C2410_CS4 + (1<<26) + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};


static struct platform_device anubis_device_ide1 = {
	.name		= "simtec-ide",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(anubis_ide1_resource),
	.resource	= anubis_ide1_resource,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data anubis_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource anubis_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5,
		.end   = S3C2410_CS5 + (0x20 * 0x20) -1,
		.flags = IORESOURCE_MEM
	},
	[1] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device anubis_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_asix_resource),
	.resource	= anubis_asix_resource,
	.dev		= {
		.platform_data = &anubis_asix_platdata,
	}
};

/* Standard Anubis devices */

static struct platform_device *anubis_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&anubis_device_ide0,
	&anubis_device_ide1,
	&anubis_device_asix,
};

static struct clk *anubis_clocks[] = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static void __init anubis_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = NULL;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = NULL;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));

	s3c_device_nand.dev.platform_data = &anubis_nand_info;

	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));

	/* ensure that the GPIO is setup */
	s3c2410_gpio_setpin(S3C2410_GPA0, 1);
}

static void __init anubis_init(void)
{
	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
}


MACHINE_START(ANUBIS, "Simtec-Anubis")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= anubis_map_io,
	.init_machine	= anubis_init,
	.init_irq	= s3c24xx_init_irq,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-anubis.c
7efb833d BD	2	*
	3	* Copyright (c) 2003-2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
7efb833d BD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
7efb833d BD	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
b6d1f542	18	#include <linux/serial_core.h>
d052d1be	19	#include <linux/platform_device.h>
7efb833d BD	20
	21	#include <asm/mach/arch.h>
	22	#include <asm/mach/map.h>
	23	#include <asm/mach/irq.h>
	24
	25	#include <asm/arch/anubis-map.h>
	26	#include <asm/arch/anubis-irq.h>
	27	#include <asm/arch/anubis-cpld.h>
	28
	29	#include <asm/hardware.h>
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/mach-types.h>
	33
	34	#include <asm/arch/regs-serial.h>
	35	#include <asm/arch/regs-gpio.h>
	36	#include <asm/arch/regs-mem.h>
	37	#include <asm/arch/regs-lcd.h>
	38	#include <asm/arch/nand.h>
	39
	40	#include <linux/mtd/mtd.h>
	41	#include <linux/mtd/nand.h>
	42	#include <linux/mtd/nand_ecc.h>
	43	#include <linux/mtd/partitions.h>
	44
eac1d8da BD	45	#include <net/ax88796.h>
eac1d8da BD	46
a21765a7 BD	47	#include <asm/plat-s3c24xx/clock.h>
	48	#include <asm/plat-s3c24xx/devs.h>
	49	#include <asm/plat-s3c24xx/cpu.h>
7efb833d BD	50
	51	#define COPYRIGHT ", (c) 2005 Simtec Electronics"
	52
	53	static struct map_desc anubis_iodesc[] __initdata = {
	54	/* ISA IO areas */
	55
8dd52311 BD	56	{
	57	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	58	.pfn = __phys_to_pfn(0x0),
	59	.length = SZ_4M,
705630db	60	.type = MT_DEVICE,
8dd52311 BD	61	}, {
	62	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	63	.pfn = __phys_to_pfn(0x0),
705630db BD	64	.length = SZ_4M,
705630db BD	65	.type = MT_DEVICE,
8dd52311	66	},
7efb833d BD	67
	68	/* we could possibly compress the next set down into a set of smaller tables
	69	* pagetables, but that would mean using an L2 section, and it still means
	70	* we cannot actually feed the same register to an LDR due to 16K spacing
	71	*/
	72
	73	/* CPLD control registers */
	74
8dd52311 BD	75	{
	76	.virtual = (u32)ANUBIS_VA_CTRL1,
	77	.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
	78	.length = SZ_4K,
705630db	79	.type = MT_DEVICE,
8dd52311	80	}, {
6c1640d5 BD	81	.virtual = (u32)ANUBIS_VA_IDREG,
6c1640d5 BD	82	.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
8dd52311	83	.length = SZ_4K,
705630db	84	.type = MT_DEVICE,
8dd52311	85	},
7efb833d BD	86	};
	87
	88	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	89	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	90	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	91
	92	static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	93	[0] = {
	94	.name = "uclk",
	95	.divisor = 1,
	96	.min_baud = 0,
	97	.max_baud = 0,
	98	},
	99	[1] = {
	100	.name = "pclk",
	101	.divisor = 1,
	102	.min_baud = 0,
705630db	103	.max_baud = 0,
7efb833d BD	104	}
	105	};
	106
	107
66a9b49a	108	static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
7efb833d BD	109	[0] = {
	110	.hwport = 0,
	111	.flags = 0,
	112	.ucon = UCON,
	113	.ulcon = ULCON,
	114	.ufcon = UFCON,
	115	.clocks = anubis_serial_clocks,
705630db	116	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	117	},
	118	[1] = {
	119	.hwport = 2,
	120	.flags = 0,
	121	.ucon = UCON,
	122	.ulcon = ULCON,
	123	.ufcon = UFCON,
	124	.clocks = anubis_serial_clocks,
705630db	125	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	126	},
	127	};
	128
	129	/* NAND Flash on Anubis board */
	130
	131	static int external_map[] = { 2 };
	132	static int chip0_map[] = { 0 };
	133	static int chip1_map[] = { 1 };
	134
9f693d7b	135	static struct mtd_partition anubis_default_nand_part[] = {
7efb833d BD	136	[0] = {
	137	.name = "Boot Agent",
	138	.size = SZ_16K,
705630db	139	.offset = 0,
7efb833d BD	140	},
	141	[1] = {
	142	.name = "/boot",
	143	.size = SZ_4M - SZ_16K,
	144	.offset = SZ_16K,
	145	},
	146	[2] = {
	147	.name = "user1",
	148	.offset = SZ_4M,
	149	.size = SZ_32M - SZ_4M,
	150	},
	151	[3] = {
	152	.name = "user2",
	153	.offset = SZ_32M,
	154	.size = MTDPART_SIZ_FULL,
	155	}
	156	};
	157
	158	/* the Anubis has 3 selectable slots for nand-flash, the two
	159	* on-board chip areas, as well as the external slot.
	160	*
	161	* Note, there is no current hot-plug support for the External
	162	* socket.
	163	*/
	164
	165	static struct s3c2410_nand_set anubis_nand_sets[] = {
	166	[1] = {
	167	.name = "External",
	168	.nr_chips = 1,
	169	.nr_map = external_map,
	170	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	171	.partitions = anubis_default_nand_part,
7efb833d BD	172	},
	173	[0] = {
	174	.name = "chip0",
	175	.nr_chips = 1,
	176	.nr_map = chip0_map,
	177	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	178	.partitions = anubis_default_nand_part,
7efb833d BD	179	},
	180	[2] = {
	181	.name = "chip1",
	182	.nr_chips = 1,
	183	.nr_map = chip1_map,
	184	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	185	.partitions = anubis_default_nand_part,
7efb833d BD	186	},
	187	};
	188
	189	static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
	190	{
	191	unsigned int tmp;
	192
	193	slot = set->nr_map[slot] & 3;
	194
	195	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
	196	slot, set, set->nr_map);
	197
	198	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	199	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	200	tmp \|= slot;
	201
	202	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
	203
	204	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
	205	}
	206
	207	static struct s3c2410_platform_nand anubis_nand_info = {
	208	.tacls = 25,
661e6acf BD	209	.twrph0 = 55,
661e6acf BD	210	.twrph1 = 40,
7efb833d BD	211	.nr_sets = ARRAY_SIZE(anubis_nand_sets),
	212	.sets = anubis_nand_sets,
	213	.select_chip = anubis_nand_select,
	214	};
	215
bf1c56a3 BD	216	/* IDE channels */
	217
	218	static struct resource anubis_ide0_resource[] = {
	219	{
	220	.start = S3C2410_CS3,
	221	.end = S3C2410_CS3 + (8*32) - 1,
	222	.flags = IORESOURCE_MEM,
	223	}, {
	224	.start = S3C2410_CS3 + (1<<26),
	225	.end = S3C2410_CS3 + (1<<26) + (8*32) - 1,
	226	.flags = IORESOURCE_MEM,
	227	}, {
	228	.start = IRQ_IDE0,
	229	.end = IRQ_IDE0,
	230	.flags = IORESOURCE_IRQ,
	231	},
	232	};
	233
	234	static struct platform_device anubis_device_ide0 = {
	235	.name = "simtec-ide",
	236	.id = 0,
	237	.num_resources = ARRAY_SIZE(anubis_ide0_resource),
	238	.resource = anubis_ide0_resource,
	239	};
	240
	241	static struct resource anubis_ide1_resource[] = {
	242	{
	243	.start = S3C2410_CS4,
	244	.end = S3C2410_CS4 + (8*32) - 1,
	245	.flags = IORESOURCE_MEM,
	246	}, {
	247	.start = S3C2410_CS4 + (1<<26),
	248	.end = S3C2410_CS4 + (1<<26) + (8*32) - 1,
	249	.flags = IORESOURCE_MEM,
	250	}, {
	251	.start = IRQ_IDE0,
	252	.end = IRQ_IDE0,
	253	.flags = IORESOURCE_IRQ,
	254	},
	255	};
	256
	257
	258	static struct platform_device anubis_device_ide1 = {
	259	.name = "simtec-ide",
	260	.id = 1,
	261	.num_resources = ARRAY_SIZE(anubis_ide1_resource),
	262	.resource = anubis_ide1_resource,
	263	};
7efb833d	264
eac1d8da BD	265	/* Asix AX88796 10/100 ethernet controller */
	266
	267	static struct ax_plat_data anubis_asix_platdata = {
	268	.flags = AXFLG_MAC_FROMDEV,
	269	.wordlength = 2,
	270	.dcr_val = 0x48,
	271	.rcr_val = 0x40,
	272	};
	273
	274	static struct resource anubis_asix_resource[] = {
	275	[0] = {
	276	.start = S3C2410_CS5,
	277	.end = S3C2410_CS5 + (0x20 * 0x20) -1,
	278	.flags = IORESOURCE_MEM
	279	},
	280	[1] = {
	281	.start = IRQ_ASIX,
	282	.end = IRQ_ASIX,
	283	.flags = IORESOURCE_IRQ
	284	}
	285	};
	286
	287	static struct platform_device anubis_device_asix = {
	288	.name = "ax88796",
	289	.id = 0,
	290	.num_resources = ARRAY_SIZE(anubis_asix_resource),
	291	.resource = anubis_asix_resource,
	292	.dev = {
	293	.platform_data = &anubis_asix_platdata,
	294	}
	295	};
	296
7efb833d BD	297	/* Standard Anubis devices */
	298
	299	static struct platform_device *anubis_devices[] __initdata = {
	300	&s3c_device_usb,
	301	&s3c_device_wdt,
	302	&s3c_device_adc,
	303	&s3c_device_i2c,
	304	&s3c_device_rtc,
	305	&s3c_device_nand,
bf1c56a3 BD	306	&anubis_device_ide0,
bf1c56a3 BD	307	&anubis_device_ide1,
eac1d8da	308	&anubis_device_asix,
7efb833d BD	309	};
	310
	311	static struct clk *anubis_clocks[] = {
	312	&s3c24xx_dclk0,
	313	&s3c24xx_dclk1,
	314	&s3c24xx_clkout0,
	315	&s3c24xx_clkout1,
	316	&s3c24xx_uclk,
	317	};
	318
5fe10ab1	319	static void __init anubis_map_io(void)
7efb833d BD	320	{
	321	/* initialise the clocks */
	322
	323	s3c24xx_dclk0.parent = NULL;
	324	s3c24xx_dclk0.rate = 1210001000;
	325
	326	s3c24xx_dclk1.parent = NULL;
	327	s3c24xx_dclk1.rate = 2410001000;
	328
	329	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	330	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	331
	332	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	333
ce89c206 BD	334	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
ce89c206 BD	335
7efb833d BD	336	s3c_device_nand.dev.platform_data = &anubis_nand_info;
	337
	338	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	339	s3c24xx_init_clocks(0);
	340	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
7efb833d BD	341
	342	/* ensure that the GPIO is setup */
	343	s3c2410_gpio_setpin(S3C2410_GPA0, 1);
	344	}
	345
57e5171c BD	346	static void __init anubis_init(void)
	347	{
	348	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
	349	}
	350
	351
7efb833d BD	352	MACHINE_START(ANUBIS, "Simtec-Anubis")
7efb833d BD	353	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
7efb833d BD	354	.phys_io = S3C2410_PA_UART,
	355	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	356	.boot_params = S3C2410_SDRAM_PA + 0x100,
	357	.map_io = anubis_map_io,
57e5171c	358	.init_machine = anubis_init,
7efb833d BD	359	.init_irq = s3c24xx_init_irq,
	360	.timer = &s3c24xx_timer,
	361	MACHINE_END