[deliverable/linux.git] / arch / arm / mach-s3c2440 / mach-osiris.c

/* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
 * Copyright (c) 2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/clk.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/arch/osiris-map.h>
#include <asm/arch/osiris-cpld.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <asm/plat-s3c/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>
#include <asm/plat-s3c/nand.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>

/* onboard perihperal map */

static struct map_desc osiris_iodesc[] __initdata = {
  /* ISA IO areas (may be over-written later) */

  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },

  /* CPLD control registers */

  {
	  .virtual	= (u32)OSIRIS_VA_CTRL0,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL1,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL2,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_IDREG,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};

static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	}
};

/* NAND Flash on Osiris board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition osiris_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition osiris_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Osiris has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set osiris_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
};

static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(OSIRIS_VA_CTRL0);
	tmp &= ~OSIRIS_CTRL0_NANDSEL;
	tmp |= slot;

	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}

static struct s3c2410_platform_nand osiris_nand_info = {
	.tacls		= 25,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(osiris_nand_sets),
	.sets		= osiris_nand_sets,
	.select_chip	= osiris_nand_select,
};

/* PCMCIA control and configuration */

static struct resource osiris_pcmcia_resource[] = {
	[0] = {
		.start	= 0x0f000000,
		.end	= 0x0f100000,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 0x0c000000,
		.end	= 0x0c100000,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device osiris_pcmcia = {
	.name		= "osiris-pcmcia",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(osiris_pcmcia_resource),
	.resource	= osiris_pcmcia_resource,
};

/* Osiris power management device */

#ifdef CONFIG_PM
static unsigned char pm_osiris_ctrl0;

static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	unsigned int tmp;

	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;

	/* ensure correct NAND slot is selected on resume */
	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	        tmp |= 2;

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);

	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA21, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);

	return 0;
}

static int osiris_pm_resume(struct sys_device *sd)
{
	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
		__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);

	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);

	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);

	return 0;
}

#else
#define osiris_pm_suspend NULL
#define osiris_pm_resume NULL
#endif

static struct sysdev_class osiris_pm_sysclass = {
	.name		= "mach-osiris",
	.suspend	= osiris_pm_suspend,
	.resume		= osiris_pm_resume,
};

static struct sys_device osiris_pm_sysdev = {
	.cls		= &osiris_pm_sysclass,
};

/* Standard Osiris devices */

static struct platform_device *osiris_devices[] __initdata = {
	&s3c_device_i2c,
	&s3c_device_wdt,
	&s3c_device_nand,
	&osiris_pcmcia,
};

static struct clk *osiris_clocks[] = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static void __init osiris_map_io(void)
{
	unsigned long flags;

	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));

	s3c_device_nand.dev.platform_data = &osiris_nand_info;

	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
		printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
		       __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
		osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
		osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	} else {
		/* write-protect line to the NAND */
		s3c2410_gpio_setpin(S3C2410_GPA0, 1);
	}

	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */

	local_irq_save(flags);
	__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
	local_irq_restore(flags);
}

static void __init osiris_init(void)
{
	sysdev_class_register(&osiris_pm_sysclass);
	sysdev_register(&osiris_pm_sysdev);

	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
};

MACHINE_START(OSIRIS, "Simtec-OSIRIS")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= osiris_map_io,
	.init_machine	= osiris_init,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= osiris_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-osiris.c
110d322b BD	2	*
	3	* Copyright (c) 2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
	18	#include <linux/device.h>
5698bd28	19	#include <linux/sysdev.h>
b6d1f542	20	#include <linux/serial_core.h>
d96a9804	21	#include <linux/clk.h>
110d322b BD	22
	23	#include <asm/mach/arch.h>
	24	#include <asm/mach/map.h>
	25	#include <asm/mach/irq.h>
	26
	27	#include <asm/arch/osiris-map.h>
	28	#include <asm/arch/osiris-cpld.h>
	29
	30	#include <asm/hardware.h>
	31	#include <asm/io.h>
	32	#include <asm/irq.h>
	33	#include <asm/mach-types.h>
	34
531b617c	35	#include <asm/plat-s3c/regs-serial.h>
110d322b BD	36	#include <asm/arch/regs-gpio.h>
	37	#include <asm/arch/regs-mem.h>
	38	#include <asm/arch/regs-lcd.h>
531b617c	39	#include <asm/plat-s3c/nand.h>
110d322b BD	40
	41	#include <linux/mtd/mtd.h>
	42	#include <linux/mtd/nand.h>
	43	#include <linux/mtd/nand_ecc.h>
	44	#include <linux/mtd/partitions.h>
	45
a21765a7 BD	46	#include <asm/plat-s3c24xx/clock.h>
	47	#include <asm/plat-s3c24xx/devs.h>
	48	#include <asm/plat-s3c24xx/cpu.h>
110d322b	49
6cbdc8c5	50	/* onboard perihperal map */
110d322b BD	51
	52	static struct map_desc osiris_iodesc[] __initdata = {
	53	/* ISA IO areas (may be over-written later) */
	54
	55	{
	56	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	57	.pfn = __phys_to_pfn(S3C2410_CS5),
	58	.length = SZ_16M,
	59	.type = MT_DEVICE,
	60	}, {
	61	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	62	.pfn = __phys_to_pfn(S3C2410_CS5),
	63	.length = SZ_16M,
	64	.type = MT_DEVICE,
	65	},
	66
	67	/* CPLD control registers */
	68
	69	{
c362aecd BD	70	.virtual = (u32)OSIRIS_VA_CTRL0,
	71	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
	72	.length = SZ_16K,
	73	.type = MT_DEVICE,
	74	}, {
110d322b BD	75	.virtual = (u32)OSIRIS_VA_CTRL1,
	76	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
	77	.length = SZ_16K,
705630db	78	.type = MT_DEVICE,
110d322b BD	79	}, {
	80	.virtual = (u32)OSIRIS_VA_CTRL2,
	81	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
	82	.length = SZ_16K,
705630db	83	.type = MT_DEVICE,
c362aecd BD	84	}, {
	85	.virtual = (u32)OSIRIS_VA_IDREG,
	86	.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
	87	.length = SZ_16K,
	88	.type = MT_DEVICE,
110d322b BD	89	},
	90	};
	91
	92	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	93	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	94	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	95
	96	static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	97	[0] = {
	98	.name = "uclk",
	99	.divisor = 1,
	100	.min_baud = 0,
	101	.max_baud = 0,
	102	},
	103	[1] = {
	104	.name = "pclk",
	105	.divisor = 1,
	106	.min_baud = 0,
705630db	107	.max_baud = 0,
110d322b BD	108	}
	109	};
	110
66a9b49a	111	static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
110d322b BD	112	[0] = {
	113	.hwport = 0,
	114	.flags = 0,
	115	.ucon = UCON,
	116	.ulcon = ULCON,
	117	.ufcon = UFCON,
	118	.clocks = osiris_serial_clocks,
705630db	119	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b BD	120	},
110d322b BD	121	[1] = {
e2e5810f	122	.hwport = 1,
110d322b BD	123	.flags = 0,
	124	.ucon = UCON,
	125	.ulcon = ULCON,
	126	.ufcon = UFCON,
	127	.clocks = osiris_serial_clocks,
705630db	128	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b	129	},
ca7aa4de BD	130	[2] = {
	131	.hwport = 2,
	132	.flags = 0,
	133	.ucon = UCON,
	134	.ulcon = ULCON,
	135	.ufcon = UFCON,
	136	.clocks = osiris_serial_clocks,
	137	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	138	}
110d322b BD	139	};
	140
	141	/* NAND Flash on Osiris board */
	142
	143	static int external_map[] = { 2 };
	144	static int chip0_map[] = { 0 };
	145	static int chip1_map[] = { 1 };
	146
da956fd6	147	static struct mtd_partition osiris_default_nand_part[] = {
110d322b BD	148	[0] = {
	149	.name = "Boot Agent",
	150	.size = SZ_16K,
705630db	151	.offset = 0,
110d322b BD	152	},
	153	[1] = {
	154	.name = "/boot",
	155	.size = SZ_4M - SZ_16K,
	156	.offset = SZ_16K,
	157	},
	158	[2] = {
	159	.name = "user1",
	160	.offset = SZ_4M,
	161	.size = SZ_32M - SZ_4M,
	162	},
	163	[3] = {
	164	.name = "user2",
	165	.offset = SZ_32M,
	166	.size = MTDPART_SIZ_FULL,
	167	}
	168	};
	169
3c3e69cd BD	170	static struct mtd_partition osiris_default_nand_part_large[] = {
	171	[0] = {
	172	.name = "Boot Agent",
	173	.size = SZ_128K,
	174	.offset = 0,
	175	},
	176	[1] = {
	177	.name = "/boot",
	178	.size = SZ_4M - SZ_128K,
	179	.offset = SZ_128K,
	180	},
	181	[2] = {
	182	.name = "user1",
	183	.offset = SZ_4M,
	184	.size = SZ_32M - SZ_4M,
	185	},
	186	[3] = {
	187	.name = "user2",
	188	.offset = SZ_32M,
	189	.size = MTDPART_SIZ_FULL,
	190	}
	191	};
	192
110d322b BD	193	/* the Osiris has 3 selectable slots for nand-flash, the two
	194	* on-board chip areas, as well as the external slot.
	195	*
	196	* Note, there is no current hot-plug support for the External
	197	* socket.
	198	*/
	199
	200	static struct s3c2410_nand_set osiris_nand_sets[] = {
	201	[1] = {
	202	.name = "External",
	203	.nr_chips = 1,
	204	.nr_map = external_map,
	205	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	206	.partitions = osiris_default_nand_part,
110d322b BD	207	},
	208	[0] = {
	209	.name = "chip0",
	210	.nr_chips = 1,
	211	.nr_map = chip0_map,
	212	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	213	.partitions = osiris_default_nand_part,
110d322b BD	214	},
	215	[2] = {
	216	.name = "chip1",
	217	.nr_chips = 1,
	218	.nr_map = chip1_map,
	219	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	220	.partitions = osiris_default_nand_part,
110d322b BD	221	},
	222	};
	223
	224	static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
	225	{
	226	unsigned int tmp;
	227
	228	slot = set->nr_map[slot] & 3;
	229
	230	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
	231	slot, set, set->nr_map);
	232
c362aecd BD	233	tmp = __raw_readb(OSIRIS_VA_CTRL0);
c362aecd BD	234	tmp &= ~OSIRIS_CTRL0_NANDSEL;
110d322b BD	235	tmp \|= slot;
110d322b BD	236
c362aecd	237	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
110d322b	238
c362aecd	239	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
110d322b BD	240	}
	241
	242	static struct s3c2410_platform_nand osiris_nand_info = {
	243	.tacls = 25,
	244	.twrph0 = 60,
	245	.twrph1 = 60,
	246	.nr_sets = ARRAY_SIZE(osiris_nand_sets),
	247	.sets = osiris_nand_sets,
	248	.select_chip = osiris_nand_select,
	249	};
	250
	251	/* PCMCIA control and configuration */
	252
	253	static struct resource osiris_pcmcia_resource[] = {
	254	[0] = {
	255	.start = 0x0f000000,
	256	.end = 0x0f100000,
	257	.flags = IORESOURCE_MEM,
	258	},
	259	[1] = {
	260	.start = 0x0c000000,
	261	.end = 0x0c100000,
	262	.flags = IORESOURCE_MEM,
	263	}
	264	};
	265
	266	static struct platform_device osiris_pcmcia = {
	267	.name = "osiris-pcmcia",
	268	.id = -1,
	269	.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
	270	.resource = osiris_pcmcia_resource,
	271	};
	272
5698bd28 BD	273	/* Osiris power management device */
	274
	275	#ifdef CONFIG_PM
	276	static unsigned char pm_osiris_ctrl0;
	277
	278	static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
	279	{
28047ece BD	280	unsigned int tmp;
28047ece BD	281
5698bd28	282	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
28047ece BD	283	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
	284
	285	/* ensure correct NAND slot is selected on resume */
	286	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	287	tmp \|= 2;
	288
	289	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
	290
4afcddae BD	291	/* ensure that an nRESET is not generated on resume. */
	292	s3c2410_gpio_setpin(S3C2410_GPA21, 1);
	293	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
	294
5698bd28 BD	295	return 0;
	296	}
	297
	298	static int osiris_pm_resume(struct sys_device *sd)
	299	{
	300	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
	301	__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
	302
28047ece BD	303	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
28047ece BD	304
4afcddae BD	305	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
4afcddae BD	306
5698bd28 BD	307	return 0;
	308	}
	309
	310	#else
	311	#define osiris_pm_suspend NULL
	312	#define osiris_pm_resume NULL
	313	#endif
	314
	315	static struct sysdev_class osiris_pm_sysclass = {
af5ca3f4	316	.name = "mach-osiris",
5698bd28 BD	317	.suspend = osiris_pm_suspend,
	318	.resume = osiris_pm_resume,
	319	};
	320
	321	static struct sys_device osiris_pm_sysdev = {
	322	.cls = &osiris_pm_sysclass,
	323	};
	324
110d322b BD	325	/* Standard Osiris devices */
	326
	327	static struct platform_device *osiris_devices[] __initdata = {
	328	&s3c_device_i2c,
55ba86bc	329	&s3c_device_wdt,
110d322b BD	330	&s3c_device_nand,
	331	&osiris_pcmcia,
	332	};
	333
	334	static struct clk *osiris_clocks[] = {
	335	&s3c24xx_dclk0,
	336	&s3c24xx_dclk1,
	337	&s3c24xx_clkout0,
	338	&s3c24xx_clkout1,
	339	&s3c24xx_uclk,
	340	};
	341
da956fd6	342	static void __init osiris_map_io(void)
110d322b	343	{
da956fd6 BD	344	unsigned long flags;
da956fd6 BD	345
110d322b BD	346	/* initialise the clocks */
110d322b BD	347
d96a9804	348	s3c24xx_dclk0.parent = &clk_upll;
110d322b BD	349	s3c24xx_dclk0.rate = 1210001000;
110d322b BD	350
d96a9804	351	s3c24xx_dclk1.parent = &clk_upll;
110d322b BD	352	s3c24xx_dclk1.rate = 2410001000;
	353
	354	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	355	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	356
	357	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	358
ce89c206 BD	359	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
ce89c206 BD	360
110d322b BD	361	s3c_device_nand.dev.platform_data = &osiris_nand_info;
	362
	363	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	364	s3c24xx_init_clocks(0);
	365	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
110d322b	366
3c3e69cd BD	367	/* check for the newer revision boards with large page nand */
	368
	369	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
	370	printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
	371	__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
	372	osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
	373	osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	374	} else {
	375	/* write-protect line to the NAND */
	376	s3c2410_gpio_setpin(S3C2410_GPA0, 1);
	377	}
	378
110d322b	379	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
da956fd6 BD	380
da956fd6 BD	381	local_irq_save(flags);
110d322b	382	__raw_writel(__raw_readl(S3C2410_BWSCON) \| S3C2410_BWSCON_ST1 \| S3C2410_BWSCON_ST2 \| S3C2410_BWSCON_ST3 \| S3C2410_BWSCON_ST4 \| S3C2410_BWSCON_ST5, S3C2410_BWSCON);
da956fd6	383	local_irq_restore(flags);
110d322b BD	384	}
110d322b BD	385
57e5171c BD	386	static void __init osiris_init(void)
57e5171c BD	387	{
5698bd28 BD	388	sysdev_class_register(&osiris_pm_sysclass);
	389	sysdev_register(&osiris_pm_sysdev);
	390
57e5171c BD	391	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
	392	};
	393
110d322b BD	394	MACHINE_START(OSIRIS, "Simtec-OSIRIS")
110d322b BD	395	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
110d322b BD	396	.phys_io = S3C2410_PA_UART,
	397	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	398	.boot_params = S3C2410_SDRAM_PA + 0x100,
	399	.map_io = osiris_map_io,
57e5171c	400	.init_machine = osiris_init,
110d322b	401	.init_irq = s3c24xx_init_irq,
5698bd28	402	.init_machine = osiris_init,
110d322b BD	403	.timer = &s3c24xx_timer,
110d322b BD	404	MACHINE_END