[deliverable/linux.git] / arch / arm / mach-s3c2440 / mach-osiris.c

/* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
 * Copyright (c) 2005-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <linux/i2c/tps65010.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/osiris-map.h>
#include <mach/osiris-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

/* onboard perihperal map */

static struct map_desc osiris_iodesc[] __initdata = {
  /* ISA IO areas (may be over-written later) */

  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },

  /* CPLD control registers */

  {
	  .virtual	= (u32)OSIRIS_VA_CTRL0,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL1,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL2,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_IDREG,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};

static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	}
};

/* NAND Flash on Osiris board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition osiris_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition osiris_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Osiris has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set osiris_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
};

static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(OSIRIS_VA_CTRL0);
	tmp &= ~OSIRIS_CTRL0_NANDSEL;
	tmp |= slot;

	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}

static struct s3c2410_platform_nand osiris_nand_info = {
	.tacls		= 25,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(osiris_nand_sets),
	.sets		= osiris_nand_sets,
	.select_chip	= osiris_nand_select,
};

/* PCMCIA control and configuration */

static struct resource osiris_pcmcia_resource[] = {
	[0] = {
		.start	= 0x0f000000,
		.end	= 0x0f100000,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 0x0c000000,
		.end	= 0x0c100000,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device osiris_pcmcia = {
	.name		= "osiris-pcmcia",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(osiris_pcmcia_resource),
	.resource	= osiris_pcmcia_resource,
};

/* Osiris power management device */

#ifdef CONFIG_PM
static unsigned char pm_osiris_ctrl0;

static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	unsigned int tmp;

	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;

	/* ensure correct NAND slot is selected on resume */
	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	        tmp |= 2;

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);

	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);

	return 0;
}

static int osiris_pm_resume(struct sys_device *sd)
{
	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
		__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);

	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);

	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);

	return 0;
}

#else
#define osiris_pm_suspend NULL
#define osiris_pm_resume NULL
#endif

static struct sysdev_class osiris_pm_sysclass = {
	.name		= "mach-osiris",
	.suspend	= osiris_pm_suspend,
	.resume		= osiris_pm_resume,
};

static struct sys_device osiris_pm_sysdev = {
	.cls		= &osiris_pm_sysclass,
};

/* Link for DVS driver to TPS65011 */

static void osiris_tps_release(struct device *dev)
{
	/* static device, do not need to release anything */
}

static struct platform_device osiris_tps_device = {
	.name	= "osiris-dvs",
	.id	= -1,
	.dev.release = osiris_tps_release,
};

static int osiris_tps_setup(struct i2c_client *client, void *context)
{
	osiris_tps_device.dev.parent = &client->dev;
	return platform_device_register(&osiris_tps_device);
}

static int osiris_tps_remove(struct i2c_client *client, void *context)
{
	platform_device_unregister(&osiris_tps_device);
	return 0;
}

static struct tps65010_board osiris_tps_board = {
	.base		= -1,	/* GPIO can go anywhere at the moment */
	.setup		= osiris_tps_setup,
	.teardown	= osiris_tps_remove,
};

/* I2C devices fitted. */

static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
		.platform_data = &osiris_tps_board,
	},
};

/* Standard Osiris devices */

static struct platform_device *osiris_devices[] __initdata = {
	&s3c_device_i2c0,
	&s3c_device_wdt,
	&s3c_device_nand,
	&osiris_pcmcia,
};

static struct clk *osiris_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	.refresh	= 7800, /* refresh period is 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static void __init osiris_map_io(void)
{
	unsigned long flags;

	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));

	s3c_device_nand.dev.platform_data = &osiris_nand_info;

	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
		printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
		       __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
		osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
		osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	} else {
		/* write-protect line to the NAND */
		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
	}

	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */

	local_irq_save(flags);
	__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
	local_irq_restore(flags);
}

static void __init osiris_init(void)
{
	sysdev_class_register(&osiris_pm_sysclass);
	sysdev_register(&osiris_pm_sysdev);

	s3c_i2c0_set_platdata(NULL);

	s3c_cpufreq_setboard(&osiris_cpufreq);

	i2c_register_board_info(0, osiris_i2c_devs,
				ARRAY_SIZE(osiris_i2c_devs));

	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
};

MACHINE_START(OSIRIS, "Simtec-OSIRIS")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= osiris_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= osiris_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-osiris.c
110d322b	2	*
ccae941e	3	* Copyright (c) 2005-2008 Simtec Electronics
110d322b BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
110d322b	19	#include <linux/device.h>
5698bd28	20	#include <linux/sysdev.h>
b6d1f542	21	#include <linux/serial_core.h>
d96a9804	22	#include <linux/clk.h>
f3374221	23	#include <linux/i2c.h>
fced80c7	24	#include <linux/io.h>
110d322b	25
4fa084af BD	26	#include <linux/i2c/tps65010.h>
4fa084af BD	27
110d322b BD	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/irq.h>
	31
a09e64fb RK	32	#include <mach/osiris-map.h>
a09e64fb RK	33	#include <mach/osiris-cpld.h>
110d322b	34
a09e64fb	35	#include <mach/hardware.h>
110d322b BD	36	#include <asm/irq.h>
	37	#include <asm/mach-types.h>
	38
baf6b281	39	#include <plat/cpu-freq.h>
a2b7ba9c	40	#include <plat/regs-serial.h>
a09e64fb RK	41	#include <mach/regs-gpio.h>
	42	#include <mach/regs-mem.h>
	43	#include <mach/regs-lcd.h>
7926b5a3	44	#include <plat/nand.h>
3e1b776c	45	#include <plat/iic.h>
110d322b BD	46
	47	#include <linux/mtd/mtd.h>
	48	#include <linux/mtd/nand.h>
	49	#include <linux/mtd/nand_ecc.h>
	50	#include <linux/mtd/partitions.h>
	51
d5120ae7	52	#include <plat/clock.h>
a2b7ba9c BD	53	#include <plat/devs.h>
a2b7ba9c BD	54	#include <plat/cpu.h>
110d322b	55
6cbdc8c5	56	/* onboard perihperal map */
110d322b BD	57
	58	static struct map_desc osiris_iodesc[] __initdata = {
	59	/* ISA IO areas (may be over-written later) */
	60
	61	{
	62	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	63	.pfn = __phys_to_pfn(S3C2410_CS5),
	64	.length = SZ_16M,
	65	.type = MT_DEVICE,
	66	}, {
	67	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	68	.pfn = __phys_to_pfn(S3C2410_CS5),
	69	.length = SZ_16M,
	70	.type = MT_DEVICE,
	71	},
	72
	73	/* CPLD control registers */
	74
	75	{
c362aecd BD	76	.virtual = (u32)OSIRIS_VA_CTRL0,
	77	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
	78	.length = SZ_16K,
	79	.type = MT_DEVICE,
	80	}, {
110d322b BD	81	.virtual = (u32)OSIRIS_VA_CTRL1,
	82	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
	83	.length = SZ_16K,
705630db	84	.type = MT_DEVICE,
110d322b BD	85	}, {
	86	.virtual = (u32)OSIRIS_VA_CTRL2,
	87	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
	88	.length = SZ_16K,
705630db	89	.type = MT_DEVICE,
c362aecd BD	90	}, {
	91	.virtual = (u32)OSIRIS_VA_IDREG,
	92	.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
	93	.length = SZ_16K,
	94	.type = MT_DEVICE,
110d322b BD	95	},
	96	};
	97
	98	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	99	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	100	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	101
	102	static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	103	[0] = {
	104	.name = "uclk",
	105	.divisor = 1,
	106	.min_baud = 0,
	107	.max_baud = 0,
	108	},
	109	[1] = {
	110	.name = "pclk",
	111	.divisor = 1,
	112	.min_baud = 0,
705630db	113	.max_baud = 0,
110d322b BD	114	}
	115	};
	116
66a9b49a	117	static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
110d322b BD	118	[0] = {
	119	.hwport = 0,
	120	.flags = 0,
	121	.ucon = UCON,
	122	.ulcon = ULCON,
	123	.ufcon = UFCON,
	124	.clocks = osiris_serial_clocks,
705630db	125	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b BD	126	},
110d322b BD	127	[1] = {
e2e5810f	128	.hwport = 1,
110d322b BD	129	.flags = 0,
	130	.ucon = UCON,
	131	.ulcon = ULCON,
	132	.ufcon = UFCON,
	133	.clocks = osiris_serial_clocks,
705630db	134	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b	135	},
ca7aa4de BD	136	[2] = {
	137	.hwport = 2,
	138	.flags = 0,
	139	.ucon = UCON,
	140	.ulcon = ULCON,
	141	.ufcon = UFCON,
	142	.clocks = osiris_serial_clocks,
	143	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	144	}
110d322b BD	145	};
	146
	147	/* NAND Flash on Osiris board */
	148
	149	static int external_map[] = { 2 };
	150	static int chip0_map[] = { 0 };
	151	static int chip1_map[] = { 1 };
	152
da956fd6	153	static struct mtd_partition osiris_default_nand_part[] = {
110d322b BD	154	[0] = {
	155	.name = "Boot Agent",
	156	.size = SZ_16K,
705630db	157	.offset = 0,
110d322b BD	158	},
	159	[1] = {
	160	.name = "/boot",
	161	.size = SZ_4M - SZ_16K,
	162	.offset = SZ_16K,
	163	},
	164	[2] = {
	165	.name = "user1",
	166	.offset = SZ_4M,
	167	.size = SZ_32M - SZ_4M,
	168	},
	169	[3] = {
	170	.name = "user2",
	171	.offset = SZ_32M,
	172	.size = MTDPART_SIZ_FULL,
	173	}
	174	};
	175
3c3e69cd BD	176	static struct mtd_partition osiris_default_nand_part_large[] = {
	177	[0] = {
	178	.name = "Boot Agent",
	179	.size = SZ_128K,
	180	.offset = 0,
	181	},
	182	[1] = {
	183	.name = "/boot",
	184	.size = SZ_4M - SZ_128K,
	185	.offset = SZ_128K,
	186	},
	187	[2] = {
	188	.name = "user1",
	189	.offset = SZ_4M,
	190	.size = SZ_32M - SZ_4M,
	191	},
	192	[3] = {
	193	.name = "user2",
	194	.offset = SZ_32M,
	195	.size = MTDPART_SIZ_FULL,
	196	}
	197	};
	198
110d322b BD	199	/* the Osiris has 3 selectable slots for nand-flash, the two
	200	* on-board chip areas, as well as the external slot.
	201	*
	202	* Note, there is no current hot-plug support for the External
	203	* socket.
	204	*/
	205
	206	static struct s3c2410_nand_set osiris_nand_sets[] = {
	207	[1] = {
	208	.name = "External",
	209	.nr_chips = 1,
	210	.nr_map = external_map,
	211	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	212	.partitions = osiris_default_nand_part,
110d322b BD	213	},
	214	[0] = {
	215	.name = "chip0",
	216	.nr_chips = 1,
	217	.nr_map = chip0_map,
	218	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	219	.partitions = osiris_default_nand_part,
110d322b BD	220	},
	221	[2] = {
	222	.name = "chip1",
	223	.nr_chips = 1,
	224	.nr_map = chip1_map,
	225	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	226	.partitions = osiris_default_nand_part,
110d322b BD	227	},
	228	};
	229
	230	static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
	231	{
	232	unsigned int tmp;
	233
	234	slot = set->nr_map[slot] & 3;
	235
	236	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
	237	slot, set, set->nr_map);
	238
c362aecd BD	239	tmp = __raw_readb(OSIRIS_VA_CTRL0);
c362aecd BD	240	tmp &= ~OSIRIS_CTRL0_NANDSEL;
110d322b BD	241	tmp \|= slot;
110d322b BD	242
c362aecd	243	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
110d322b	244
c362aecd	245	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
110d322b BD	246	}
	247
	248	static struct s3c2410_platform_nand osiris_nand_info = {
	249	.tacls = 25,
	250	.twrph0 = 60,
	251	.twrph1 = 60,
	252	.nr_sets = ARRAY_SIZE(osiris_nand_sets),
	253	.sets = osiris_nand_sets,
	254	.select_chip = osiris_nand_select,
	255	};
	256
	257	/* PCMCIA control and configuration */
	258
	259	static struct resource osiris_pcmcia_resource[] = {
	260	[0] = {
	261	.start = 0x0f000000,
	262	.end = 0x0f100000,
	263	.flags = IORESOURCE_MEM,
	264	},
	265	[1] = {
	266	.start = 0x0c000000,
	267	.end = 0x0c100000,
	268	.flags = IORESOURCE_MEM,
	269	}
	270	};
	271
	272	static struct platform_device osiris_pcmcia = {
	273	.name = "osiris-pcmcia",
	274	.id = -1,
	275	.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
	276	.resource = osiris_pcmcia_resource,
	277	};
	278
5698bd28 BD	279	/* Osiris power management device */
	280
	281	#ifdef CONFIG_PM
	282	static unsigned char pm_osiris_ctrl0;
	283
	284	static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
	285	{
28047ece BD	286	unsigned int tmp;
28047ece BD	287
5698bd28	288	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
28047ece BD	289	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
	290
	291	/* ensure correct NAND slot is selected on resume */
	292	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	293	tmp \|= 2;
	294
	295	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
	296
4afcddae	297	/* ensure that an nRESET is not generated on resume. */
070276d5 BD	298	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
070276d5 BD	299	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
4afcddae	300
5698bd28 BD	301	return 0;
	302	}
	303
	304	static int osiris_pm_resume(struct sys_device *sd)
	305	{
	306	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
	307	__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
	308
28047ece BD	309	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
28047ece BD	310
070276d5	311	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
4afcddae	312
5698bd28 BD	313	return 0;
	314	}
	315
	316	#else
	317	#define osiris_pm_suspend NULL
	318	#define osiris_pm_resume NULL
	319	#endif
	320
	321	static struct sysdev_class osiris_pm_sysclass = {
af5ca3f4	322	.name = "mach-osiris",
5698bd28 BD	323	.suspend = osiris_pm_suspend,
	324	.resume = osiris_pm_resume,
	325	};
	326
	327	static struct sys_device osiris_pm_sysdev = {
	328	.cls = &osiris_pm_sysclass,
	329	};
	330
4fa084af BD	331	/* Link for DVS driver to TPS65011 */
	332
	333	static void osiris_tps_release(struct device *dev)
	334	{
	335	/* static device, do not need to release anything */
	336	}
	337
	338	static struct platform_device osiris_tps_device = {
	339	.name = "osiris-dvs",
	340	.id = -1,
	341	.dev.release = osiris_tps_release,
	342	};
	343
	344	static int osiris_tps_setup(struct i2c_client client, void context)
	345	{
	346	osiris_tps_device.dev.parent = &client->dev;
	347	return platform_device_register(&osiris_tps_device);
	348	}
	349
	350	static int osiris_tps_remove(struct i2c_client client, void context)
	351	{
	352	platform_device_unregister(&osiris_tps_device);
	353	return 0;
	354	}
	355
	356	static struct tps65010_board osiris_tps_board = {
	357	.base = -1, /* GPIO can go anywhere at the moment */
	358	.setup = osiris_tps_setup,
	359	.teardown = osiris_tps_remove,
	360	};
	361
f3374221 BD	362	/* I2C devices fitted. */
	363
	364	static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	365	{
	366	I2C_BOARD_INFO("tps65011", 0x48),
	367	.irq = IRQ_EINT20,
4fa084af	368	.platform_data = &osiris_tps_board,
f3374221 BD	369	},
	370	};
	371
110d322b BD	372	/* Standard Osiris devices */
	373
	374	static struct platform_device *osiris_devices[] __initdata = {
3e1b776c	375	&s3c_device_i2c0,
55ba86bc	376	&s3c_device_wdt,
110d322b BD	377	&s3c_device_nand,
	378	&osiris_pcmcia,
	379	};
	380
2bc7509f	381	static struct clk *osiris_clocks[] __initdata = {
110d322b BD	382	&s3c24xx_dclk0,
	383	&s3c24xx_dclk1,
	384	&s3c24xx_clkout0,
	385	&s3c24xx_clkout1,
	386	&s3c24xx_uclk,
	387	};
	388
baf6b281 BD	389	static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	390	.refresh = 7800, /* refresh period is 7.8usec */
	391	.auto_io = 1,
	392	.need_io = 1,
	393	};
	394
da956fd6	395	static void __init osiris_map_io(void)
110d322b	396	{
da956fd6 BD	397	unsigned long flags;
da956fd6 BD	398
110d322b BD	399	/* initialise the clocks */
110d322b BD	400
d96a9804	401	s3c24xx_dclk0.parent = &clk_upll;
110d322b BD	402	s3c24xx_dclk0.rate = 1210001000;
110d322b BD	403
d96a9804	404	s3c24xx_dclk1.parent = &clk_upll;
110d322b BD	405	s3c24xx_dclk1.rate = 2410001000;
	406
	407	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	408	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	409
	410	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	411
ce89c206 BD	412	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
ce89c206 BD	413
110d322b BD	414	s3c_device_nand.dev.platform_data = &osiris_nand_info;
	415
	416	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	417	s3c24xx_init_clocks(0);
	418	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
110d322b	419
3c3e69cd BD	420	/* check for the newer revision boards with large page nand */
	421
	422	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
	423	printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
	424	__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
	425	osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
	426	osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	427	} else {
	428	/* write-protect line to the NAND */
070276d5	429	s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
3c3e69cd BD	430	}
3c3e69cd BD	431
110d322b	432	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
da956fd6 BD	433
da956fd6 BD	434	local_irq_save(flags);
110d322b	435	__raw_writel(__raw_readl(S3C2410_BWSCON) \| S3C2410_BWSCON_ST1 \| S3C2410_BWSCON_ST2 \| S3C2410_BWSCON_ST3 \| S3C2410_BWSCON_ST4 \| S3C2410_BWSCON_ST5, S3C2410_BWSCON);
da956fd6	436	local_irq_restore(flags);
110d322b BD	437	}
110d322b BD	438
57e5171c BD	439	static void __init osiris_init(void)
57e5171c BD	440	{
5698bd28 BD	441	sysdev_class_register(&osiris_pm_sysclass);
	442	sysdev_register(&osiris_pm_sysdev);
	443
3e1b776c BD	444	s3c_i2c0_set_platdata(NULL);
3e1b776c BD	445
baf6b281 BD	446	s3c_cpufreq_setboard(&osiris_cpufreq);
baf6b281 BD	447
f3374221 BD	448	i2c_register_board_info(0, osiris_i2c_devs,
	449	ARRAY_SIZE(osiris_i2c_devs));
	450
57e5171c BD	451	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
	452	};
	453
110d322b BD	454	MACHINE_START(OSIRIS, "Simtec-OSIRIS")
110d322b BD	455	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
110d322b BD	456	.phys_io = S3C2410_PA_UART,
	457	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	458	.boot_params = S3C2410_SDRAM_PA + 0x100,
	459	.map_io = osiris_map_io,
	460	.init_irq = s3c24xx_init_irq,
5698bd28	461	.init_machine = osiris_init,
110d322b BD	462	.timer = &s3c24xx_timer,
110d322b BD	463	MACHINE_END