[deliverable/linux.git] / arch / arm / mach-s3c2440 / mach-osiris.c

/* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
 * Copyright (c) 2005,2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/osiris-map.h>
#include <mach/osiris-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

/* onboard perihperal map */

static struct map_desc osiris_iodesc[] __initdata = {
  /* ISA IO areas (may be over-written later) */

  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },

  /* CPLD control registers */

  {
	  .virtual	= (u32)OSIRIS_VA_CTRL0,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL1,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL2,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_IDREG,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};

static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	}
};

/* NAND Flash on Osiris board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition osiris_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition osiris_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Osiris has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set osiris_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
};

static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(OSIRIS_VA_CTRL0);
	tmp &= ~OSIRIS_CTRL0_NANDSEL;
	tmp |= slot;

	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}

static struct s3c2410_platform_nand osiris_nand_info = {
	.tacls		= 25,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(osiris_nand_sets),
	.sets		= osiris_nand_sets,
	.select_chip	= osiris_nand_select,
};

/* PCMCIA control and configuration */

static struct resource osiris_pcmcia_resource[] = {
	[0] = {
		.start	= 0x0f000000,
		.end	= 0x0f100000,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 0x0c000000,
		.end	= 0x0c100000,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device osiris_pcmcia = {
	.name		= "osiris-pcmcia",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(osiris_pcmcia_resource),
	.resource	= osiris_pcmcia_resource,
};

/* Osiris power management device */

#ifdef CONFIG_PM
static unsigned char pm_osiris_ctrl0;

static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	unsigned int tmp;

	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;

	/* ensure correct NAND slot is selected on resume */
	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	        tmp |= 2;

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);

	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);

	return 0;
}

static int osiris_pm_resume(struct sys_device *sd)
{
	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
		__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);

	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);

	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);

	return 0;
}

#else
#define osiris_pm_suspend NULL
#define osiris_pm_resume NULL
#endif

static struct sysdev_class osiris_pm_sysclass = {
	.name		= "mach-osiris",
	.suspend	= osiris_pm_suspend,
	.resume		= osiris_pm_resume,
};

static struct sys_device osiris_pm_sysdev = {
	.cls		= &osiris_pm_sysclass,
};

/* I2C devices fitted. */

static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
	},
};

/* Standard Osiris devices */

static struct platform_device *osiris_devices[] __initdata = {
	&s3c_device_i2c0,
	&s3c_device_wdt,
	&s3c_device_nand,
	&osiris_pcmcia,
};

static struct clk *osiris_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	.refresh	= 7800, /* refresh period is 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static void __init osiris_map_io(void)
{
	unsigned long flags;

	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));

	s3c_device_nand.dev.platform_data = &osiris_nand_info;

	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
		printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
		       __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
		osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
		osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	} else {
		/* write-protect line to the NAND */
		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
	}

	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */

	local_irq_save(flags);
	__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
	local_irq_restore(flags);
}

static void __init osiris_init(void)
{
	sysdev_class_register(&osiris_pm_sysclass);
	sysdev_register(&osiris_pm_sysdev);

	s3c_i2c0_set_platdata(NULL);

	s3c_cpufreq_setboard(&osiris_cpufreq);

	i2c_register_board_info(0, osiris_i2c_devs,
				ARRAY_SIZE(osiris_i2c_devs));

	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
};

MACHINE_START(OSIRIS, "Simtec-OSIRIS")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= osiris_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= osiris_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-osiris.c
110d322b	2	*
f3374221	3	* Copyright (c) 2005,2008 Simtec Electronics
110d322b BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
110d322b	19	#include <linux/device.h>
5698bd28	20	#include <linux/sysdev.h>
b6d1f542	21	#include <linux/serial_core.h>
d96a9804	22	#include <linux/clk.h>
f3374221	23	#include <linux/i2c.h>
fced80c7	24	#include <linux/io.h>
110d322b BD	25
	26	#include <asm/mach/arch.h>
	27	#include <asm/mach/map.h>
	28	#include <asm/mach/irq.h>
	29
a09e64fb RK	30	#include <mach/osiris-map.h>
a09e64fb RK	31	#include <mach/osiris-cpld.h>
110d322b	32
a09e64fb	33	#include <mach/hardware.h>
110d322b BD	34	#include <asm/irq.h>
	35	#include <asm/mach-types.h>
	36
baf6b281	37	#include <plat/cpu-freq.h>
a2b7ba9c	38	#include <plat/regs-serial.h>
a09e64fb RK	39	#include <mach/regs-gpio.h>
	40	#include <mach/regs-mem.h>
	41	#include <mach/regs-lcd.h>
7926b5a3	42	#include <plat/nand.h>
3e1b776c	43	#include <plat/iic.h>
110d322b BD	44
	45	#include <linux/mtd/mtd.h>
	46	#include <linux/mtd/nand.h>
	47	#include <linux/mtd/nand_ecc.h>
	48	#include <linux/mtd/partitions.h>
	49
d5120ae7	50	#include <plat/clock.h>
a2b7ba9c BD	51	#include <plat/devs.h>
a2b7ba9c BD	52	#include <plat/cpu.h>
110d322b	53
6cbdc8c5	54	/* onboard perihperal map */
110d322b BD	55
	56	static struct map_desc osiris_iodesc[] __initdata = {
	57	/* ISA IO areas (may be over-written later) */
	58
	59	{
	60	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	61	.pfn = __phys_to_pfn(S3C2410_CS5),
	62	.length = SZ_16M,
	63	.type = MT_DEVICE,
	64	}, {
	65	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	66	.pfn = __phys_to_pfn(S3C2410_CS5),
	67	.length = SZ_16M,
	68	.type = MT_DEVICE,
	69	},
	70
	71	/* CPLD control registers */
	72
	73	{
c362aecd BD	74	.virtual = (u32)OSIRIS_VA_CTRL0,
	75	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
	76	.length = SZ_16K,
	77	.type = MT_DEVICE,
	78	}, {
110d322b BD	79	.virtual = (u32)OSIRIS_VA_CTRL1,
	80	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
	81	.length = SZ_16K,
705630db	82	.type = MT_DEVICE,
110d322b BD	83	}, {
	84	.virtual = (u32)OSIRIS_VA_CTRL2,
	85	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
	86	.length = SZ_16K,
705630db	87	.type = MT_DEVICE,
c362aecd BD	88	}, {
	89	.virtual = (u32)OSIRIS_VA_IDREG,
	90	.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
	91	.length = SZ_16K,
	92	.type = MT_DEVICE,
110d322b BD	93	},
	94	};
	95
	96	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	97	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	98	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	99
	100	static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	101	[0] = {
	102	.name = "uclk",
	103	.divisor = 1,
	104	.min_baud = 0,
	105	.max_baud = 0,
	106	},
	107	[1] = {
	108	.name = "pclk",
	109	.divisor = 1,
	110	.min_baud = 0,
705630db	111	.max_baud = 0,
110d322b BD	112	}
	113	};
	114
66a9b49a	115	static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
110d322b BD	116	[0] = {
	117	.hwport = 0,
	118	.flags = 0,
	119	.ucon = UCON,
	120	.ulcon = ULCON,
	121	.ufcon = UFCON,
	122	.clocks = osiris_serial_clocks,
705630db	123	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b BD	124	},
110d322b BD	125	[1] = {
e2e5810f	126	.hwport = 1,
110d322b BD	127	.flags = 0,
	128	.ucon = UCON,
	129	.ulcon = ULCON,
	130	.ufcon = UFCON,
	131	.clocks = osiris_serial_clocks,
705630db	132	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b	133	},
ca7aa4de BD	134	[2] = {
	135	.hwport = 2,
	136	.flags = 0,
	137	.ucon = UCON,
	138	.ulcon = ULCON,
	139	.ufcon = UFCON,
	140	.clocks = osiris_serial_clocks,
	141	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	142	}
110d322b BD	143	};
	144
	145	/* NAND Flash on Osiris board */
	146
	147	static int external_map[] = { 2 };
	148	static int chip0_map[] = { 0 };
	149	static int chip1_map[] = { 1 };
	150
da956fd6	151	static struct mtd_partition osiris_default_nand_part[] = {
110d322b BD	152	[0] = {
	153	.name = "Boot Agent",
	154	.size = SZ_16K,
705630db	155	.offset = 0,
110d322b BD	156	},
	157	[1] = {
	158	.name = "/boot",
	159	.size = SZ_4M - SZ_16K,
	160	.offset = SZ_16K,
	161	},
	162	[2] = {
	163	.name = "user1",
	164	.offset = SZ_4M,
	165	.size = SZ_32M - SZ_4M,
	166	},
	167	[3] = {
	168	.name = "user2",
	169	.offset = SZ_32M,
	170	.size = MTDPART_SIZ_FULL,
	171	}
	172	};
	173
3c3e69cd BD	174	static struct mtd_partition osiris_default_nand_part_large[] = {
	175	[0] = {
	176	.name = "Boot Agent",
	177	.size = SZ_128K,
	178	.offset = 0,
	179	},
	180	[1] = {
	181	.name = "/boot",
	182	.size = SZ_4M - SZ_128K,
	183	.offset = SZ_128K,
	184	},
	185	[2] = {
	186	.name = "user1",
	187	.offset = SZ_4M,
	188	.size = SZ_32M - SZ_4M,
	189	},
	190	[3] = {
	191	.name = "user2",
	192	.offset = SZ_32M,
	193	.size = MTDPART_SIZ_FULL,
	194	}
	195	};
	196
110d322b BD	197	/* the Osiris has 3 selectable slots for nand-flash, the two
	198	* on-board chip areas, as well as the external slot.
	199	*
	200	* Note, there is no current hot-plug support for the External
	201	* socket.
	202	*/
	203
	204	static struct s3c2410_nand_set osiris_nand_sets[] = {
	205	[1] = {
	206	.name = "External",
	207	.nr_chips = 1,
	208	.nr_map = external_map,
	209	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	210	.partitions = osiris_default_nand_part,
110d322b BD	211	},
	212	[0] = {
	213	.name = "chip0",
	214	.nr_chips = 1,
	215	.nr_map = chip0_map,
	216	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	217	.partitions = osiris_default_nand_part,
110d322b BD	218	},
	219	[2] = {
	220	.name = "chip1",
	221	.nr_chips = 1,
	222	.nr_map = chip1_map,
	223	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	224	.partitions = osiris_default_nand_part,
110d322b BD	225	},
	226	};
	227
	228	static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
	229	{
	230	unsigned int tmp;
	231
	232	slot = set->nr_map[slot] & 3;
	233
	234	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
	235	slot, set, set->nr_map);
	236
c362aecd BD	237	tmp = __raw_readb(OSIRIS_VA_CTRL0);
c362aecd BD	238	tmp &= ~OSIRIS_CTRL0_NANDSEL;
110d322b BD	239	tmp \|= slot;
110d322b BD	240
c362aecd	241	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
110d322b	242
c362aecd	243	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
110d322b BD	244	}
	245
	246	static struct s3c2410_platform_nand osiris_nand_info = {
	247	.tacls = 25,
	248	.twrph0 = 60,
	249	.twrph1 = 60,
	250	.nr_sets = ARRAY_SIZE(osiris_nand_sets),
	251	.sets = osiris_nand_sets,
	252	.select_chip = osiris_nand_select,
	253	};
	254
	255	/* PCMCIA control and configuration */
	256
	257	static struct resource osiris_pcmcia_resource[] = {
	258	[0] = {
	259	.start = 0x0f000000,
	260	.end = 0x0f100000,
	261	.flags = IORESOURCE_MEM,
	262	},
	263	[1] = {
	264	.start = 0x0c000000,
	265	.end = 0x0c100000,
	266	.flags = IORESOURCE_MEM,
	267	}
	268	};
	269
	270	static struct platform_device osiris_pcmcia = {
	271	.name = "osiris-pcmcia",
	272	.id = -1,
	273	.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
	274	.resource = osiris_pcmcia_resource,
	275	};
	276
5698bd28 BD	277	/* Osiris power management device */
	278
	279	#ifdef CONFIG_PM
	280	static unsigned char pm_osiris_ctrl0;
	281
	282	static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
	283	{
28047ece BD	284	unsigned int tmp;
28047ece BD	285
5698bd28	286	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
28047ece BD	287	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
	288
	289	/* ensure correct NAND slot is selected on resume */
	290	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	291	tmp \|= 2;
	292
	293	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
	294
4afcddae	295	/* ensure that an nRESET is not generated on resume. */
070276d5 BD	296	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
070276d5 BD	297	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
4afcddae	298
5698bd28 BD	299	return 0;
	300	}
	301
	302	static int osiris_pm_resume(struct sys_device *sd)
	303	{
	304	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
	305	__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
	306
28047ece BD	307	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
28047ece BD	308
070276d5	309	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
4afcddae	310
5698bd28 BD	311	return 0;
	312	}
	313
	314	#else
	315	#define osiris_pm_suspend NULL
	316	#define osiris_pm_resume NULL
	317	#endif
	318
	319	static struct sysdev_class osiris_pm_sysclass = {
af5ca3f4	320	.name = "mach-osiris",
5698bd28 BD	321	.suspend = osiris_pm_suspend,
	322	.resume = osiris_pm_resume,
	323	};
	324
	325	static struct sys_device osiris_pm_sysdev = {
	326	.cls = &osiris_pm_sysclass,
	327	};
	328
f3374221 BD	329	/* I2C devices fitted. */
	330
	331	static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	332	{
	333	I2C_BOARD_INFO("tps65011", 0x48),
	334	.irq = IRQ_EINT20,
	335	},
	336	};
	337
110d322b BD	338	/* Standard Osiris devices */
	339
	340	static struct platform_device *osiris_devices[] __initdata = {
3e1b776c	341	&s3c_device_i2c0,
55ba86bc	342	&s3c_device_wdt,
110d322b BD	343	&s3c_device_nand,
	344	&osiris_pcmcia,
	345	};
	346
2bc7509f	347	static struct clk *osiris_clocks[] __initdata = {
110d322b BD	348	&s3c24xx_dclk0,
	349	&s3c24xx_dclk1,
	350	&s3c24xx_clkout0,
	351	&s3c24xx_clkout1,
	352	&s3c24xx_uclk,
	353	};
	354
baf6b281 BD	355	static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	356	.refresh = 7800, /* refresh period is 7.8usec */
	357	.auto_io = 1,
	358	.need_io = 1,
	359	};
	360
da956fd6	361	static void __init osiris_map_io(void)
110d322b	362	{
da956fd6 BD	363	unsigned long flags;
da956fd6 BD	364
110d322b BD	365	/* initialise the clocks */
110d322b BD	366
d96a9804	367	s3c24xx_dclk0.parent = &clk_upll;
110d322b BD	368	s3c24xx_dclk0.rate = 1210001000;
110d322b BD	369
d96a9804	370	s3c24xx_dclk1.parent = &clk_upll;
110d322b BD	371	s3c24xx_dclk1.rate = 2410001000;
	372
	373	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	374	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	375
	376	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	377
ce89c206 BD	378	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
ce89c206 BD	379
110d322b BD	380	s3c_device_nand.dev.platform_data = &osiris_nand_info;
	381
	382	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	383	s3c24xx_init_clocks(0);
	384	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
110d322b	385
3c3e69cd BD	386	/* check for the newer revision boards with large page nand */
	387
	388	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
	389	printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
	390	__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
	391	osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
	392	osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	393	} else {
	394	/* write-protect line to the NAND */
070276d5	395	s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
3c3e69cd BD	396	}
3c3e69cd BD	397
110d322b	398	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
da956fd6 BD	399
da956fd6 BD	400	local_irq_save(flags);
110d322b	401	__raw_writel(__raw_readl(S3C2410_BWSCON) \| S3C2410_BWSCON_ST1 \| S3C2410_BWSCON_ST2 \| S3C2410_BWSCON_ST3 \| S3C2410_BWSCON_ST4 \| S3C2410_BWSCON_ST5, S3C2410_BWSCON);
da956fd6	402	local_irq_restore(flags);
110d322b BD	403	}
110d322b BD	404
57e5171c BD	405	static void __init osiris_init(void)
57e5171c BD	406	{
5698bd28 BD	407	sysdev_class_register(&osiris_pm_sysclass);
	408	sysdev_register(&osiris_pm_sysdev);
	409
3e1b776c BD	410	s3c_i2c0_set_platdata(NULL);
3e1b776c BD	411
baf6b281 BD	412	s3c_cpufreq_setboard(&osiris_cpufreq);
baf6b281 BD	413
f3374221 BD	414	i2c_register_board_info(0, osiris_i2c_devs,
	415	ARRAY_SIZE(osiris_i2c_devs));
	416
57e5171c BD	417	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
	418	};
	419
110d322b BD	420	MACHINE_START(OSIRIS, "Simtec-OSIRIS")
110d322b BD	421	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
110d322b BD	422	.phys_io = S3C2410_PA_UART,
	423	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	424	.boot_params = S3C2410_SDRAM_PA + 0x100,
	425	.map_io = osiris_map_io,
	426	.init_irq = s3c24xx_init_irq,
5698bd28	427	.init_machine = osiris_init,
110d322b BD	428	.timer = &s3c24xx_timer,
110d322b BD	429	MACHINE_END