[deliverable/linux.git] / arch / arm / mach-s3c2440 / s3c244x.c

/* linux/arch/arm/plat-s3c24xx/s3c244x.c
 *
 * Copyright (c) 2004-2006 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/syscore_ops.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#include <plat/cpu-freq.h>

#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-gpioj.h>
#include <mach/regs-dsc.h>

#include <plat/s3c2410.h>
#include <plat/s3c244x.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/nand-core.h>

static struct map_desc s3c244x_iodesc[] __initdata = {
	IODESC_ENT(CLKPWR),
	IODESC_ENT(TIMER),
	IODESC_ENT(WATCHDOG),
};

/* uart initialisation */

void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
}

void __init s3c244x_map_io(void)
{
	/* register our io-tables */

	iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));

	/* rename any peripherals used differing from the s3c2410 */

	s3c_device_sdi.name  = "s3c2440-sdi";
	s3c_device_i2c0.name  = "s3c2440-i2c";
	s3c_nand_setname("s3c2440-nand");
	s3c_device_ts.name = "s3c2440-ts";
	s3c_device_usbgadget.name = "s3c2440-usbgadget";
}

void __init_or_cpufreq s3c244x_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long clkdiv;
	unsigned long camdiv;
	unsigned long xtal;
	unsigned long hclk, fclk, pclk;
	int hdiv = 1;

	xtal_clk = clk_get(NULL, "xtal");
	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;

	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	camdiv = __raw_readl(S3C2440_CAMDIVN);

	/* work out clock scalings */

	switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
	case S3C2440_CLKDIVN_HDIVN_1:
		hdiv = 1;
		break;

	case S3C2440_CLKDIVN_HDIVN_2:
		hdiv = 2;
		break;

	case S3C2440_CLKDIVN_HDIVN_4_8:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
		break;

	case S3C2440_CLKDIVN_HDIVN_3_6:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
		break;
	}

	hclk = fclk / hdiv;
	pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);

	/* print brief summary of clocks, etc */

	printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	       print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

	s3c24xx_setup_clocks(fclk, hclk, pclk);
}

void __init s3c244x_init_clocks(int xtal)
{
	/* initialise the clocks here, to allow other things like the
	 * console to use them, and to add new ones after the initialisation
	 */

	s3c24xx_register_baseclocks(xtal);
	s3c244x_setup_clocks();
	s3c2410_baseclk_add();
}

/* Since the S3C2442 and S3C2440 share  items, put both sysclasses here */

struct sysdev_class s3c2440_sysclass = {
	.name		= "s3c2440-core",
};

struct sysdev_class s3c2442_sysclass = {
	.name		= "s3c2442-core",
};

/* need to register class before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2440 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
*/

static int __init s3c2440_core_init(void)
{
	return sysdev_class_register(&s3c2440_sysclass);
}

core_initcall(s3c2440_core_init);

static int __init s3c2442_core_init(void)
{
	return sysdev_class_register(&s3c2442_sysclass);
}

core_initcall(s3c2442_core_init);


#ifdef CONFIG_PM
static struct sleep_save s3c244x_sleep[] = {
	SAVE_ITEM(S3C2440_DSC0),
	SAVE_ITEM(S3C2440_DSC1),
	SAVE_ITEM(S3C2440_GPJDAT),
	SAVE_ITEM(S3C2440_GPJCON),
	SAVE_ITEM(S3C2440_GPJUP)
};

static int s3c244x_suspend(void)
{
	s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
	return 0;
}

static void s3c244x_resume(void)
{
	s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
}
#else
#define s3c244x_suspend NULL
#define s3c244x_resume  NULL
#endif

struct syscore_ops s3c244x_pm_syscore_ops = {
	.suspend	= s3c244x_suspend,
	.resume		= s3c244x_resume,
};
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/plat-s3c24xx/s3c244x.c
96ce2385 BD	2	*
	3	* Copyright (c) 2004-2006 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
e4d06e39	6	* Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
96ce2385 BD	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
b6d1f542	19	#include <linux/serial_core.h>
96ce2385 BD	20	#include <linux/platform_device.h>
96ce2385 BD	21	#include <linux/sysdev.h>
bb072c3c	22	#include <linux/syscore_ops.h>
96ce2385	23	#include <linux/clk.h>
fced80c7	24	#include <linux/io.h>
96ce2385 BD	25
	26	#include <asm/mach/arch.h>
	27	#include <asm/mach/map.h>
	28	#include <asm/mach/irq.h>
	29
a09e64fb	30	#include <mach/hardware.h>
96ce2385 BD	31	#include <asm/irq.h>
96ce2385 BD	32
e425382e BD	33	#include <plat/cpu-freq.h>
e425382e BD	34
a09e64fb	35	#include <mach/regs-clock.h>
a2b7ba9c	36	#include <plat/regs-serial.h>
a09e64fb RK	37	#include <mach/regs-gpio.h>
	38	#include <mach/regs-gpioj.h>
	39	#include <mach/regs-dsc.h>
96ce2385	40
a2b7ba9c	41	#include <plat/s3c2410.h>
58bac7b8	42	#include <plat/s3c244x.h>
d5120ae7	43	#include <plat/clock.h>
a2b7ba9c BD	44	#include <plat/devs.h>
	45	#include <plat/cpu.h>
	46	#include <plat/pm.h>
e24b864a	47	#include <plat/pll.h>
ef3f2dd4	48	#include <plat/nand-core.h>
96ce2385 BD	49
	50	static struct map_desc s3c244x_iodesc[] __initdata = {
	51	IODESC_ENT(CLKPWR),
	52	IODESC_ENT(TIMER),
	53	IODESC_ENT(WATCHDOG),
96ce2385 BD	54	};
	55
	56	/* uart initialisation */
	57
	58	void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
	59	{
	60	s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
	61	}
	62
74b265d4	63	void __init s3c244x_map_io(void)
96ce2385 BD	64	{
	65	/* register our io-tables */
	66
	67	iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
96ce2385 BD	68
	69	/* rename any peripherals used differing from the s3c2410 */
	70
90239bbd	71	s3c_device_sdi.name = "s3c2440-sdi";
3e1b776c	72	s3c_device_i2c0.name = "s3c2440-i2c";
ef3f2dd4	73	s3c_nand_setname("s3c2440-nand");
ce8877b5	74	s3c_device_ts.name = "s3c2440-ts";
b8ccca4a	75	s3c_device_usbgadget.name = "s3c2440-usbgadget";
96ce2385 BD	76	}
96ce2385 BD	77
e425382e	78	void __init_or_cpufreq s3c244x_setup_clocks(void)
96ce2385	79	{
e425382e	80	struct clk *xtal_clk;
96ce2385 BD	81	unsigned long clkdiv;
96ce2385 BD	82	unsigned long camdiv;
e425382e	83	unsigned long xtal;
96ce2385 BD	84	unsigned long hclk, fclk, pclk;
	85	int hdiv = 1;
	86
e425382e BD	87	xtal_clk = clk_get(NULL, "xtal");
	88	xtal = clk_get_rate(xtal_clk);
	89	clk_put(xtal_clk);
96ce2385	90
e24b864a	91	fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
96ce2385 BD	92
	93	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	94	camdiv = __raw_readl(S3C2440_CAMDIVN);
	95
	96	/* work out clock scalings */
	97
	98	switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
	99	case S3C2440_CLKDIVN_HDIVN_1:
	100	hdiv = 1;
	101	break;
	102
	103	case S3C2440_CLKDIVN_HDIVN_2:
	104	hdiv = 2;
	105	break;
	106
	107	case S3C2440_CLKDIVN_HDIVN_4_8:
	108	hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
	109	break;
	110
	111	case S3C2440_CLKDIVN_HDIVN_3_6:
	112	hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
	113	break;
	114	}
	115
	116	hclk = fclk / hdiv;
e425382e	117	pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
96ce2385 BD	118
	119	/* print brief summary of clocks, etc */
	120
	121	printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	122	print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
	123
e425382e BD	124	s3c24xx_setup_clocks(fclk, hclk, pclk);
	125	}
	126
	127	void __init s3c244x_init_clocks(int xtal)
	128	{
96ce2385 BD	129	/* initialise the clocks here, to allow other things like the
	130	* console to use them, and to add new ones after the initialisation
	131	*/
	132
e425382e BD	133	s3c24xx_register_baseclocks(xtal);
e425382e BD	134	s3c244x_setup_clocks();
99c13853	135	s3c2410_baseclk_add();
96ce2385 BD	136	}
96ce2385 BD	137
96ce2385 BD	138	/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
	139
	140	struct sysdev_class s3c2440_sysclass = {
af5ca3f4	141	.name = "s3c2440-core",
96ce2385 BD	142	};
	143
	144	struct sysdev_class s3c2442_sysclass = {
af5ca3f4	145	.name = "s3c2442-core",
96ce2385 BD	146	};
	147
	148	/* need to register class before we actually register the device, and
	149	* we also need to ensure that it has been initialised before any of the
	150	* drivers even try to use it (even if not on an s3c2440 based system)
	151	* as a driver which may support both 2410 and 2440 may try and use it.
	152	*/
	153
	154	static int __init s3c2440_core_init(void)
	155	{
	156	return sysdev_class_register(&s3c2440_sysclass);
	157	}
	158
	159	core_initcall(s3c2440_core_init);
	160
	161	static int __init s3c2442_core_init(void)
	162	{
	163	return sysdev_class_register(&s3c2442_sysclass);
	164	}
	165
	166	core_initcall(s3c2442_core_init);
bb072c3c RW	167
	168
	169	#ifdef CONFIG_PM
	170	static struct sleep_save s3c244x_sleep[] = {
	171	SAVE_ITEM(S3C2440_DSC0),
	172	SAVE_ITEM(S3C2440_DSC1),
	173	SAVE_ITEM(S3C2440_GPJDAT),
	174	SAVE_ITEM(S3C2440_GPJCON),
	175	SAVE_ITEM(S3C2440_GPJUP)
	176	};
	177
	178	static int s3c244x_suspend(void)
	179	{
	180	s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
	181	return 0;
	182	}
	183
	184	static void s3c244x_resume(void)
	185	{
	186	s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
	187	}
	188	#else
	189	#define s3c244x_suspend NULL
	190	#define s3c244x_resume NULL
	191	#endif
	192
	193	struct syscore_ops s3c244x_pm_syscore_ops = {
	194	.suspend = s3c244x_suspend,
	195	.resume = s3c244x_resume,
	196	};