[deliverable/linux.git] / arch / arm / mach-s3c24xx / clock-s3c2412.c

/* linux/arch/arm/mach-s3c2412/clock.c
 *
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2412,S3C2413 Clock control support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/io.h>

#include <asm/mach/map.h>

#include <mach/hardware.h>

#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>

#include <plat/clock.h>
#include <plat/cpu.h>

/* We currently have to assume that the system is running
 * from the XTPll input, and that all ***REFCLKs are being
 * fed from it, as we cannot read the state of OM[4] from
 * software.
 *
 * It would be possible for each board initialisation to
 * set the correct muxing at initialisation
*/

static int s3c2412_clkcon_enable(struct clk *clk, int enable)
{
	unsigned int clocks = clk->ctrlbit;
	unsigned long clkcon;

	clkcon = __raw_readl(S3C2410_CLKCON);

	if (enable)
		clkcon |= clocks;
	else
		clkcon &= ~clocks;

	__raw_writel(clkcon, S3C2410_CLKCON);

	return 0;
}

static int s3c2412_upll_enable(struct clk *clk, int enable)
{
	unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
	unsigned long orig = upllcon;

	if (!enable)
		upllcon |= S3C2412_PLLCON_OFF;
	else
		upllcon &= ~S3C2412_PLLCON_OFF;

	__raw_writel(upllcon, S3C2410_UPLLCON);

	/* allow ~150uS for the PLL to settle and lock */

	if (enable && (orig & S3C2412_PLLCON_OFF))
		udelay(150);

	return 0;
}

/* clock selections */

static struct clk clk_erefclk = {
	.name		= "erefclk",
};

static struct clk clk_urefclk = {
	.name		= "urefclk",
};

static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);

	if (parent == &clk_urefclk)
		clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
	else if (parent == &clk_upll)
		clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
	else
		return -EINVAL;

	clk->parent = parent;

	__raw_writel(clksrc, S3C2412_CLKSRC);
	return 0;
}

static struct clk clk_usysclk = {
	.name		= "usysclk",
	.parent		= &clk_xtal,
	.ops		= &(struct clk_ops) {
		.set_parent	= s3c2412_setparent_usysclk,
	},
};

static struct clk clk_mrefclk = {
	.name		= "mrefclk",
	.parent		= &clk_xtal,
};

static struct clk clk_mdivclk = {
	.name		= "mdivclk",
	.parent		= &clk_xtal,
};

static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);

	if (parent == &clk_usysclk)
		clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
	else if (parent == &clk_h)
		clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
	else
		return -EINVAL;

	clk->parent = parent;

	__raw_writel(clksrc, S3C2412_CLKSRC);
	return 0;
}

static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
					      unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
		return parent_rate;

	div = parent_rate / rate;
	if (div > 2)
		div = 2;

	return parent_rate / div;
}

static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2410_CLKDIVN);

	return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
}

static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);

	rate = s3c2412_roundrate_usbsrc(clk, rate);

	if ((parent_rate / rate) == 2)
		clkdivn |= S3C2412_CLKDIVN_USB48DIV;
	else
		clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;

	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	return 0;
}

static struct clk clk_usbsrc = {
	.name		= "usbsrc",
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2412_getrate_usbsrc,
		.set_rate	= s3c2412_setrate_usbsrc,
		.round_rate	= s3c2412_roundrate_usbsrc,
		.set_parent	= s3c2412_setparent_usbsrc,
	},
};

static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);

	if (parent == &clk_mdivclk)
		clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
	else if (parent == &clk_mpll)
		clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
	else
		return -EINVAL;

	clk->parent = parent;

	__raw_writel(clksrc, S3C2412_CLKSRC);
	return 0;
}

static struct clk clk_msysclk = {
	.name		= "msysclk",
	.ops		= &(struct clk_ops) {
		.set_parent	= s3c2412_setparent_msysclk,
	},
};

static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
{
	unsigned long flags;
	unsigned long clkdiv;
	unsigned long dvs;

	/* Note, we current equate fclk andf msysclk for S3C2412 */

	if (parent == &clk_msysclk || parent == &clk_f)
		dvs = 0;
	else if (parent == &clk_h)
		dvs = S3C2412_CLKDIVN_DVSEN;
	else
		return -EINVAL;

	clk->parent = parent;

	/* update this under irq lockdown, clkdivn is not protected
	 * by the clock system. */

	local_irq_save(flags);

	clkdiv  = __raw_readl(S3C2410_CLKDIVN);
	clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
	clkdiv |= dvs;
	__raw_writel(clkdiv, S3C2410_CLKDIVN);

	local_irq_restore(flags);

	return 0;
}

static struct clk clk_armclk = {
	.name		= "armclk",
	.parent		= &clk_msysclk,
	.ops		= &(struct clk_ops) {
		.set_parent	= s3c2412_setparent_armclk,
	},
};

/* these next clocks have an divider immediately after them,
 * so we can register them with their divider and leave out the
 * intermediate clock stage
*/
static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
					      unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
		return parent_rate;

	/* note, we remove the +/- 1 calculations as they cancel out */

	div = (rate / parent_rate);

	if (div < 1)
		div = 1;
	else if (div > 16)
		div = 16;

	return parent_rate / div;
}

static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);

	if (parent == &clk_erefclk)
		clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
	else if (parent == &clk_mpll)
		clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
	else
		return -EINVAL;

	clk->parent = parent;

	__raw_writel(clksrc, S3C2412_CLKSRC);
	return 0;
}

static unsigned long s3c2412_getrate_uart(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2410_CLKDIVN);

	div &= S3C2412_CLKDIVN_UARTDIV_MASK;
	div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;

	return parent_rate / (div + 1);
}

static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);

	rate = s3c2412_roundrate_clksrc(clk, rate);

	clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
	clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;

	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	return 0;
}

static struct clk clk_uart = {
	.name		= "uartclk",
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2412_getrate_uart,
		.set_rate	= s3c2412_setrate_uart,
		.set_parent	= s3c2412_setparent_uart,
		.round_rate	= s3c2412_roundrate_clksrc,
	},
};

static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);

	if (parent == &clk_erefclk)
		clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
	else if (parent == &clk_mpll)
		clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
	else
		return -EINVAL;

	clk->parent = parent;

	__raw_writel(clksrc, S3C2412_CLKSRC);
	return 0;
}

static unsigned long s3c2412_getrate_i2s(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2410_CLKDIVN);

	div &= S3C2412_CLKDIVN_I2SDIV_MASK;
	div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;

	return parent_rate / (div + 1);
}

static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);

	rate = s3c2412_roundrate_clksrc(clk, rate);

	clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
	clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;

	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	return 0;
}

static struct clk clk_i2s = {
	.name		= "i2sclk",
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2412_getrate_i2s,
		.set_rate	= s3c2412_setrate_i2s,
		.set_parent	= s3c2412_setparent_i2s,
		.round_rate	= s3c2412_roundrate_clksrc,
	},
};

static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);

	if (parent == &clk_usysclk)
		clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
	else if (parent == &clk_h)
		clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
	else
		return -EINVAL;

	clk->parent = parent;

	__raw_writel(clksrc, S3C2412_CLKSRC);
	return 0;
}
static unsigned long s3c2412_getrate_cam(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2410_CLKDIVN);

	div &= S3C2412_CLKDIVN_CAMDIV_MASK;
	div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;

	return parent_rate / (div + 1);
}

static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);

	rate = s3c2412_roundrate_clksrc(clk, rate);

	clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
	clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;

	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	return 0;
}

static struct clk clk_cam = {
	.name		= "camif-upll",	/* same as 2440 name */
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2412_getrate_cam,
		.set_rate	= s3c2412_setrate_cam,
		.set_parent	= s3c2412_setparent_cam,
		.round_rate	= s3c2412_roundrate_clksrc,
	},
};

/* standard clock definitions */

static struct clk init_clocks_disable[] = {
	{
		.name		= "nand",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_NAND,
	}, {
		.name		= "sdi",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_SDI,
	}, {
		.name		= "adc",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_ADC,
	}, {
		.name		= "i2c",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_IIC,
	}, {
		.name		= "iis",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_IIS,
	}, {
		.name		= "spi",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_SPI,
	}
};

static struct clk init_clocks[] = {
	{
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_DMA0,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_DMA1,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_DMA2,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_DMA3,
	}, {
		.name		= "lcd",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_LCDC,
	}, {
		.name		= "gpio",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_GPIO,
	}, {
		.name		= "usb-host",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_USBH,
	}, {
		.name		= "usb-device",
		.parent		= &clk_h,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_USBD,
	}, {
		.name		= "timers",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_PWMT,
	}, {
		.name		= "uart",
		.devname	= "s3c2412-uart.0",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_UART0,
	}, {
		.name		= "uart",
		.devname	= "s3c2412-uart.1",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_UART1,
	}, {
		.name		= "uart",
		.devname	= "s3c2412-uart.2",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_UART2,
	}, {
		.name		= "rtc",
		.parent		= &clk_p,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_RTC,
	}, {
		.name		= "watchdog",
		.parent		= &clk_p,
		.ctrlbit	= 0,
	}, {
		.name		= "usb-bus-gadget",
		.parent		= &clk_usb_bus,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_USB_DEV48,
	}, {
		.name		= "usb-bus-host",
		.parent		= &clk_usb_bus,
		.enable		= s3c2412_clkcon_enable,
		.ctrlbit	= S3C2412_CLKCON_USB_HOST48,
	}
};

/* clocks to add where we need to check their parentage */

struct clk_init {
	struct clk	*clk;
	unsigned int	 bit;
	struct clk	*src_0;
	struct clk	*src_1;
};

static struct clk_init clks_src[] __initdata = {
	{
		.clk	= &clk_usysclk,
		.bit	= S3C2412_CLKSRC_USBCLK_HCLK,
		.src_0	= &clk_urefclk,
		.src_1	= &clk_upll,
	}, {
		.clk	= &clk_i2s,
		.bit	= S3C2412_CLKSRC_I2SCLK_MPLL,
		.src_0	= &clk_erefclk,
		.src_1	= &clk_mpll,
	}, {
		.clk	= &clk_cam,
		.bit	= S3C2412_CLKSRC_CAMCLK_HCLK,
		.src_0	= &clk_usysclk,
		.src_1	= &clk_h,
	}, {
		.clk	= &clk_msysclk,
		.bit	= S3C2412_CLKSRC_MSYSCLK_MPLL,
		.src_0	= &clk_mdivclk,
		.src_1	= &clk_mpll,
	}, {
		.clk	= &clk_uart,
		.bit	= S3C2412_CLKSRC_UARTCLK_MPLL,
		.src_0	= &clk_erefclk,
		.src_1	= &clk_mpll,
	}, {
		.clk	= &clk_usbsrc,
		.bit	= S3C2412_CLKSRC_USBCLK_HCLK,
		.src_0	= &clk_usysclk,
		.src_1	= &clk_h,
	/* here we assume  OM[4] select xtal */
	}, {
		.clk	= &clk_erefclk,
		.bit	= S3C2412_CLKSRC_EREFCLK_EXTCLK,
		.src_0	= &clk_xtal,
		.src_1	= &clk_ext,
	}, {
		.clk	= &clk_urefclk,
		.bit	= S3C2412_CLKSRC_UREFCLK_EXTCLK,
		.src_0	= &clk_xtal,
		.src_1	= &clk_ext,
	},
};

/* s3c2412_clk_initparents
 *
 * Initialise the parents for the clocks that we get at start-time
*/

static void __init s3c2412_clk_initparents(void)
{
	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	struct clk_init *cip = clks_src;
	struct clk *src;
	int ptr;
	int ret;

	for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
		ret = s3c24xx_register_clock(cip->clk);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       cip->clk->name, ret);
		}

		src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;

		printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
		clk_set_parent(cip->clk, src);
	}
}

/* clocks to add straight away */

static struct clk *clks[] __initdata = {
	&clk_ext,
	&clk_usb_bus,
	&clk_mrefclk,
	&clk_armclk,
};

static struct clk_lookup s3c2412_clk_lookup[] = {
	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
};

int __init s3c2412_baseclk_add(void)
{
	unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
	unsigned int dvs;
	struct clk *clkp;
	int ret;
	int ptr;

	clk_upll.enable = s3c2412_upll_enable;
	clk_usb_bus.parent = &clk_usbsrc;
	clk_usb_bus.rate = 0x0;

	clk_f.parent = &clk_msysclk;

	s3c2412_clk_initparents();

	for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
		clkp = clks[ptr];

		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
	}

	/* set the dvs state according to what we got at boot time */

	dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;

	if (dvs)
		clk_armclk.parent = &clk_h;

	printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");

	/* ensure usb bus clock is within correct rate of 48MHz */

	if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
		printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");

		/* for the moment, let's use the UPLL, and see if we can
		 * get 48MHz */

		clk_set_parent(&clk_usysclk, &clk_upll);
		clk_set_parent(&clk_usbsrc, &clk_usysclk);
		clk_set_rate(&clk_usbsrc, 48*1000*1000);
	}

	printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
	       (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
	       print_mhz(clk_get_rate(&clk_upll)),
	       print_mhz(clk_get_rate(&clk_usb_bus)));

	/* register clocks from clock array */

	clkp = init_clocks;
	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
		/* ensure that we note the clock state */

		clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;

		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
	}

	/* We must be careful disabling the clocks we are not intending to
	 * be using at boot time, as subsystems such as the LCD which do
	 * their own DMA requests to the bus can cause the system to lockup
	 * if they where in the middle of requesting bus access.
	 *
	 * Disabling the LCD clock if the LCD is active is very dangerous,
	 * and therefore the bootloader should be careful to not enable
	 * the LCD clock if it is not needed.
	*/

	/* install (and disable) the clocks we do not need immediately */

	clkp = init_clocks_disable;
	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {

		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}

		s3c2412_clkcon_enable(clkp, 0);
	}

	clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
	s3c_pwmclk_init();
	return 0;
}
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2412/clock.c
736855f0 BD	2	*
	3	* Copyright (c) 2006 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2412,S3C2413 Clock control support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/kernel.h>
	26	#include <linux/list.h>
	27	#include <linux/errno.h>
	28	#include <linux/err.h>
edbaa603	29	#include <linux/device.h>
736855f0 BD	30	#include <linux/clk.h>
	31	#include <linux/mutex.h>
	32	#include <linux/delay.h>
b6d1f542	33	#include <linux/serial_core.h>
fced80c7	34	#include <linux/io.h>
736855f0	35
7ae9e420 BD	36	#include <asm/mach/map.h>
7ae9e420 BD	37
a09e64fb	38	#include <mach/hardware.h>
736855f0	39
a2b7ba9c	40	#include <plat/regs-serial.h>
a09e64fb RK	41	#include <mach/regs-clock.h>
a09e64fb RK	42	#include <mach/regs-gpio.h>
736855f0	43
d5120ae7	44	#include <plat/clock.h>
a2b7ba9c	45	#include <plat/cpu.h>
736855f0 BD	46
	47	/* We currently have to assume that the system is running
	48	* from the XTPll input, and that all ***REFCLKs are being
	49	* fed from it, as we cannot read the state of OM[4] from
	50	* software.
	51	*
	52	* It would be possible for each board initialisation to
	53	* set the correct muxing at initialisation
	54	*/
	55
7ae9e420	56	static int s3c2412_clkcon_enable(struct clk *clk, int enable)
736855f0 BD	57	{
	58	unsigned int clocks = clk->ctrlbit;
	59	unsigned long clkcon;
	60
	61	clkcon = __raw_readl(S3C2410_CLKCON);
	62
	63	if (enable)
	64	clkcon \|= clocks;
	65	else
	66	clkcon &= ~clocks;
	67
	68	__raw_writel(clkcon, S3C2410_CLKCON);
	69
	70	return 0;
	71	}
	72
	73	static int s3c2412_upll_enable(struct clk *clk, int enable)
	74	{
	75	unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
	76	unsigned long orig = upllcon;
	77
	78	if (!enable)
	79	upllcon \|= S3C2412_PLLCON_OFF;
	80	else
	81	upllcon &= ~S3C2412_PLLCON_OFF;
	82
	83	__raw_writel(upllcon, S3C2410_UPLLCON);
	84
	85	/* allow ~150uS for the PLL to settle and lock */
	86
	87	if (enable && (orig & S3C2412_PLLCON_OFF))
	88	udelay(150);
	89
	90	return 0;
	91	}
	92
	93	/* clock selections */
	94
736855f0 BD	95	static struct clk clk_erefclk = {
736855f0 BD	96	.name = "erefclk",
736855f0 BD	97	};
	98
	99	static struct clk clk_urefclk = {
	100	.name = "urefclk",
736855f0 BD	101	};
	102
	103	static int s3c2412_setparent_usysclk(struct clk clk, struct clk parent)
	104	{
	105	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	106
	107	if (parent == &clk_urefclk)
	108	clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
	109	else if (parent == &clk_upll)
	110	clksrc \|= S3C2412_CLKSRC_USYSCLK_UPLL;
	111	else
	112	return -EINVAL;
	113
	114	clk->parent = parent;
	115
	116	__raw_writel(clksrc, S3C2412_CLKSRC);
	117	return 0;
	118	}
	119
	120	static struct clk clk_usysclk = {
	121	.name = "usysclk",
736855f0	122	.parent = &clk_xtal,
b3bf41be BD	123	.ops = &(struct clk_ops) {
	124	.set_parent = s3c2412_setparent_usysclk,
	125	},
736855f0 BD	126	};
	127
	128	static struct clk clk_mrefclk = {
	129	.name = "mrefclk",
	130	.parent = &clk_xtal,
736855f0 BD	131	};
	132
	133	static struct clk clk_mdivclk = {
	134	.name = "mdivclk",
	135	.parent = &clk_xtal,
736855f0 BD	136	};
	137
	138	static int s3c2412_setparent_usbsrc(struct clk clk, struct clk parent)
	139	{
	140	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	141
	142	if (parent == &clk_usysclk)
	143	clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
	144	else if (parent == &clk_h)
	145	clksrc \|= S3C2412_CLKSRC_USBCLK_HCLK;
	146	else
	147	return -EINVAL;
	148
	149	clk->parent = parent;
	150
	151	__raw_writel(clksrc, S3C2412_CLKSRC);
	152	return 0;
	153	}
	154
	155	static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
	156	unsigned long rate)
	157	{
	158	unsigned long parent_rate = clk_get_rate(clk->parent);
	159	int div;
	160
	161	if (rate > parent_rate)
	162	return parent_rate;
	163
	164	div = parent_rate / rate;
	165	if (div > 2)
	166	div = 2;
	167
	168	return parent_rate / div;
	169	}
	170
	171	static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
	172	{
	173	unsigned long parent_rate = clk_get_rate(clk->parent);
	174	unsigned long div = __raw_readl(S3C2410_CLKDIVN);
	175
	176	return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
	177	}
	178
	179	static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
	180	{
	181	unsigned long parent_rate = clk_get_rate(clk->parent);
	182	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
	183
	184	rate = s3c2412_roundrate_usbsrc(clk, rate);
	185
	186	if ((parent_rate / rate) == 2)
	187	clkdivn \|= S3C2412_CLKDIVN_USB48DIV;
	188	else
	189	clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
	190
	191	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	192	return 0;
	193	}
	194
	195	static struct clk clk_usbsrc = {
	196	.name = "usbsrc",
b3bf41be BD	197	.ops = &(struct clk_ops) {
	198	.get_rate = s3c2412_getrate_usbsrc,
	199	.set_rate = s3c2412_setrate_usbsrc,
	200	.round_rate = s3c2412_roundrate_usbsrc,
	201	.set_parent = s3c2412_setparent_usbsrc,
	202	},
736855f0 BD	203	};
	204
	205	static int s3c2412_setparent_msysclk(struct clk clk, struct clk parent)
	206	{
	207	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	208
	209	if (parent == &clk_mdivclk)
	210	clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
cca851d7	211	else if (parent == &clk_mpll)
736855f0 BD	212	clksrc \|= S3C2412_CLKSRC_MSYSCLK_MPLL;
	213	else
	214	return -EINVAL;
	215
	216	clk->parent = parent;
	217
	218	__raw_writel(clksrc, S3C2412_CLKSRC);
	219	return 0;
	220	}
	221
	222	static struct clk clk_msysclk = {
	223	.name = "msysclk",
b3bf41be BD	224	.ops = &(struct clk_ops) {
	225	.set_parent = s3c2412_setparent_msysclk,
	226	},
736855f0 BD	227	};
736855f0 BD	228
bdbea34d BD	229	static int s3c2412_setparent_armclk(struct clk clk, struct clk parent)
	230	{
	231	unsigned long flags;
	232	unsigned long clkdiv;
	233	unsigned long dvs;
	234
	235	/* Note, we current equate fclk andf msysclk for S3C2412 */
	236
	237	if (parent == &clk_msysclk \|\| parent == &clk_f)
	238	dvs = 0;
	239	else if (parent == &clk_h)
	240	dvs = S3C2412_CLKDIVN_DVSEN;
	241	else
	242	return -EINVAL;
	243
	244	clk->parent = parent;
	245
	246	/* update this under irq lockdown, clkdivn is not protected
	247	* by the clock system. */
	248
	249	local_irq_save(flags);
	250
	251	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	252	clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
	253	clkdiv \|= dvs;
	254	__raw_writel(clkdiv, S3C2410_CLKDIVN);
	255
	256	local_irq_restore(flags);
	257
	258	return 0;
	259	}
	260
	261	static struct clk clk_armclk = {
	262	.name = "armclk",
bdbea34d	263	.parent = &clk_msysclk,
b3bf41be BD	264	.ops = &(struct clk_ops) {
	265	.set_parent = s3c2412_setparent_armclk,
	266	},
bdbea34d BD	267	};
bdbea34d BD	268
736855f0 BD	269	/* these next clocks have an divider immediately after them,
	270	* so we can register them with their divider and leave out the
	271	* intermediate clock stage
	272	*/
	273	static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
	274	unsigned long rate)
	275	{
	276	unsigned long parent_rate = clk_get_rate(clk->parent);
	277	int div;
	278
	279	if (rate > parent_rate)
	280	return parent_rate;
	281
	282	/* note, we remove the +/- 1 calculations as they cancel out */
	283
	284	div = (rate / parent_rate);
	285
	286	if (div < 1)
	287	div = 1;
	288	else if (div > 16)
	289	div = 16;
	290
	291	return parent_rate / div;
	292	}
	293
	294	static int s3c2412_setparent_uart(struct clk clk, struct clk parent)
	295	{
	296	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	297
	298	if (parent == &clk_erefclk)
	299	clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
	300	else if (parent == &clk_mpll)
	301	clksrc \|= S3C2412_CLKSRC_UARTCLK_MPLL;
	302	else
	303	return -EINVAL;
	304
	305	clk->parent = parent;
	306
	307	__raw_writel(clksrc, S3C2412_CLKSRC);
	308	return 0;
	309	}
	310
	311	static unsigned long s3c2412_getrate_uart(struct clk *clk)
	312	{
	313	unsigned long parent_rate = clk_get_rate(clk->parent);
	314	unsigned long div = __raw_readl(S3C2410_CLKDIVN);
	315
	316	div &= S3C2412_CLKDIVN_UARTDIV_MASK;
	317	div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
	318
	319	return parent_rate / (div + 1);
	320	}
	321
	322	static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
	323	{
	324	unsigned long parent_rate = clk_get_rate(clk->parent);
	325	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
	326
	327	rate = s3c2412_roundrate_clksrc(clk, rate);
	328
	329	clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
	330	clkdivn \|= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
	331
	332	__raw_writel(clkdivn, S3C2410_CLKDIVN);
333	return 0;
334	}
335
336	static struct clk clk_uart = {
337	.name = "uartclk",
b3bf41be BD	338	.ops = &(struct clk_ops) {
	339	.get_rate = s3c2412_getrate_uart,
	340	.set_rate = s3c2412_setrate_uart,
	341	.set_parent = s3c2412_setparent_uart,
	342	.round_rate = s3c2412_roundrate_clksrc,
	343	},
736855f0 BD	344	};
	345
	346	static int s3c2412_setparent_i2s(struct clk clk, struct clk parent)
	347	{
	348	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	349
	350	if (parent == &clk_erefclk)
	351	clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
	352	else if (parent == &clk_mpll)
	353	clksrc \|= S3C2412_CLKSRC_I2SCLK_MPLL;
	354	else
	355	return -EINVAL;
	356
	357	clk->parent = parent;
	358
	359	__raw_writel(clksrc, S3C2412_CLKSRC);
	360	return 0;
	361	}
	362
	363	static unsigned long s3c2412_getrate_i2s(struct clk *clk)
	364	{
	365	unsigned long parent_rate = clk_get_rate(clk->parent);
	366	unsigned long div = __raw_readl(S3C2410_CLKDIVN);
	367
	368	div &= S3C2412_CLKDIVN_I2SDIV_MASK;
	369	div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
	370
	371	return parent_rate / (div + 1);
	372	}
	373
	374	static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
	375	{
	376	unsigned long parent_rate = clk_get_rate(clk->parent);
	377	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
	378
	379	rate = s3c2412_roundrate_clksrc(clk, rate);
	380
	381	clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
	382	clkdivn \|= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
	383
	384	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	385	return 0;
	386	}
	387
	388	static struct clk clk_i2s = {
	389	.name = "i2sclk",
b3bf41be BD	390	.ops = &(struct clk_ops) {
	391	.get_rate = s3c2412_getrate_i2s,
	392	.set_rate = s3c2412_setrate_i2s,
	393	.set_parent = s3c2412_setparent_i2s,
	394	.round_rate = s3c2412_roundrate_clksrc,
	395	},
736855f0 BD	396	};
	397
	398	static int s3c2412_setparent_cam(struct clk clk, struct clk parent)
	399	{
	400	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	401
	402	if (parent == &clk_usysclk)
	403	clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
	404	else if (parent == &clk_h)
	405	clksrc \|= S3C2412_CLKSRC_CAMCLK_HCLK;
	406	else
	407	return -EINVAL;
	408
	409	clk->parent = parent;
	410
	411	__raw_writel(clksrc, S3C2412_CLKSRC);
	412	return 0;
	413	}
	414	static unsigned long s3c2412_getrate_cam(struct clk *clk)
	415	{
	416	unsigned long parent_rate = clk_get_rate(clk->parent);
	417	unsigned long div = __raw_readl(S3C2410_CLKDIVN);
	418
	419	div &= S3C2412_CLKDIVN_CAMDIV_MASK;
	420	div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
	421
	422	return parent_rate / (div + 1);
	423	}
	424
	425	static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
	426	{
	427	unsigned long parent_rate = clk_get_rate(clk->parent);
	428	unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
	429
	430	rate = s3c2412_roundrate_clksrc(clk, rate);
	431
	432	clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
	433	clkdivn \|= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
	434
	435	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	436	return 0;
	437	}
	438
	439	static struct clk clk_cam = {
	440	.name = "camif-upll", /* same as 2440 name */
b3bf41be BD	441	.ops = &(struct clk_ops) {
	442	.get_rate = s3c2412_getrate_cam,
	443	.set_rate = s3c2412_setrate_cam,
	444	.set_parent = s3c2412_setparent_cam,
	445	.round_rate = s3c2412_roundrate_clksrc,
	446	},
736855f0 BD	447	};
	448
	449	/* standard clock definitions */
	450
	451	static struct clk init_clocks_disable[] = {
	452	{
	453	.name = "nand",
736855f0 BD	454	.parent = &clk_h,
	455	.enable = s3c2412_clkcon_enable,
	456	.ctrlbit = S3C2412_CLKCON_NAND,
	457	}, {
	458	.name = "sdi",
736855f0 BD	459	.parent = &clk_p,
	460	.enable = s3c2412_clkcon_enable,
	461	.ctrlbit = S3C2412_CLKCON_SDI,
	462	}, {
	463	.name = "adc",
736855f0 BD	464	.parent = &clk_p,
	465	.enable = s3c2412_clkcon_enable,
	466	.ctrlbit = S3C2412_CLKCON_ADC,
	467	}, {
	468	.name = "i2c",
736855f0 BD	469	.parent = &clk_p,
	470	.enable = s3c2412_clkcon_enable,
	471	.ctrlbit = S3C2412_CLKCON_IIC,
	472	}, {
	473	.name = "iis",
736855f0 BD	474	.parent = &clk_p,
	475	.enable = s3c2412_clkcon_enable,
	476	.ctrlbit = S3C2412_CLKCON_IIS,
	477	}, {
	478	.name = "spi",
736855f0 BD	479	.parent = &clk_p,
	480	.enable = s3c2412_clkcon_enable,
	481	.ctrlbit = S3C2412_CLKCON_SPI,
	482	}
	483	};
	484
	485	static struct clk init_clocks[] = {
	486	{
	487	.name = "dma",
736855f0 BD	488	.parent = &clk_h,
	489	.enable = s3c2412_clkcon_enable,
	490	.ctrlbit = S3C2412_CLKCON_DMA0,
	491	}, {
	492	.name = "dma",
736855f0 BD	493	.parent = &clk_h,
	494	.enable = s3c2412_clkcon_enable,
	495	.ctrlbit = S3C2412_CLKCON_DMA1,
	496	}, {
	497	.name = "dma",
736855f0 BD	498	.parent = &clk_h,
	499	.enable = s3c2412_clkcon_enable,
	500	.ctrlbit = S3C2412_CLKCON_DMA2,
	501	}, {
	502	.name = "dma",
736855f0 BD	503	.parent = &clk_h,
	504	.enable = s3c2412_clkcon_enable,
	505	.ctrlbit = S3C2412_CLKCON_DMA3,
	506	}, {
	507	.name = "lcd",
736855f0 BD	508	.parent = &clk_h,
	509	.enable = s3c2412_clkcon_enable,
	510	.ctrlbit = S3C2412_CLKCON_LCDC,
	511	}, {
	512	.name = "gpio",
736855f0 BD	513	.parent = &clk_p,
	514	.enable = s3c2412_clkcon_enable,
	515	.ctrlbit = S3C2412_CLKCON_GPIO,
	516	}, {
	517	.name = "usb-host",
736855f0 BD	518	.parent = &clk_h,
	519	.enable = s3c2412_clkcon_enable,
	520	.ctrlbit = S3C2412_CLKCON_USBH,
	521	}, {
	522	.name = "usb-device",
736855f0 BD	523	.parent = &clk_h,
	524	.enable = s3c2412_clkcon_enable,
	525	.ctrlbit = S3C2412_CLKCON_USBD,
	526	}, {
	527	.name = "timers",
736855f0 BD	528	.parent = &clk_p,
	529	.enable = s3c2412_clkcon_enable,
	530	.ctrlbit = S3C2412_CLKCON_PWMT,
	531	}, {
	532	.name = "uart",
e83626f2	533	.devname = "s3c2412-uart.0",
736855f0 BD	534	.parent = &clk_p,
	535	.enable = s3c2412_clkcon_enable,
	536	.ctrlbit = S3C2412_CLKCON_UART0,
	537	}, {
	538	.name = "uart",
e83626f2	539	.devname = "s3c2412-uart.1",
736855f0 BD	540	.parent = &clk_p,
	541	.enable = s3c2412_clkcon_enable,
	542	.ctrlbit = S3C2412_CLKCON_UART1,
	543	}, {
	544	.name = "uart",
e83626f2	545	.devname = "s3c2412-uart.2",
736855f0 BD	546	.parent = &clk_p,
	547	.enable = s3c2412_clkcon_enable,
	548	.ctrlbit = S3C2412_CLKCON_UART2,
	549	}, {
	550	.name = "rtc",
736855f0 BD	551	.parent = &clk_p,
	552	.enable = s3c2412_clkcon_enable,
	553	.ctrlbit = S3C2412_CLKCON_RTC,
	554	}, {
	555	.name = "watchdog",
736855f0 BD	556	.parent = &clk_p,
	557	.ctrlbit = 0,
	558	}, {
	559	.name = "usb-bus-gadget",
736855f0 BD	560	.parent = &clk_usb_bus,
	561	.enable = s3c2412_clkcon_enable,
	562	.ctrlbit = S3C2412_CLKCON_USB_DEV48,
	563	}, {
	564	.name = "usb-bus-host",
736855f0 BD	565	.parent = &clk_usb_bus,
	566	.enable = s3c2412_clkcon_enable,
	567	.ctrlbit = S3C2412_CLKCON_USB_HOST48,
	568	}
	569	};
	570
	571	/* clocks to add where we need to check their parentage */
	572
	573	struct clk_init {
	574	struct clk *clk;
	575	unsigned int bit;
	576	struct clk *src_0;
	577	struct clk *src_1;
	578	};
	579
7ae9e420	580	static struct clk_init clks_src[] __initdata = {
736855f0 BD	581	{
	582	.clk = &clk_usysclk,
	583	.bit = S3C2412_CLKSRC_USBCLK_HCLK,
	584	.src_0 = &clk_urefclk,
	585	.src_1 = &clk_upll,
	586	}, {
	587	.clk = &clk_i2s,
	588	.bit = S3C2412_CLKSRC_I2SCLK_MPLL,
	589	.src_0 = &clk_erefclk,
	590	.src_1 = &clk_mpll,
	591	}, {
	592	.clk = &clk_cam,
	593	.bit = S3C2412_CLKSRC_CAMCLK_HCLK,
	594	.src_0 = &clk_usysclk,
	595	.src_1 = &clk_h,
	596	}, {
	597	.clk = &clk_msysclk,
	598	.bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
	599	.src_0 = &clk_mdivclk,
	600	.src_1 = &clk_mpll,
	601	}, {
	602	.clk = &clk_uart,
	603	.bit = S3C2412_CLKSRC_UARTCLK_MPLL,
	604	.src_0 = &clk_erefclk,
	605	.src_1 = &clk_mpll,
	606	}, {
	607	.clk = &clk_usbsrc,
	608	.bit = S3C2412_CLKSRC_USBCLK_HCLK,
	609	.src_0 = &clk_usysclk,
	610	.src_1 = &clk_h,
d5c52922 MC	611	/* here we assume OM[4] select xtal */
	612	}, {
	613	.clk = &clk_erefclk,
	614	.bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
	615	.src_0 = &clk_xtal,
	616	.src_1 = &clk_ext,
	617	}, {
	618	.clk = &clk_urefclk,
	619	.bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
	620	.src_0 = &clk_xtal,
	621	.src_1 = &clk_ext,
736855f0 BD	622	},
	623	};
	624
	625	/* s3c2412_clk_initparents
	626	*
	627	* Initialise the parents for the clocks that we get at start-time
	628	*/
	629
	630	static void __init s3c2412_clk_initparents(void)
	631	{
	632	unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
	633	struct clk_init *cip = clks_src;
	634	struct clk *src;
	635	int ptr;
	636	int ret;
	637
	638	for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
	639	ret = s3c24xx_register_clock(cip->clk);
	640	if (ret < 0) {
	641	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	642	cip->clk->name, ret);
	643	}
	644
	645	src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
	646
	647	printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
	648	clk_set_parent(cip->clk, src);
	649	}
	650	}
	651
	652	/* clocks to add straight away */
	653
7ae9e420	654	static struct clk *clks[] __initdata = {
736855f0 BD	655	&clk_ext,
736855f0 BD	656	&clk_usb_bus,
736855f0	657	&clk_mrefclk,
bdbea34d	658	&clk_armclk,
736855f0 BD	659	};
736855f0 BD	660
0cfb26e1 TA	661	static struct clk_lookup s3c2412_clk_lookup[] = {
	662	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
	663	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
	664	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
	665	};
	666
736855f0 BD	667	int __init s3c2412_baseclk_add(void)
	668	{
	669	unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
bdbea34d	670	unsigned int dvs;
736855f0 BD	671	struct clk *clkp;
	672	int ret;
	673	int ptr;
	674
	675	clk_upll.enable = s3c2412_upll_enable;
	676	clk_usb_bus.parent = &clk_usbsrc;
	677	clk_usb_bus.rate = 0x0;
	678
ddd870bd BD	679	clk_f.parent = &clk_msysclk;
ddd870bd BD	680
736855f0 BD	681	s3c2412_clk_initparents();
	682
	683	for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
	684	clkp = clks[ptr];
	685
	686	ret = s3c24xx_register_clock(clkp);
	687	if (ret < 0) {
	688	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	689	clkp->name, ret);
	690	}
	691	}
	692
bdbea34d BD	693	/* set the dvs state according to what we got at boot time */
	694
	695	dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
	696
	697	if (dvs)
	698	clk_armclk.parent = &clk_h;
	699
	700	printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
	701
736855f0 BD	702	/* ensure usb bus clock is within correct rate of 48MHz */
	703
	704	if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
	705	printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
	706
	707	/* for the moment, let's use the UPLL, and see if we can
	708	* get 48MHz */
	709
	710	clk_set_parent(&clk_usysclk, &clk_upll);
	711	clk_set_parent(&clk_usbsrc, &clk_usysclk);
	712	clk_set_rate(&clk_usbsrc, 4810001000);
	713	}
	714
	715	printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
	716	(__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
	717	print_mhz(clk_get_rate(&clk_upll)),
	718	print_mhz(clk_get_rate(&clk_usb_bus)));
	719
	720	/* register clocks from clock array */
	721
	722	clkp = init_clocks;
	723	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
	724	/* ensure that we note the clock state */
	725
	726	clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
	727
	728	ret = s3c24xx_register_clock(clkp);
	729	if (ret < 0) {
	730	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	731	clkp->name, ret);
	732	}
	733	}
	734
	735	/* We must be careful disabling the clocks we are not intending to
3a4fa0a2	736	* be using at boot time, as subsystems such as the LCD which do
736855f0 BD	737	* their own DMA requests to the bus can cause the system to lockup
	738	* if they where in the middle of requesting bus access.
	739	*
	740	* Disabling the LCD clock if the LCD is active is very dangerous,
	741	* and therefore the bootloader should be careful to not enable
	742	* the LCD clock if it is not needed.
	743	*/
	744
	745	/* install (and disable) the clocks we do not need immediately */
	746
	747	clkp = init_clocks_disable;
	748	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
	749
	750	ret = s3c24xx_register_clock(clkp);
	751	if (ret < 0) {
	752	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	753	clkp->name, ret);
	754	}
	755
	756	s3c2412_clkcon_enable(clkp, 0);
	757	}
	758
0cfb26e1	759	clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
9d325f23	760	s3c_pwmclk_init();
736855f0 BD	761	return 0;
736855f0 BD	762	}