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a21765a7 | 1 | /* linux/arch/arm/mach-s3c2440/clock.c |
a8d11e3d BD |
2 | * |
3 | * Copyright (c) 2004-2005 Simtec Electronics | |
4 | * http://armlinux.simtec.co.uk/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * S3C2440 Clock support | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/device.h> | |
a8d11e3d BD |
31 | #include <linux/interrupt.h> |
32 | #include <linux/ioport.h> | |
36c64af4 | 33 | #include <linux/mutex.h> |
f8ce2547 | 34 | #include <linux/clk.h> |
fced80c7 | 35 | #include <linux/io.h> |
046c217c | 36 | #include <linux/serial_core.h> |
a8d11e3d | 37 | |
a09e64fb | 38 | #include <mach/hardware.h> |
60063497 | 39 | #include <linux/atomic.h> |
a8d11e3d | 40 | #include <asm/irq.h> |
a8d11e3d | 41 | |
a09e64fb | 42 | #include <mach/regs-clock.h> |
a8d11e3d | 43 | |
d5120ae7 | 44 | #include <plat/clock.h> |
a2b7ba9c | 45 | #include <plat/cpu.h> |
046c217c | 46 | #include <plat/regs-serial.h> |
a8d11e3d BD |
47 | |
48 | /* S3C2440 extended clock support */ | |
49 | ||
e44c0396 BD |
50 | static unsigned long s3c2440_camif_upll_round(struct clk *clk, |
51 | unsigned long rate) | |
52 | { | |
53 | unsigned long parent_rate = clk_get_rate(clk->parent); | |
54 | int div; | |
55 | ||
56 | if (rate > parent_rate) | |
57 | return parent_rate; | |
58 | ||
59 | /* note, we remove the +/- 1 calculations for the divisor */ | |
60 | ||
61 | div = (parent_rate / rate) / 2; | |
62 | ||
63 | if (div < 1) | |
64 | div = 1; | |
65 | else if (div > 16) | |
66 | div = 16; | |
67 | ||
68 | return parent_rate / (div * 2); | |
69 | } | |
70 | ||
71 | static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) | |
72 | { | |
73 | unsigned long parent_rate = clk_get_rate(clk->parent); | |
74 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); | |
75 | ||
76 | rate = s3c2440_camif_upll_round(clk, rate); | |
77 | ||
78 | camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK); | |
79 | ||
80 | if (rate != parent_rate) { | |
81 | camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; | |
82 | camdivn |= (((parent_rate / rate) / 2) - 1); | |
83 | } | |
84 | ||
85 | __raw_writel(camdivn, S3C2440_CAMDIVN); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
98a7069b SN |
90 | static unsigned long s3c2440_camif_upll_getrate(struct clk *clk) |
91 | { | |
92 | unsigned long parent_rate = clk_get_rate(clk->parent); | |
93 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); | |
94 | ||
95 | if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL)) | |
96 | return parent_rate; | |
97 | ||
98 | camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK; | |
99 | ||
100 | return parent_rate / (camdivn + 1) / 2; | |
101 | } | |
102 | ||
e44c0396 BD |
103 | /* Extra S3C2440 clocks */ |
104 | ||
a8d11e3d BD |
105 | static struct clk s3c2440_clk_cam = { |
106 | .name = "camif", | |
99c13853 | 107 | .enable = s3c2410_clkcon_enable, |
a8d11e3d BD |
108 | .ctrlbit = S3C2440_CLKCON_CAMERA, |
109 | }; | |
110 | ||
e44c0396 BD |
111 | static struct clk s3c2440_clk_cam_upll = { |
112 | .name = "camif-upll", | |
b3bf41be BD |
113 | .ops = &(struct clk_ops) { |
114 | .set_rate = s3c2440_camif_upll_setrate, | |
98a7069b | 115 | .get_rate = s3c2440_camif_upll_getrate, |
b3bf41be BD |
116 | .round_rate = s3c2440_camif_upll_round, |
117 | }, | |
e44c0396 BD |
118 | }; |
119 | ||
a8d11e3d BD |
120 | static struct clk s3c2440_clk_ac97 = { |
121 | .name = "ac97", | |
99c13853 | 122 | .enable = s3c2410_clkcon_enable, |
bb148802 | 123 | .ctrlbit = S3C2440_CLKCON_AC97, |
a8d11e3d BD |
124 | }; |
125 | ||
046c217c TA |
126 | static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) |
127 | { | |
128 | unsigned long ucon0, ucon1, ucon2, divisor; | |
129 | ||
130 | /* the fun of calculating the uart divisors on the s3c2440 */ | |
131 | ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); | |
132 | ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); | |
133 | ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); | |
134 | ||
135 | ucon0 &= S3C2440_UCON0_DIVMASK; | |
136 | ucon1 &= S3C2440_UCON1_DIVMASK; | |
137 | ucon2 &= S3C2440_UCON2_DIVMASK; | |
138 | ||
139 | if (ucon0 != 0) | |
140 | divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6; | |
141 | else if (ucon1 != 0) | |
142 | divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21; | |
143 | else if (ucon2 != 0) | |
144 | divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36; | |
145 | else | |
146 | /* manual calims 44, seems to be 9 */ | |
147 | divisor = 9; | |
148 | ||
149 | return clk_get_rate(clk->parent) / divisor; | |
150 | } | |
151 | ||
152 | static struct clk s3c2440_clk_fclk_n = { | |
153 | .name = "fclk_n", | |
154 | .parent = &clk_f, | |
155 | .ops = &(struct clk_ops) { | |
156 | .get_rate = s3c2440_fclk_n_getrate, | |
157 | }, | |
158 | }; | |
159 | ||
0cfb26e1 TA |
160 | static struct clk_lookup s3c2440_clk_lookup[] = { |
161 | CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), | |
162 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), | |
163 | CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), | |
7d3b5fac | 164 | CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll), |
0cfb26e1 TA |
165 | }; |
166 | ||
5276b687 | 167 | static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) |
a8d11e3d | 168 | { |
3a38e4be | 169 | struct clk *clock_upll; |
e546e8af BD |
170 | struct clk *clock_h; |
171 | struct clk *clock_p; | |
a8d11e3d | 172 | |
e546e8af BD |
173 | clock_p = clk_get(NULL, "pclk"); |
174 | clock_h = clk_get(NULL, "hclk"); | |
175 | clock_upll = clk_get(NULL, "upll"); | |
a8d11e3d | 176 | |
e546e8af | 177 | if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { |
a8d11e3d BD |
178 | printk(KERN_ERR "S3C2440: Failed to get parent clocks\n"); |
179 | return -EINVAL; | |
180 | } | |
181 | ||
e546e8af BD |
182 | s3c2440_clk_cam.parent = clock_h; |
183 | s3c2440_clk_ac97.parent = clock_p; | |
184 | s3c2440_clk_cam_upll.parent = clock_upll; | |
046c217c | 185 | s3c24xx_register_clock(&s3c2440_clk_fclk_n); |
a8d11e3d BD |
186 | |
187 | s3c24xx_register_clock(&s3c2440_clk_ac97); | |
188 | s3c24xx_register_clock(&s3c2440_clk_cam); | |
e44c0396 | 189 | s3c24xx_register_clock(&s3c2440_clk_cam_upll); |
0cfb26e1 | 190 | clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup)); |
a8d11e3d BD |
191 | |
192 | clk_disable(&s3c2440_clk_ac97); | |
193 | clk_disable(&s3c2440_clk_cam); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
4a858cfc KS |
198 | static struct subsys_interface s3c2440_clk_interface = { |
199 | .name = "s3c2440_clk", | |
200 | .subsys = &s3c2440_subsys, | |
201 | .add_dev = s3c2440_clk_add, | |
a8d11e3d BD |
202 | }; |
203 | ||
4a858cfc | 204 | static __init int s3c24xx_clk_init(void) |
a8d11e3d | 205 | { |
4a858cfc | 206 | return subsys_interface_register(&s3c2440_clk_interface); |
a8d11e3d BD |
207 | } |
208 | ||
4a858cfc | 209 | arch_initcall(s3c24xx_clk_init); |