[deliverable/linux.git] / arch / arm / mach-s3c24xx / clock-s3c2440.c

/* linux/arch/arm/mach-s3c2440/clock.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2440 Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/serial_core.h>

#include <mach/hardware.h>
#include <linux/atomic.h>
#include <asm/irq.h>

#include <mach/regs-clock.h>

#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>

/* S3C2440 extended clock support */

static unsigned long s3c2440_camif_upll_round(struct clk *clk,
					      unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
		return parent_rate;

	/* note, we remove the +/- 1 calculations for the divisor */

	div = (parent_rate / rate) / 2;

	if (div < 1)
		div = 1;
	else if (div > 16)
		div = 16;

	return parent_rate / (div * 2);
}

static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);

	rate = s3c2440_camif_upll_round(clk, rate);

	camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);

	if (rate != parent_rate) {
		camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
		camdivn |= (((parent_rate / rate) / 2) - 1);
	}

	__raw_writel(camdivn, S3C2440_CAMDIVN);

	return 0;
}

/* Extra S3C2440 clocks */

static struct clk s3c2440_clk_cam = {
	.name		= "camif",
	.enable		= s3c2410_clkcon_enable,
	.ctrlbit	= S3C2440_CLKCON_CAMERA,
};

static struct clk s3c2440_clk_cam_upll = {
	.name		= "camif-upll",
	.ops		= &(struct clk_ops) {
		.set_rate	= s3c2440_camif_upll_setrate,
		.round_rate	= s3c2440_camif_upll_round,
	},
};

static struct clk s3c2440_clk_ac97 = {
	.name		= "ac97",
	.enable		= s3c2410_clkcon_enable,
	.ctrlbit	= S3C2440_CLKCON_AC97,
};

static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
{
	unsigned long ucon0, ucon1, ucon2, divisor;

	/* the fun of calculating the uart divisors on the s3c2440 */
	ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
	ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
	ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);

	ucon0 &= S3C2440_UCON0_DIVMASK;
	ucon1 &= S3C2440_UCON1_DIVMASK;
	ucon2 &= S3C2440_UCON2_DIVMASK;

	if (ucon0 != 0)
		divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
	else if (ucon1 != 0)
		divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
	else if (ucon2 != 0)
		divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
	else
		/* manual calims 44, seems to be 9 */
		divisor = 9;

	return clk_get_rate(clk->parent) / divisor;
}

static struct clk s3c2440_clk_fclk_n = {
	.name		= "fclk_n",
	.parent		= &clk_f,
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2440_fclk_n_getrate,
	},
};

static struct clk_lookup s3c2440_clk_lookup[] = {
	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
	CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
};

static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
{
	struct clk *clock_upll;
	struct clk *clock_h;
	struct clk *clock_p;

	clock_p = clk_get(NULL, "pclk");
	clock_h = clk_get(NULL, "hclk");
	clock_upll = clk_get(NULL, "upll");

	if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
		printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
		return -EINVAL;
	}

	s3c2440_clk_cam.parent = clock_h;
	s3c2440_clk_ac97.parent = clock_p;
	s3c2440_clk_cam_upll.parent = clock_upll;
	s3c24xx_register_clock(&s3c2440_clk_fclk_n);

	s3c24xx_register_clock(&s3c2440_clk_ac97);
	s3c24xx_register_clock(&s3c2440_clk_cam);
	s3c24xx_register_clock(&s3c2440_clk_cam_upll);
	clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));

	clk_disable(&s3c2440_clk_ac97);
	clk_disable(&s3c2440_clk_cam);

	return 0;
}

static struct subsys_interface s3c2440_clk_interface = {
	.name		= "s3c2440_clk",
	.subsys		= &s3c2440_subsys,
	.add_dev	= s3c2440_clk_add,
};

static __init int s3c24xx_clk_init(void)
{
	return subsys_interface_register(&s3c2440_clk_interface);
}

arch_initcall(s3c24xx_clk_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/clock.c
a8d11e3d BD	2	*
	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C2440 Clock support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#include <linux/init.h>
	25	#include <linux/module.h>
	26	#include <linux/kernel.h>
	27	#include <linux/list.h>
	28	#include <linux/errno.h>
	29	#include <linux/err.h>
	30	#include <linux/device.h>
a8d11e3d BD	31	#include <linux/interrupt.h>
a8d11e3d BD	32	#include <linux/ioport.h>
36c64af4	33	#include <linux/mutex.h>
f8ce2547	34	#include <linux/clk.h>
fced80c7	35	#include <linux/io.h>
046c217c	36	#include <linux/serial_core.h>
a8d11e3d	37
a09e64fb	38	#include <mach/hardware.h>
60063497	39	#include <linux/atomic.h>
a8d11e3d	40	#include <asm/irq.h>
a8d11e3d	41
a09e64fb	42	#include <mach/regs-clock.h>
a8d11e3d	43
d5120ae7	44	#include <plat/clock.h>
a2b7ba9c	45	#include <plat/cpu.h>
046c217c	46	#include <plat/regs-serial.h>
a8d11e3d BD	47
	48	/* S3C2440 extended clock support */
	49
e44c0396 BD	50	static unsigned long s3c2440_camif_upll_round(struct clk *clk,
	51	unsigned long rate)
	52	{
	53	unsigned long parent_rate = clk_get_rate(clk->parent);
	54	int div;
	55
	56	if (rate > parent_rate)
	57	return parent_rate;
	58
	59	/* note, we remove the +/- 1 calculations for the divisor */
	60
	61	div = (parent_rate / rate) / 2;
	62
	63	if (div < 1)
	64	div = 1;
	65	else if (div > 16)
	66	div = 16;
	67
	68	return parent_rate / (div * 2);
	69	}
	70
	71	static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
	72	{
	73	unsigned long parent_rate = clk_get_rate(clk->parent);
	74	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	75
	76	rate = s3c2440_camif_upll_round(clk, rate);
	77
	78	camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL \| S3C2440_CAMDIVN_CAMCLK_MASK);
	79
	80	if (rate != parent_rate) {
	81	camdivn \|= S3C2440_CAMDIVN_CAMCLK_SEL;
	82	camdivn \|= (((parent_rate / rate) / 2) - 1);
	83	}
	84
	85	__raw_writel(camdivn, S3C2440_CAMDIVN);
	86
	87	return 0;
	88	}
	89
	90	/* Extra S3C2440 clocks */
	91
a8d11e3d BD	92	static struct clk s3c2440_clk_cam = {
a8d11e3d BD	93	.name = "camif",
99c13853	94	.enable = s3c2410_clkcon_enable,
a8d11e3d BD	95	.ctrlbit = S3C2440_CLKCON_CAMERA,
	96	};
	97
e44c0396 BD	98	static struct clk s3c2440_clk_cam_upll = {
e44c0396 BD	99	.name = "camif-upll",
b3bf41be BD	100	.ops = &(struct clk_ops) {
	101	.set_rate = s3c2440_camif_upll_setrate,
	102	.round_rate = s3c2440_camif_upll_round,
	103	},
e44c0396 BD	104	};
e44c0396 BD	105
a8d11e3d BD	106	static struct clk s3c2440_clk_ac97 = {
a8d11e3d BD	107	.name = "ac97",
99c13853	108	.enable = s3c2410_clkcon_enable,
bb148802	109	.ctrlbit = S3C2440_CLKCON_AC97,
a8d11e3d BD	110	};
a8d11e3d BD	111
046c217c TA	112	static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
	113	{
	114	unsigned long ucon0, ucon1, ucon2, divisor;
	115
	116	/* the fun of calculating the uart divisors on the s3c2440 */
	117	ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
	118	ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
	119	ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
	120
	121	ucon0 &= S3C2440_UCON0_DIVMASK;
	122	ucon1 &= S3C2440_UCON1_DIVMASK;
	123	ucon2 &= S3C2440_UCON2_DIVMASK;
	124
	125	if (ucon0 != 0)
	126	divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
	127	else if (ucon1 != 0)
	128	divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
	129	else if (ucon2 != 0)
	130	divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
	131	else
	132	/* manual calims 44, seems to be 9 */
	133	divisor = 9;
	134
	135	return clk_get_rate(clk->parent) / divisor;
	136	}
	137
	138	static struct clk s3c2440_clk_fclk_n = {
	139	.name = "fclk_n",
	140	.parent = &clk_f,
	141	.ops = &(struct clk_ops) {
	142	.get_rate = s3c2440_fclk_n_getrate,
	143	},
	144	};
	145
0cfb26e1 TA	146	static struct clk_lookup s3c2440_clk_lookup[] = {
	147	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
	148	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
	149	CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
	150	};
	151
04511a6f	152	static int s3c2440_clk_add(struct device dev, struct subsys_interface sif)
a8d11e3d	153	{
3a38e4be	154	struct clk *clock_upll;
e546e8af BD	155	struct clk *clock_h;
e546e8af BD	156	struct clk *clock_p;
a8d11e3d	157
e546e8af BD	158	clock_p = clk_get(NULL, "pclk");
	159	clock_h = clk_get(NULL, "hclk");
	160	clock_upll = clk_get(NULL, "upll");
a8d11e3d	161
e546e8af	162	if (IS_ERR(clock_p) \|\| IS_ERR(clock_h) \|\| IS_ERR(clock_upll)) {
a8d11e3d BD	163	printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
	164	return -EINVAL;
	165	}
	166
e546e8af BD	167	s3c2440_clk_cam.parent = clock_h;
	168	s3c2440_clk_ac97.parent = clock_p;
	169	s3c2440_clk_cam_upll.parent = clock_upll;
046c217c	170	s3c24xx_register_clock(&s3c2440_clk_fclk_n);
a8d11e3d BD	171
	172	s3c24xx_register_clock(&s3c2440_clk_ac97);
	173	s3c24xx_register_clock(&s3c2440_clk_cam);
e44c0396	174	s3c24xx_register_clock(&s3c2440_clk_cam_upll);
0cfb26e1	175	clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
a8d11e3d BD	176
	177	clk_disable(&s3c2440_clk_ac97);
	178	clk_disable(&s3c2440_clk_cam);
	179
	180	return 0;
	181	}
	182
4a858cfc KS	183	static struct subsys_interface s3c2440_clk_interface = {
	184	.name = "s3c2440_clk",
	185	.subsys = &s3c2440_subsys,
	186	.add_dev = s3c2440_clk_add,
a8d11e3d BD	187	};
a8d11e3d BD	188
4a858cfc	189	static __init int s3c24xx_clk_init(void)
a8d11e3d	190	{
4a858cfc	191	return subsys_interface_register(&s3c2440_clk_interface);
a8d11e3d BD	192	}
a8d11e3d BD	193
4a858cfc	194	arch_initcall(s3c24xx_clk_init);