[deliverable/linux.git] / arch / arm / mach-s3c24xx / clock-s3c2440.c

/* linux/arch/arm/mach-s3c2440/clock.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2440 Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/serial_core.h>

#include <mach/hardware.h>
#include <linux/atomic.h>
#include <asm/irq.h>

#include <mach/regs-clock.h>

#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>

/* S3C2440 extended clock support */

static unsigned long s3c2440_camif_upll_round(struct clk *clk,
					      unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
		return parent_rate;

	/* note, we remove the +/- 1 calculations for the divisor */

	div = (parent_rate / rate) / 2;

	if (div < 1)
		div = 1;
	else if (div > 16)
		div = 16;

	return parent_rate / (div * 2);
}

static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);

	rate = s3c2440_camif_upll_round(clk, rate);

	camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);

	if (rate != parent_rate) {
		camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
		camdivn |= (((parent_rate / rate) / 2) - 1);
	}

	__raw_writel(camdivn, S3C2440_CAMDIVN);

	return 0;
}

static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);

	if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
		return parent_rate;

	camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;

	return parent_rate / (camdivn + 1) / 2;
}

/* Extra S3C2440 clocks */

static struct clk s3c2440_clk_cam = {
	.name		= "camif",
	.enable		= s3c2410_clkcon_enable,
	.ctrlbit	= S3C2440_CLKCON_CAMERA,
};

static struct clk s3c2440_clk_cam_upll = {
	.name		= "camif-upll",
	.ops		= &(struct clk_ops) {
		.set_rate	= s3c2440_camif_upll_setrate,
		.get_rate	= s3c2440_camif_upll_getrate,
		.round_rate	= s3c2440_camif_upll_round,
	},
};

static struct clk s3c2440_clk_ac97 = {
	.name		= "ac97",
	.enable		= s3c2410_clkcon_enable,
	.ctrlbit	= S3C2440_CLKCON_AC97,
};

#define S3C24XX_VA_UART0      (S3C_VA_UART)
#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )

static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
{
	unsigned long ucon0, ucon1, ucon2, divisor;

	/* the fun of calculating the uart divisors on the s3c2440 */
	ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
	ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
	ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);

	ucon0 &= S3C2440_UCON0_DIVMASK;
	ucon1 &= S3C2440_UCON1_DIVMASK;
	ucon2 &= S3C2440_UCON2_DIVMASK;

	if (ucon0 != 0)
		divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
	else if (ucon1 != 0)
		divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
	else if (ucon2 != 0)
		divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
	else
		/* manual calims 44, seems to be 9 */
		divisor = 9;

	return clk_get_rate(clk->parent) / divisor;
}

static struct clk s3c2440_clk_fclk_n = {
	.name		= "fclk_n",
	.parent		= &clk_f,
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2440_fclk_n_getrate,
	},
};

static struct clk_lookup s3c2440_clk_lookup[] = {
	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
	CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
	CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
	CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
	CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
	CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
};

static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
{
	struct clk *clock_upll;
	struct clk *clock_h;
	struct clk *clock_p;

	clock_p = clk_get(NULL, "pclk");
	clock_h = clk_get(NULL, "hclk");
	clock_upll = clk_get(NULL, "upll");

	if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
		printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
		return -EINVAL;
	}

	s3c2440_clk_cam.parent = clock_h;
	s3c2440_clk_ac97.parent = clock_p;
	s3c2440_clk_cam_upll.parent = clock_upll;
	s3c24xx_register_clock(&s3c2440_clk_fclk_n);

	s3c24xx_register_clock(&s3c2440_clk_ac97);
	s3c24xx_register_clock(&s3c2440_clk_cam);
	s3c24xx_register_clock(&s3c2440_clk_cam_upll);
	clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));

	clk_disable(&s3c2440_clk_ac97);
	clk_disable(&s3c2440_clk_cam);

	return 0;
}

static struct subsys_interface s3c2440_clk_interface = {
	.name		= "s3c2440_clk",
	.subsys		= &s3c2440_subsys,
	.add_dev	= s3c2440_clk_add,
};

static __init int s3c24xx_clk_init(void)
{
	return subsys_interface_register(&s3c2440_clk_interface);
}

arch_initcall(s3c24xx_clk_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/clock.c
a8d11e3d BD	2	*
	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C2440 Clock support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#include <linux/init.h>
	25	#include <linux/module.h>
	26	#include <linux/kernel.h>
	27	#include <linux/list.h>
	28	#include <linux/errno.h>
	29	#include <linux/err.h>
	30	#include <linux/device.h>
a8d11e3d BD	31	#include <linux/interrupt.h>
a8d11e3d BD	32	#include <linux/ioport.h>
36c64af4	33	#include <linux/mutex.h>
f8ce2547	34	#include <linux/clk.h>
fced80c7	35	#include <linux/io.h>
046c217c	36	#include <linux/serial_core.h>
a8d11e3d	37
a09e64fb	38	#include <mach/hardware.h>
60063497	39	#include <linux/atomic.h>
a8d11e3d	40	#include <asm/irq.h>
a8d11e3d	41
a09e64fb	42	#include <mach/regs-clock.h>
a8d11e3d	43
d5120ae7	44	#include <plat/clock.h>
a2b7ba9c	45	#include <plat/cpu.h>
046c217c	46	#include <plat/regs-serial.h>
a8d11e3d BD	47
	48	/* S3C2440 extended clock support */
	49
e44c0396 BD	50	static unsigned long s3c2440_camif_upll_round(struct clk *clk,
	51	unsigned long rate)
	52	{
	53	unsigned long parent_rate = clk_get_rate(clk->parent);
	54	int div;
	55
	56	if (rate > parent_rate)
	57	return parent_rate;
	58
	59	/* note, we remove the +/- 1 calculations for the divisor */
	60
	61	div = (parent_rate / rate) / 2;
	62
	63	if (div < 1)
	64	div = 1;
	65	else if (div > 16)
	66	div = 16;
	67
	68	return parent_rate / (div * 2);
	69	}
	70
	71	static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
	72	{
	73	unsigned long parent_rate = clk_get_rate(clk->parent);
	74	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	75
	76	rate = s3c2440_camif_upll_round(clk, rate);
	77
	78	camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL \| S3C2440_CAMDIVN_CAMCLK_MASK);
	79
	80	if (rate != parent_rate) {
	81	camdivn \|= S3C2440_CAMDIVN_CAMCLK_SEL;
	82	camdivn \|= (((parent_rate / rate) / 2) - 1);
	83	}
	84
	85	__raw_writel(camdivn, S3C2440_CAMDIVN);
	86
	87	return 0;
	88	}
	89
98a7069b SN	90	static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
	91	{
	92	unsigned long parent_rate = clk_get_rate(clk->parent);
	93	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	94
	95	if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
	96	return parent_rate;
	97
	98	camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
	99
	100	return parent_rate / (camdivn + 1) / 2;
	101	}
	102
e44c0396 BD	103	/* Extra S3C2440 clocks */
e44c0396 BD	104
a8d11e3d BD	105	static struct clk s3c2440_clk_cam = {
a8d11e3d BD	106	.name = "camif",
99c13853	107	.enable = s3c2410_clkcon_enable,
a8d11e3d BD	108	.ctrlbit = S3C2440_CLKCON_CAMERA,
	109	};
	110
e44c0396 BD	111	static struct clk s3c2440_clk_cam_upll = {
e44c0396 BD	112	.name = "camif-upll",
b3bf41be BD	113	.ops = &(struct clk_ops) {
b3bf41be BD	114	.set_rate = s3c2440_camif_upll_setrate,
98a7069b	115	.get_rate = s3c2440_camif_upll_getrate,
b3bf41be BD	116	.round_rate = s3c2440_camif_upll_round,
b3bf41be BD	117	},
e44c0396 BD	118	};
e44c0396 BD	119
a8d11e3d BD	120	static struct clk s3c2440_clk_ac97 = {
a8d11e3d BD	121	.name = "ac97",
99c13853	122	.enable = s3c2410_clkcon_enable,
bb148802	123	.ctrlbit = S3C2440_CLKCON_AC97,
a8d11e3d BD	124	};
a8d11e3d BD	125
9ee51f01 AB	126	#define S3C24XX_VA_UART0 (S3C_VA_UART)
	127	#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
	128	#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
	129	#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
	130
046c217c TA	131	static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
	132	{
	133	unsigned long ucon0, ucon1, ucon2, divisor;
	134
	135	/* the fun of calculating the uart divisors on the s3c2440 */
	136	ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
	137	ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
	138	ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
	139
	140	ucon0 &= S3C2440_UCON0_DIVMASK;
	141	ucon1 &= S3C2440_UCON1_DIVMASK;
	142	ucon2 &= S3C2440_UCON2_DIVMASK;
	143
	144	if (ucon0 != 0)
	145	divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
	146	else if (ucon1 != 0)
	147	divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
	148	else if (ucon2 != 0)
	149	divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
	150	else
	151	/* manual calims 44, seems to be 9 */
	152	divisor = 9;
	153
	154	return clk_get_rate(clk->parent) / divisor;
	155	}
	156
	157	static struct clk s3c2440_clk_fclk_n = {
	158	.name = "fclk_n",
	159	.parent = &clk_f,
	160	.ops = &(struct clk_ops) {
	161	.get_rate = s3c2440_fclk_n_getrate,
	162	},
	163	};
	164
0cfb26e1 TA	165	static struct clk_lookup s3c2440_clk_lookup[] = {
	166	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
	167	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
	168	CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
d817468c SN	169	CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
	170	CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
	171	CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
7d3b5fac	172	CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
0cfb26e1 TA	173	};
0cfb26e1 TA	174
5276b687	175	static int __init_refok s3c2440_clk_add(struct device dev, struct subsys_interface sif)
a8d11e3d	176	{
3a38e4be	177	struct clk *clock_upll;
e546e8af BD	178	struct clk *clock_h;
e546e8af BD	179	struct clk *clock_p;
a8d11e3d	180
e546e8af BD	181	clock_p = clk_get(NULL, "pclk");
	182	clock_h = clk_get(NULL, "hclk");
	183	clock_upll = clk_get(NULL, "upll");
a8d11e3d	184
e546e8af	185	if (IS_ERR(clock_p) \|\| IS_ERR(clock_h) \|\| IS_ERR(clock_upll)) {
a8d11e3d BD	186	printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
	187	return -EINVAL;
	188	}
	189
e546e8af BD	190	s3c2440_clk_cam.parent = clock_h;
	191	s3c2440_clk_ac97.parent = clock_p;
	192	s3c2440_clk_cam_upll.parent = clock_upll;
046c217c	193	s3c24xx_register_clock(&s3c2440_clk_fclk_n);
a8d11e3d BD	194
	195	s3c24xx_register_clock(&s3c2440_clk_ac97);
	196	s3c24xx_register_clock(&s3c2440_clk_cam);
e44c0396	197	s3c24xx_register_clock(&s3c2440_clk_cam_upll);
0cfb26e1	198	clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
a8d11e3d BD	199
	200	clk_disable(&s3c2440_clk_ac97);
	201	clk_disable(&s3c2440_clk_cam);
	202
	203	return 0;
	204	}
	205
4a858cfc KS	206	static struct subsys_interface s3c2440_clk_interface = {
	207	.name = "s3c2440_clk",
	208	.subsys = &s3c2440_subsys,
	209	.add_dev = s3c2440_clk_add,
a8d11e3d BD	210	};
a8d11e3d BD	211
4a858cfc	212	static __init int s3c24xx_clk_init(void)
a8d11e3d	213	{
4a858cfc	214	return subsys_interface_register(&s3c2440_clk_interface);
a8d11e3d BD	215	}
a8d11e3d BD	216
4a858cfc	217	arch_initcall(s3c24xx_clk_init);