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e4d06e39 BD |
1 | /* linux/arch/arm/mach-s3c2443/clock.c |
2 | * | |
4bed36b2 | 3 | * Copyright (c) 2007, 2010 Simtec Electronics |
e4d06e39 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2443 Clock control support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
af337f3e | 24 | |
e4d06e39 BD |
25 | #include <linux/module.h> |
26 | #include <linux/kernel.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/err.h> | |
edbaa603 | 30 | #include <linux/device.h> |
e4d06e39 BD |
31 | #include <linux/clk.h> |
32 | #include <linux/mutex.h> | |
e4d06e39 | 33 | #include <linux/serial_core.h> |
fced80c7 | 34 | #include <linux/io.h> |
e4d06e39 BD |
35 | |
36 | #include <asm/mach/map.h> | |
37 | ||
a09e64fb | 38 | #include <mach/hardware.h> |
e4d06e39 | 39 | |
a09e64fb | 40 | #include <mach/regs-s3c2443-clock.h> |
e4d06e39 | 41 | |
e425382e BD |
42 | #include <plat/cpu-freq.h> |
43 | ||
d5120ae7 | 44 | #include <plat/clock.h> |
9aa753c4 | 45 | #include <plat/clock-clksrc.h> |
a2b7ba9c | 46 | #include <plat/cpu.h> |
e4d06e39 BD |
47 | |
48 | /* We currently have to assume that the system is running | |
49 | * from the XTPll input, and that all ***REFCLKs are being | |
50 | * fed from it, as we cannot read the state of OM[4] from | |
51 | * software. | |
52 | * | |
53 | * It would be possible for each board initialisation to | |
54 | * set the correct muxing at initialisation | |
55 | */ | |
56 | ||
e4d06e39 BD |
57 | /* clock selections */ |
58 | ||
ba7622a1 BD |
59 | /* armdiv |
60 | * | |
61 | * this clock is sourced from msysclk and can have a number of | |
62 | * divider values applied to it to then be fed into armclk. | |
aab08eeb HS |
63 | * The real clock definition is done in s3c2443-clock.c, |
64 | * only the armdiv divisor table must be defined here. | |
ba7622a1 BD |
65 | */ |
66 | ||
41f23a09 BD |
67 | static unsigned int armdiv[16] = { |
68 | [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, | |
69 | [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, | |
70 | [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, | |
71 | [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, | |
72 | [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, | |
73 | [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, | |
74 | [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, | |
75 | [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, | |
76 | }; | |
77 | ||
e4d06e39 BD |
78 | /* hsspi |
79 | * | |
80 | * high-speed spi clock, sourced from esysclk | |
81 | */ | |
82 | ||
9aa753c4 BD |
83 | static struct clksrc_clk clk_hsspi = { |
84 | .clk = { | |
8b069b77 | 85 | .name = "hsspi-if", |
4bed36b2 | 86 | .parent = &clk_esysclk.clk, |
9aa753c4 BD |
87 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, |
88 | .enable = s3c2443_clkcon_enable_s, | |
b3bf41be | 89 | }, |
9aa753c4 | 90 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, |
e4d06e39 BD |
91 | }; |
92 | ||
e4d06e39 BD |
93 | |
94 | /* clk_hsmcc_div | |
95 | * | |
96 | * this clock is sourced from epll, and is fed through a divider, | |
97 | * to a mux controlled by sclkcon where either it or a extclk can | |
98 | * be fed to the hsmmc block | |
99 | */ | |
100 | ||
9aa753c4 BD |
101 | static struct clksrc_clk clk_hsmmc_div = { |
102 | .clk = { | |
103 | .name = "hsmmc-div", | |
e83626f2 | 104 | .devname = "s3c-sdhci.1", |
4bed36b2 | 105 | .parent = &clk_esysclk.clk, |
b3bf41be | 106 | }, |
9aa753c4 | 107 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, |
e4d06e39 BD |
108 | }; |
109 | ||
110 | static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) | |
111 | { | |
112 | unsigned long clksrc = __raw_readl(S3C2443_SCLKCON); | |
113 | ||
114 | clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT | | |
115 | S3C2443_SCLKCON_HSMMCCLK_EPLL); | |
116 | ||
117 | if (parent == &clk_epll) | |
118 | clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL; | |
119 | else if (parent == &clk_ext) | |
120 | clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT; | |
121 | else | |
122 | return -EINVAL; | |
123 | ||
124 | if (clk->usage > 0) { | |
125 | __raw_writel(clksrc, S3C2443_SCLKCON); | |
126 | } | |
127 | ||
128 | clk->parent = parent; | |
129 | return 0; | |
130 | } | |
131 | ||
132 | static int s3c2443_enable_hsmmc(struct clk *clk, int enable) | |
133 | { | |
134 | return s3c2443_setparent_hsmmc(clk, clk->parent); | |
135 | } | |
136 | ||
137 | static struct clk clk_hsmmc = { | |
138 | .name = "hsmmc-if", | |
e83626f2 | 139 | .devname = "s3c-sdhci.1", |
9aa753c4 | 140 | .parent = &clk_hsmmc_div.clk, |
e4d06e39 | 141 | .enable = s3c2443_enable_hsmmc, |
b3bf41be BD |
142 | .ops = &(struct clk_ops) { |
143 | .set_parent = s3c2443_setparent_hsmmc, | |
144 | }, | |
e4d06e39 BD |
145 | }; |
146 | ||
e4d06e39 BD |
147 | /* standard clock definitions */ |
148 | ||
4e04691b | 149 | static struct clk init_clocks_off[] = { |
e4d06e39 | 150 | { |
e4d06e39 | 151 | .name = "sdi", |
e4d06e39 BD |
152 | .parent = &clk_p, |
153 | .enable = s3c2443_clkcon_enable_p, | |
154 | .ctrlbit = S3C2443_PCLKCON_SDI, | |
e4d06e39 BD |
155 | }, { |
156 | .name = "spi", | |
e83626f2 | 157 | .devname = "s3c2410-spi.0", |
e4d06e39 BD |
158 | .parent = &clk_p, |
159 | .enable = s3c2443_clkcon_enable_p, | |
e4d06e39 BD |
160 | .ctrlbit = S3C2443_PCLKCON_SPI1, |
161 | } | |
162 | }; | |
163 | ||
e4d06e39 BD |
164 | /* clocks to add straight away */ |
165 | ||
9aa753c4 | 166 | static struct clksrc_clk *clksrcs[] __initdata = { |
e4d06e39 BD |
167 | &clk_hsspi, |
168 | &clk_hsmmc_div, | |
9aa753c4 BD |
169 | }; |
170 | ||
171 | static struct clk *clks[] __initdata = { | |
e4d06e39 BD |
172 | &clk_hsmmc, |
173 | }; | |
174 | ||
d25a8f94 HS |
175 | static struct clk_lookup s3c2443_clk_lookup[] = { |
176 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), | |
a5238e36 | 177 | CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk), |
d25a8f94 HS |
178 | }; |
179 | ||
e425382e BD |
180 | void __init s3c2443_init_clocks(int xtal) |
181 | { | |
e425382e | 182 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); |
e425382e BD |
183 | int ptr; |
184 | ||
af337f3e BD |
185 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); |
186 | clk_epll.parent = &clk_epllref.clk; | |
187 | ||
33ccedfd | 188 | s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, |
d9a3bfbd HS |
189 | armdiv, ARRAY_SIZE(armdiv), |
190 | S3C2443_CLKDIV0_ARMDIV_MASK); | |
e425382e | 191 | |
4e04691b | 192 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
e4d06e39 | 193 | |
9aa753c4 BD |
194 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
195 | s3c_register_clksrc(clksrcs[ptr], 1); | |
196 | ||
e4d06e39 | 197 | /* We must be careful disabling the clocks we are not intending to |
3a4fa0a2 | 198 | * be using at boot time, as subsystems such as the LCD which do |
e4d06e39 BD |
199 | * their own DMA requests to the bus can cause the system to lockup |
200 | * if they where in the middle of requesting bus access. | |
201 | * | |
202 | * Disabling the LCD clock if the LCD is active is very dangerous, | |
203 | * and therefore the bootloader should be careful to not enable | |
204 | * the LCD clock if it is not needed. | |
205 | */ | |
206 | ||
207 | /* install (and disable) the clocks we do not need immediately */ | |
208 | ||
4e04691b BD |
209 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
210 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
d25a8f94 | 211 | clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); |
e4d06e39 | 212 | } |