[deliverable/linux.git] / arch / arm / mach-s3c24xx / common.c

/* linux/arch/arm/plat-s3c24xx/cpu.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	http://www.simtec.co.uk/products/SWLINUX/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * Common code for S3C24XX machines
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/


#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <asm/irq.h>
#include <asm/cacheflush.h>
#include <asm/system_info.h>
#include <asm/system_misc.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s3c2410.h>
#include <plat/s3c2412.h>
#include <plat/s3c2416.h>
#include <plat/s3c244x.h>
#include <plat/s3c2443.h>

/* table of supported CPUs */

static const char name_s3c2410[]  = "S3C2410";
static const char name_s3c2412[]  = "S3C2412";
static const char name_s3c2416[]  = "S3C2416/S3C2450";
static const char name_s3c2440[]  = "S3C2440";
static const char name_s3c2442[]  = "S3C2442";
static const char name_s3c2442b[]  = "S3C2442B";
static const char name_s3c2443[]  = "S3C2443";
static const char name_s3c2410a[] = "S3C2410A";
static const char name_s3c2440a[] = "S3C2440A";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= 0x32410000,
		.idmask		= 0xffffffff,
		.map_io		= s3c2410_map_io,
		.init_clocks	= s3c2410_init_clocks,
		.init_uarts	= s3c2410_init_uarts,
		.init		= s3c2410_init,
		.name		= name_s3c2410
	},
	{
		.idcode		= 0x32410002,
		.idmask		= 0xffffffff,
		.map_io		= s3c2410_map_io,
		.init_clocks	= s3c2410_init_clocks,
		.init_uarts	= s3c2410_init_uarts,
		.init		= s3c2410a_init,
		.name		= name_s3c2410a
	},
	{
		.idcode		= 0x32440000,
		.idmask		= 0xffffffff,
		.map_io		= s3c2440_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2440_init,
		.name		= name_s3c2440
	},
	{
		.idcode		= 0x32440001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2440_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2440_init,
		.name		= name_s3c2440a
	},
	{
		.idcode		= 0x32440aaa,
		.idmask		= 0xffffffff,
		.map_io		= s3c2442_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2442_init,
		.name		= name_s3c2442
	},
	{
		.idcode		= 0x32440aab,
		.idmask		= 0xffffffff,
		.map_io		= s3c2442_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2442_init,
		.name		= name_s3c2442b
	},
	{
		.idcode		= 0x32412001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2412_map_io,
		.init_clocks	= s3c2412_init_clocks,
		.init_uarts	= s3c2412_init_uarts,
		.init		= s3c2412_init,
		.name		= name_s3c2412,
	},
	{			/* a newer version of the s3c2412 */
		.idcode		= 0x32412003,
		.idmask		= 0xffffffff,
		.map_io		= s3c2412_map_io,
		.init_clocks	= s3c2412_init_clocks,
		.init_uarts	= s3c2412_init_uarts,
		.init		= s3c2412_init,
		.name		= name_s3c2412,
	},
	{			/* a strange version of the s3c2416 */
		.idcode		= 0x32450003,
		.idmask		= 0xffffffff,
		.map_io		= s3c2416_map_io,
		.init_clocks	= s3c2416_init_clocks,
		.init_uarts	= s3c2416_init_uarts,
		.init		= s3c2416_init,
		.name		= name_s3c2416,
	},
	{
		.idcode		= 0x32443001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2443_map_io,
		.init_clocks	= s3c2443_init_clocks,
		.init_uarts	= s3c2443_init_uarts,
		.init		= s3c2443_init,
		.name		= name_s3c2443,
	},
};

/* minimal IO mapping */

static struct map_desc s3c_iodesc[] __initdata = {
	IODESC_ENT(GPIO),
	IODESC_ENT(IRQ),
	IODESC_ENT(MEMCTRL),
	IODESC_ENT(UART)
};

/* read cpu identificaiton code */

static unsigned long s3c24xx_read_idcode_v5(void)
{
#if defined(CONFIG_CPU_S3C2416)
	/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */

	u32 gs = __raw_readl(S3C24XX_GSTATUS1);

	/* test for s3c2416 or similar device */
	if ((gs >> 16) == 0x3245)
		return gs;
#endif

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
	return __raw_readl(S3C2412_GSTATUS1);
#else
	return 1UL;	/* don't look like an 2400 */
#endif
}

static unsigned long s3c24xx_read_idcode_v4(void)
{
	return __raw_readl(S3C2410_GSTATUS1);
}

static void s3c24xx_default_idle(void)
{
	unsigned long tmp;
	int i;

	/* idle the system by using the idle mode which will wait for an
	 * interrupt to happen before restarting the system.
	 */

	/* Warning: going into idle state upsets jtag scanning */

	__raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
		     S3C2410_CLKCON);

	/* the samsung port seems to do a loop and then unset idle.. */
	for (i = 0; i < 50; i++)
		tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */

	/* this bit is not cleared on re-start... */

	__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
		     S3C2410_CLKCON);
}

void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
{
	arm_pm_idle = s3c24xx_default_idle;

	/* initialise the io descriptors we need for initialisation */
	iotable_init(mach_desc, size);
	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));

	if (cpu_architecture() >= CPU_ARCH_ARMv5) {
		samsung_cpu_id = s3c24xx_read_idcode_v5();
	} else {
		samsung_cpu_id = s3c24xx_read_idcode_v4();
	}
	s3c24xx_init_cpu();

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/plat-s3c24xx/cpu.c
1da177e4 LT	2	*
	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* http://www.simtec.co.uk/products/SWLINUX/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
4a9f52fd	7	* Common code for S3C24XX machines
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/ioport.h>
b6d1f542	29	#include <linux/serial_core.h>
d052d1be	30	#include <linux/platform_device.h>
3c7d9c81	31	#include <linux/delay.h>
fced80c7	32	#include <linux/io.h>
1da177e4	33
a09e64fb	34	#include <mach/hardware.h>
92311272	35	#include <mach/regs-clock.h>
1da177e4	36	#include <asm/irq.h>
3c7d9c81	37	#include <asm/cacheflush.h>
9f97da78	38	#include <asm/system_info.h>
86dfe446	39	#include <asm/system_misc.h>
1da177e4 LT	40
	41	#include <asm/mach/arch.h>
	42	#include <asm/mach/map.h>
	43
a09e64fb	44	#include <mach/regs-gpio.h>
a2b7ba9c	45	#include <plat/regs-serial.h>
1da177e4	46
a2b7ba9c BD	47	#include <plat/cpu.h>
a2b7ba9c BD	48	#include <plat/devs.h>
d5120ae7	49	#include <plat/clock.h>
a2b7ba9c	50	#include <plat/s3c2410.h>
d5120ae7	51	#include <plat/s3c2412.h>
f1290a49	52	#include <plat/s3c2416.h>
58bac7b8	53	#include <plat/s3c244x.h>
a2b7ba9c	54	#include <plat/s3c2443.h>
1da177e4	55
1da177e4 LT	56	/* table of supported CPUs */
	57
	58	static const char name_s3c2410[] = "S3C2410";
68d9ab39	59	static const char name_s3c2412[] = "S3C2412";
63b1f51b	60	static const char name_s3c2416[] = "S3C2416/S3C2450";
1da177e4	61	static const char name_s3c2440[] = "S3C2440";
96ce2385	62	static const char name_s3c2442[] = "S3C2442";
f5fb9b1a	63	static const char name_s3c2442b[] = "S3C2442B";
e4d06e39	64	static const char name_s3c2443[] = "S3C2443";
1da177e4 LT	65	static const char name_s3c2410a[] = "S3C2410A";
	66	static const char name_s3c2440a[] = "S3C2440A";
	67
	68	static struct cpu_table cpu_ids[] __initdata = {
	69	{
	70	.idcode = 0x32410000,
	71	.idmask = 0xffffffff,
	72	.map_io = s3c2410_map_io,
	73	.init_clocks = s3c2410_init_clocks,
	74	.init_uarts = s3c2410_init_uarts,
	75	.init = s3c2410_init,
	76	.name = name_s3c2410
	77	},
	78	{
	79	.idcode = 0x32410002,
	80	.idmask = 0xffffffff,
	81	.map_io = s3c2410_map_io,
	82	.init_clocks = s3c2410_init_clocks,
	83	.init_uarts = s3c2410_init_uarts,
f0176794	84	.init = s3c2410a_init,
1da177e4 LT	85	.name = name_s3c2410a
	86	},
	87	{
	88	.idcode = 0x32440000,
	89	.idmask = 0xffffffff,
812c4e40	90	.map_io = s3c2440_map_io,
96ce2385 BD	91	.init_clocks = s3c244x_init_clocks,
96ce2385 BD	92	.init_uarts = s3c244x_init_uarts,
1da177e4 LT	93	.init = s3c2440_init,
	94	.name = name_s3c2440
	95	},
	96	{
	97	.idcode = 0x32440001,
	98	.idmask = 0xffffffff,
812c4e40	99	.map_io = s3c2440_map_io,
96ce2385 BD	100	.init_clocks = s3c244x_init_clocks,
96ce2385 BD	101	.init_uarts = s3c244x_init_uarts,
1da177e4 LT	102	.init = s3c2440_init,
1da177e4 LT	103	.name = name_s3c2440a
83f755f5	104	},
96ce2385 BD	105	{
	106	.idcode = 0x32440aaa,
	107	.idmask = 0xffffffff,
812c4e40	108	.map_io = s3c2442_map_io,
96ce2385 BD	109	.init_clocks = s3c244x_init_clocks,
	110	.init_uarts = s3c244x_init_uarts,
	111	.init = s3c2442_init,
	112	.name = name_s3c2442
	113	},
f5fb9b1a HW	114	{
	115	.idcode = 0x32440aab,
	116	.idmask = 0xffffffff,
812c4e40	117	.map_io = s3c2442_map_io,
f5fb9b1a HW	118	.init_clocks = s3c244x_init_clocks,
	119	.init_uarts = s3c244x_init_uarts,
	120	.init = s3c2442_init,
	121	.name = name_s3c2442b
	122	},
68d9ab39 BD	123	{
	124	.idcode = 0x32412001,
	125	.idmask = 0xffffffff,
	126	.map_io = s3c2412_map_io,
	127	.init_clocks = s3c2412_init_clocks,
	128	.init_uarts = s3c2412_init_uarts,
	129	.init = s3c2412_init,
	130	.name = name_s3c2412,
	131	},
d9bc55fa BD	132	{ /* a newer version of the s3c2412 */
	133	.idcode = 0x32412003,
	134	.idmask = 0xffffffff,
	135	.map_io = s3c2412_map_io,
	136	.init_clocks = s3c2412_init_clocks,
	137	.init_uarts = s3c2412_init_uarts,
	138	.init = s3c2412_init,
	139	.name = name_s3c2412,
	140	},
f1290a49 YK	141	{ /* a strange version of the s3c2416 */
	142	.idcode = 0x32450003,
	143	.idmask = 0xffffffff,
	144	.map_io = s3c2416_map_io,
	145	.init_clocks = s3c2416_init_clocks,
	146	.init_uarts = s3c2416_init_uarts,
	147	.init = s3c2416_init,
	148	.name = name_s3c2416,
	149	},
e4d06e39 BD	150	{
	151	.idcode = 0x32443001,
	152	.idmask = 0xffffffff,
	153	.map_io = s3c2443_map_io,
	154	.init_clocks = s3c2443_init_clocks,
	155	.init_uarts = s3c2443_init_uarts,
	156	.init = s3c2443_init,
	157	.name = name_s3c2443,
	158	},
1da177e4 LT	159	};
	160
	161	/* minimal IO mapping */
	162
	163	static struct map_desc s3c_iodesc[] __initdata = {
	164	IODESC_ENT(GPIO),
	165	IODESC_ENT(IRQ),
	166	IODESC_ENT(MEMCTRL),
	167	IODESC_ENT(UART)
	168	};
	169
74b265d4	170	/* read cpu identificaiton code */
1da177e4	171
68d9ab39 BD	172	static unsigned long s3c24xx_read_idcode_v5(void)
68d9ab39 BD	173	{
d11a7d71 BD	174	#if defined(CONFIG_CPU_S3C2416)
	175	/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
	176
	177	u32 gs = __raw_readl(S3C24XX_GSTATUS1);
	178
	179	/* test for s3c2416 or similar device */
	180	if ((gs >> 16) == 0x3245)
	181	return gs;
	182	#endif
	183
68d9ab39 BD	184	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	185	return __raw_readl(S3C2412_GSTATUS1);
	186	#else
	187	return 1UL; /* don't look like an 2400 */
	188	#endif
	189	}
	190
	191	static unsigned long s3c24xx_read_idcode_v4(void)
	192	{
68d9ab39	193	return __raw_readl(S3C2410_GSTATUS1);
68d9ab39 BD	194	}
68d9ab39 BD	195
92311272 NP	196	static void s3c24xx_default_idle(void)
	197	{
	198	unsigned long tmp;
	199	int i;
	200
	201	/* idle the system by using the idle mode which will wait for an
	202	* interrupt to happen before restarting the system.
	203	*/
	204
	205	/* Warning: going into idle state upsets jtag scanning */
	206
	207	__raw_writel(__raw_readl(S3C2410_CLKCON) \| S3C2410_CLKCON_IDLE,
	208	S3C2410_CLKCON);
	209
	210	/* the samsung port seems to do a loop and then unset idle.. */
	211	for (i = 0; i < 50; i++)
	212	tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
	213
	214	/* this bit is not cleared on re-start... */
	215
	216	__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
	217	S3C2410_CLKCON);
	218	}
	219
1da177e4 LT	220	void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
1da177e4 LT	221	{
92311272 NP	222	arm_pm_idle = s3c24xx_default_idle;
92311272 NP	223
1da177e4	224	/* initialise the io descriptors we need for initialisation */
74b265d4	225	iotable_init(mach_desc, size);
1da177e4 LT	226	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
1da177e4 LT	227
68d9ab39	228	if (cpu_architecture() >= CPU_ARCH_ARMv5) {
c06af3cc	229	samsung_cpu_id = s3c24xx_read_idcode_v5();
68d9ab39	230	} else {
c06af3cc	231	samsung_cpu_id = s3c24xx_read_idcode_v4();
68d9ab39	232	}
e6d1cb9f	233	s3c24xx_init_cpu();
83f755f5	234
c06af3cc	235	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
66a9b49a	236	}