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Merge tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[deliverable/linux.git] / arch / arm / mach-s3c24xx / common.c
CommitLineData
a21765a7 1/* linux/arch/arm/plat-s3c24xx/cpu.c
1da177e4
LT		 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
4a9f52fd 7 * Common code for S3C24XX machines
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
b6d1f542 29#include <linux/serial_core.h>
334a1c70 30#include <linux/serial_s3c.h>
1c161fd0 31#include <clocksource/samsung_pwm.h>
d052d1be 32#include <linux/platform_device.h>
3c7d9c81 33#include <linux/delay.h>
fced80c7 34#include <linux/io.h>
f2dda07d 35#include <linux/platform_data/dma-s3c24xx.h>
1da177e4 36
a09e64fb 37#include <mach/hardware.h>
92311272 38#include <mach/regs-clock.h>
1da177e4 39#include <asm/irq.h>
3c7d9c81 40#include <asm/cacheflush.h>
9f97da78 41#include <asm/system_info.h>
86dfe446 42#include <asm/system_misc.h>
1da177e4
LT		 43
44#include <asm/mach/arch.h>
45#include <asm/mach/map.h>
46
a09e64fb 47#include <mach/regs-gpio.h>
f2dda07d 48#include <mach/dma.h>
1da177e4 49
a2b7ba9c
BD		 50#include <plat/cpu.h>
51#include <plat/devs.h>
2473f713 52#include <plat/cpu-freq.h>
1c161fd0 53#include <plat/pwm-core.h>
4659c534 54#include <plat/watchdog-reset.h>
1da177e4 55
e1a621da
HS		 56#include "common.h"
57
1da177e4
LT		 58/* table of supported CPUs */
59
60static const char name_s3c2410[] = "S3C2410";
68d9ab39 61static const char name_s3c2412[] = "S3C2412";
63b1f51b 62static const char name_s3c2416[] = "S3C2416/S3C2450";
1da177e4 63static const char name_s3c2440[] = "S3C2440";
96ce2385 64static const char name_s3c2442[] = "S3C2442";
f5fb9b1a 65static const char name_s3c2442b[] = "S3C2442B";
e4d06e39 66static const char name_s3c2443[] = "S3C2443";
1da177e4
LT		 67static const char name_s3c2410a[] = "S3C2410A";
68static const char name_s3c2440a[] = "S3C2440A";
69
70static struct cpu_table cpu_ids[] __initdata = {
71 {
72 .idcode = 0x32410000,
73 .idmask = 0xffffffff,
74 .map_io = s3c2410_map_io,
1da177e4
LT		 75 .init_uarts = s3c2410_init_uarts,
76 .init = s3c2410_init,
77 .name = name_s3c2410
78 },
79 {
80 .idcode = 0x32410002,
81 .idmask = 0xffffffff,
82 .map_io = s3c2410_map_io,
1da177e4 83 .init_uarts = s3c2410_init_uarts,
f0176794 84 .init = s3c2410a_init,
1da177e4
LT		 85 .name = name_s3c2410a
86 },
87 {
88 .idcode = 0x32440000,
89 .idmask = 0xffffffff,
812c4e40 90 .map_io = s3c2440_map_io,
96ce2385 91 .init_uarts = s3c244x_init_uarts,
1da177e4
LT		 92 .init = s3c2440_init,
93 .name = name_s3c2440
94 },
95 {
96 .idcode = 0x32440001,
97 .idmask = 0xffffffff,
812c4e40 98 .map_io = s3c2440_map_io,
96ce2385 99 .init_uarts = s3c244x_init_uarts,
1da177e4
LT		 100 .init = s3c2440_init,
101 .name = name_s3c2440a
83f755f5 102 },
96ce2385
BD		 103 {
104 .idcode = 0x32440aaa,
105 .idmask = 0xffffffff,
812c4e40 106 .map_io = s3c2442_map_io,
96ce2385
BD		 107 .init_uarts = s3c244x_init_uarts,
108 .init = s3c2442_init,
109 .name = name_s3c2442
110 },
f5fb9b1a
HW		 111 {
112 .idcode = 0x32440aab,
113 .idmask = 0xffffffff,
812c4e40 114 .map_io = s3c2442_map_io,
f5fb9b1a
HW		 115 .init_uarts = s3c244x_init_uarts,
116 .init = s3c2442_init,
117 .name = name_s3c2442b
118 },
68d9ab39
BD		 119 {
120 .idcode = 0x32412001,
121 .idmask = 0xffffffff,
122 .map_io = s3c2412_map_io,
68d9ab39
BD		 123 .init_uarts = s3c2412_init_uarts,
124 .init = s3c2412_init,
125 .name = name_s3c2412,
126 },
d9bc55fa
BD		 127 { /* a newer version of the s3c2412 */
128 .idcode = 0x32412003,
129 .idmask = 0xffffffff,
130 .map_io = s3c2412_map_io,
d9bc55fa
BD		 131 .init_uarts = s3c2412_init_uarts,
132 .init = s3c2412_init,
133 .name = name_s3c2412,
134 },
f1290a49
YK		 135 { /* a strange version of the s3c2416 */
136 .idcode = 0x32450003,
137 .idmask = 0xffffffff,
138 .map_io = s3c2416_map_io,
f1290a49
YK		 139 .init_uarts = s3c2416_init_uarts,
140 .init = s3c2416_init,
141 .name = name_s3c2416,
142 },
e4d06e39
BD		 143 {
144 .idcode = 0x32443001,
145 .idmask = 0xffffffff,
146 .map_io = s3c2443_map_io,
e4d06e39
BD		 147 .init_uarts = s3c2443_init_uarts,
148 .init = s3c2443_init,
149 .name = name_s3c2443,
150 },
1da177e4
LT		 151};
152
153/* minimal IO mapping */
154
155static struct map_desc s3c_iodesc[] __initdata = {
156 IODESC_ENT(GPIO),
157 IODESC_ENT(IRQ),
158 IODESC_ENT(MEMCTRL),
159 IODESC_ENT(UART)
160};
161
74b265d4 162/* read cpu identificaiton code */
1da177e4 163
68d9ab39
BD		 164static unsigned long s3c24xx_read_idcode_v5(void)
165{
d11a7d71
BD		 166#if defined(CONFIG_CPU_S3C2416)
167 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
168
169 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
170
171 /* test for s3c2416 or similar device */
172 if ((gs >> 16) == 0x3245)
173 return gs;
174#endif
175
68d9ab39
BD		 176#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
177 return __raw_readl(S3C2412_GSTATUS1);
178#else
179 return 1UL; /* don't look like an 2400 */
180#endif
181}
182
183static unsigned long s3c24xx_read_idcode_v4(void)
184{
68d9ab39 185 return __raw_readl(S3C2410_GSTATUS1);
68d9ab39
BD		 186}
187
92311272
NP		 188static void s3c24xx_default_idle(void)
189{
813f13e7 190 unsigned long tmp = 0;
92311272
NP		 191 int i;
192
193 /* idle the system by using the idle mode which will wait for an
194 * interrupt to happen before restarting the system.
195 */
196
197 /* Warning: going into idle state upsets jtag scanning */
198
199 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
200 S3C2410_CLKCON);
201
202 /* the samsung port seems to do a loop and then unset idle.. */
203 for (i = 0; i < 50; i++)
204 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
205
206 /* this bit is not cleared on re-start... */
207
208 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
209 S3C2410_CLKCON);
210}
211
1c161fd0
TF		 212static struct samsung_pwm_variant s3c24xx_pwm_variant = {
213 .bits = 16,
214 .div_base = 1,
215 .has_tint_cstat = false,
216 .tclk_mask = (1 << 4),
217};
218
1da177e4
LT		 219void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
220{
92311272
NP		 221 arm_pm_idle = s3c24xx_default_idle;
222
1da177e4 223 /* initialise the io descriptors we need for initialisation */
74b265d4 224 iotable_init(mach_desc, size);
1da177e4
LT		 225 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
226
68d9ab39 227 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
c06af3cc 228 samsung_cpu_id = s3c24xx_read_idcode_v5();
68d9ab39 229 } else {
c06af3cc 230 samsung_cpu_id = s3c24xx_read_idcode_v4();
68d9ab39 231 }
83f755f5 232
c06af3cc 233 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
1c161fd0
TF		 234
235 samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
66a9b49a 236}
618ae08a 237
4280506a
TF		 238void __init samsung_set_timer_source(unsigned int event, unsigned int source)
239{
240 s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
241 s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
242}
243
244void __init samsung_timer_init(void)
245{
246 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
247 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
248 };
249
250 samsung_pwm_clocksource_init(S3C_VA_TIMER,
251 timer_irqs, &s3c24xx_pwm_variant);
252}
253
618ae08a
HS		 254/* Serial port registrations */
255
9ee51f01
AB		 256#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
257#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
258#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
259#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
260
618ae08a 261static struct resource s3c2410_uart0_resource[] = {
99dbdd98
TB		 262 [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
263 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
264 IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
265 NULL, IORESOURCE_IRQ)
618ae08a
HS		 266};
267
268static struct resource s3c2410_uart1_resource[] = {
99dbdd98
TB		 269 [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
270 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
271 IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
272 NULL, IORESOURCE_IRQ)
618ae08a
HS		 273};
274
275static struct resource s3c2410_uart2_resource[] = {
99dbdd98
TB		 276 [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
277 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
278 IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
279 NULL, IORESOURCE_IRQ)
618ae08a
HS		 280};
281
282static struct resource s3c2410_uart3_resource[] = {
99dbdd98
TB		 283 [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
284 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
285 IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
286 NULL, IORESOURCE_IRQ)
618ae08a
HS		 287};
288
289struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
290 [0] = {
291 .resources = s3c2410_uart0_resource,
292 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
293 },
294 [1] = {
295 .resources = s3c2410_uart1_resource,
296 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
297 },
298 [2] = {
299 .resources = s3c2410_uart2_resource,
300 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
301 },
302 [3] = {
303 .resources = s3c2410_uart3_resource,
304 .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
305 },
306};
2473f713 307
f2dda07d
HS		 308#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
309 defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
310static struct resource s3c2410_dma_resource[] = {
311 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
312 [1] = DEFINE_RES_IRQ(IRQ_DMA0),
313 [2] = DEFINE_RES_IRQ(IRQ_DMA1),
314 [3] = DEFINE_RES_IRQ(IRQ_DMA2),
315 [4] = DEFINE_RES_IRQ(IRQ_DMA3),
316};
317#endif
318
1fecf895
HS		 319#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
320static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
321 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
322 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
323 [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
324 S3C24XX_DMA_CHANREQ(2, 2) |
325 S3C24XX_DMA_CHANREQ(1, 3),
326 },
327 [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
328 [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
329 [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
330 [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
331 [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
332 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
333 S3C24XX_DMA_CHANREQ(3, 2) |
334 S3C24XX_DMA_CHANREQ(3, 3),
335 },
336 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
337 S3C24XX_DMA_CHANREQ(1, 2),
338 },
339 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
340 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
341 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
342 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
343 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
344};
345
346static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
347 .num_phy_channels = 4,
348 .channels = s3c2410_dma_channels,
349 .num_channels = DMACH_MAX,
350};
351
352struct platform_device s3c2410_device_dma = {
353 .name = "s3c2410-dma",
354 .id = 0,
355 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
356 .resource = s3c2410_dma_resource,
357 .dev = {
358 .platform_data = &s3c2410_dma_platdata,
359 },
360};
361#endif
362
f2dda07d
HS		 363#ifdef CONFIG_CPU_S3C2412
364static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
365 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
366 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
367 [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
368 [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
369 [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
370 [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
371 [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
372 [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
373 [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
374 [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
375 [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
376 [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
377 [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
378 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
379 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
380 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
381 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
382 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
383 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
384 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
385};
386
387static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
388 .num_phy_channels = 4,
389 .channels = s3c2412_dma_channels,
390 .num_channels = DMACH_MAX,
391};
392
393struct platform_device s3c2412_device_dma = {
394 .name = "s3c2412-dma",
395 .id = 0,
396 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
397 .resource = s3c2410_dma_resource,
398 .dev = {
399 .platform_data = &s3c2412_dma_platdata,
400 },
401};
402#endif
403
1fecf895
HS		 404#if defined(CONFIG_CPU_S3C2440)
405static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
406 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
407 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
408 [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
409 S3C24XX_DMA_CHANREQ(6, 1) |
410 S3C24XX_DMA_CHANREQ(2, 2) |
411 S3C24XX_DMA_CHANREQ(1, 3),
412 },
413 [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
414 [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
415 [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
416 [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
417 [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
418 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
419 S3C24XX_DMA_CHANREQ(3, 2) |
420 S3C24XX_DMA_CHANREQ(3, 3),
421 },
422 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
423 S3C24XX_DMA_CHANREQ(1, 2),
424 },
425 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
426 S3C24XX_DMA_CHANREQ(0, 2),
427 },
428 [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
429 S3C24XX_DMA_CHANREQ(5, 2),
430 },
431 [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
432 S3C24XX_DMA_CHANREQ(6, 3),
433 },
434 [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
435 S3C24XX_DMA_CHANREQ(5, 3),
436 },
437 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
438 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
439 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
440 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
441};
442
443static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
444 .num_phy_channels = 4,
445 .channels = s3c2440_dma_channels,
446 .num_channels = DMACH_MAX,
447};
448
449struct platform_device s3c2440_device_dma = {
450 .name = "s3c2410-dma",
451 .id = 0,
452 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
453 .resource = s3c2410_dma_resource,
454 .dev = {
455 .platform_data = &s3c2440_dma_platdata,
456 },
457};
458#endif
459
469641ca 460#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
f2dda07d
HS		 461static struct resource s3c2443_dma_resource[] = {
462 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
463 [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
464 [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
465 [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
466 [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
467 [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
468 [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
469};
470
471static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
472 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
473 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
474 [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
475 [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
476 [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
477 [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
478 [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
479 [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
480 [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
481 [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
482 [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
483 [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
484 [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
485 [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
486 [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
487 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
488 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
489 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
490 [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
491 [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
492 [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
493};
494
495static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
496 .num_phy_channels = 6,
497 .channels = s3c2443_dma_channels,
498 .num_channels = DMACH_MAX,
499};
500
501struct platform_device s3c2443_device_dma = {
502 .name = "s3c2443-dma",
503 .id = 0,
504 .num_resources = ARRAY_SIZE(s3c2443_dma_resource),
505 .resource = s3c2443_dma_resource,
506 .dev = {
507 .platform_data = &s3c2443_dma_platdata,
508 },
509};
510#endif
dfc0f509 511
4659c534
HS		 512#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
513void __init s3c2410_init_clocks(int xtal)
514{
515 s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
516 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
517}
518#endif
519
3c27f314
HS		 520#ifdef CONFIG_CPU_S3C2412
521void __init s3c2412_init_clocks(int xtal)
522{
523 s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
524}
525#endif
526
dfc0f509
HS		 527#ifdef CONFIG_CPU_S3C2416
528void __init s3c2416_init_clocks(int xtal)
529{
530 s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
531}
532#endif
533
4659c534
HS		 534#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
535void __init s3c2440_init_clocks(int xtal)
536{
537 s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
538 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
539}
540#endif
541
542#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
543void __init s3c2442_init_clocks(int xtal)
544{
545 s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
546 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
547}
548#endif
549
dfc0f509
HS		 550#ifdef CONFIG_CPU_S3C2443
551void __init s3c2443_init_clocks(int xtal)
552{
553 s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
554}
555#endif
51cb1289
HS		 556
557#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
558 defined(CONFIG_CPU_S3C2442)
559static struct resource s3c2410_dclk_resource[] = {
560 [0] = DEFINE_RES_MEM(0x56000084, 0x4),
561};
562
563struct platform_device s3c2410_device_dclk = {
564 .name = "s3c2410-dclk",
565 .id = 0,
566 .num_resources = ARRAY_SIZE(s3c2410_dclk_resource),
567 .resource = s3c2410_dclk_resource,
568};
569#endif
Linux kernel - Deliverables
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