Commit | Line | Data |
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505788cc | 1 | /* linux/arch/arm/mach-s3c2410/dma.c |
1da177e4 | 2 | * |
a21765a7 | 3 | * Copyright (c) 2006 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
a21765a7 | 6 | * S3C2410 DMA selection |
1da177e4 | 7 | * |
505788cc | 8 | * http://armlinux.simtec.co.uk/ |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
505788cc | 13 | */ |
1da177e4 | 14 | |
a21765a7 | 15 | #include <linux/kernel.h> |
1da177e4 | 16 | #include <linux/init.h> |
4a858cfc | 17 | #include <linux/device.h> |
a21765a7 | 18 | #include <linux/serial_core.h> |
1da177e4 | 19 | |
20934cdb | 20 | #include <mach/map.h> |
a09e64fb | 21 | #include <mach/dma.h> |
a21765a7 | 22 | |
a2b7ba9c | 23 | #include <plat/cpu.h> |
992426bf | 24 | #include <plat/dma-s3c24xx.h> |
a21765a7 | 25 | |
a2b7ba9c | 26 | #include <plat/regs-serial.h> |
a09e64fb | 27 | #include <mach/regs-gpio.h> |
f74c95c2 | 28 | #include <plat/regs-ac97.h> |
44dc9404 | 29 | #include <plat/regs-dma.h> |
a09e64fb RK |
30 | #include <mach/regs-lcd.h> |
31 | #include <mach/regs-sdi.h> | |
8150bc88 | 32 | #include <plat/regs-iis.h> |
13622708 | 33 | #include <plat/regs-spi.h> |
a21765a7 BD |
34 | |
35 | static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { | |
36 | [DMACH_XD0] = { | |
37 | .name = "xdreq0", | |
38 | .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID, | |
39 | }, | |
40 | [DMACH_XD1] = { | |
41 | .name = "xdreq1", | |
42 | .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID, | |
43 | }, | |
44 | [DMACH_SDI] = { | |
45 | .name = "sdi", | |
46 | .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, | |
47 | .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, | |
48 | .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, | |
a21765a7 BD |
49 | }, |
50 | [DMACH_SPI0] = { | |
51 | .name = "spi0", | |
52 | .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, | |
a21765a7 BD |
53 | }, |
54 | [DMACH_SPI1] = { | |
55 | .name = "spi1", | |
56 | .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, | |
a21765a7 BD |
57 | }, |
58 | [DMACH_UART0] = { | |
59 | .name = "uart0", | |
60 | .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, | |
a21765a7 BD |
61 | }, |
62 | [DMACH_UART1] = { | |
63 | .name = "uart1", | |
64 | .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, | |
a21765a7 BD |
65 | }, |
66 | [DMACH_UART2] = { | |
67 | .name = "uart2", | |
68 | .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, | |
a21765a7 BD |
69 | }, |
70 | [DMACH_TIMER] = { | |
71 | .name = "timer", | |
72 | .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID, | |
73 | .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID, | |
74 | .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID, | |
75 | }, | |
76 | [DMACH_I2S_IN] = { | |
77 | .name = "i2s-sdi", | |
78 | .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, | |
79 | .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, | |
a21765a7 BD |
80 | }, |
81 | [DMACH_I2S_OUT] = { | |
82 | .name = "i2s-sdo", | |
83 | .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, | |
a21765a7 BD |
84 | }, |
85 | [DMACH_USB_EP1] = { | |
86 | .name = "usb-ep1", | |
87 | .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID, | |
88 | }, | |
89 | [DMACH_USB_EP2] = { | |
90 | .name = "usb-ep2", | |
91 | .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID, | |
92 | }, | |
93 | [DMACH_USB_EP3] = { | |
94 | .name = "usb-ep3", | |
95 | .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID, | |
96 | }, | |
97 | [DMACH_USB_EP4] = { | |
98 | .name = "usb-ep4", | |
99 | .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID, | |
100 | }, | |
1da177e4 LT |
101 | }; |
102 | ||
a21765a7 BD |
103 | static void s3c2410_dma_select(struct s3c2410_dma_chan *chan, |
104 | struct s3c24xx_dma_map *map) | |
1da177e4 | 105 | { |
a21765a7 | 106 | chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID; |
1da177e4 LT |
107 | } |
108 | ||
a21765a7 BD |
109 | static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = { |
110 | .select = s3c2410_dma_select, | |
111 | .dcon_mask = 7 << 24, | |
112 | .map = s3c2410_dma_mappings, | |
113 | .map_size = ARRAY_SIZE(s3c2410_dma_mappings), | |
114 | }; | |
1da177e4 | 115 | |
dad8d6c5 BD |
116 | static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { |
117 | .channels = { | |
118 | [DMACH_SDI] = { | |
119 | .list = { | |
120 | [0] = 3 | DMA_CH_VALID, | |
121 | [1] = 2 | DMA_CH_VALID, | |
122 | [2] = 0 | DMA_CH_VALID, | |
123 | }, | |
124 | }, | |
125 | [DMACH_I2S_IN] = { | |
126 | .list = { | |
127 | [0] = 1 | DMA_CH_VALID, | |
128 | [1] = 2 | DMA_CH_VALID, | |
129 | }, | |
130 | }, | |
131 | }, | |
132 | }; | |
133 | ||
04511a6f HS |
134 | static int __init s3c2410_dma_add(struct device *dev, |
135 | struct subsys_interface *sif) | |
1da177e4 | 136 | { |
48adbcf3 | 137 | s3c2410_dma_init(); |
dad8d6c5 | 138 | s3c24xx_dma_order_set(&s3c2410_dma_order); |
a21765a7 | 139 | return s3c24xx_dma_init_map(&s3c2410_dma_sel); |
1da177e4 LT |
140 | } |
141 | ||
a21765a7 | 142 | #if defined(CONFIG_CPU_S3C2410) |
4a858cfc KS |
143 | static struct subsys_interface s3c2410_dma_interface = { |
144 | .name = "s3c2410_dma", | |
145 | .subsys = &s3c2410_subsys, | |
146 | .add_dev = s3c2410_dma_add, | |
a21765a7 | 147 | }; |
1da177e4 | 148 | |
48adbcf3 | 149 | static int __init s3c2410_dma_drvinit(void) |
f57e1abd | 150 | { |
04511a6f | 151 | return subsys_interface_register(&s3c2410_dma_interface); |
f57e1abd BD |
152 | } |
153 | ||
48adbcf3 | 154 | arch_initcall(s3c2410_dma_drvinit); |
f0176794 | 155 | |
4a858cfc KS |
156 | static struct subsys_interface s3c2410a_dma_interface = { |
157 | .name = "s3c2410a_dma", | |
158 | .subsys = &s3c2410a_subsys, | |
159 | .add_dev = s3c2410_dma_add, | |
f0176794 BD |
160 | }; |
161 | ||
162 | static int __init s3c2410a_dma_drvinit(void) | |
163 | { | |
4a858cfc | 164 | return subsys_interface_register(&s3c2410a_dma_interface); |
f0176794 BD |
165 | } |
166 | ||
167 | arch_initcall(s3c2410a_dma_drvinit); | |
f57e1abd BD |
168 | #endif |
169 | ||
a21765a7 BD |
170 | #if defined(CONFIG_CPU_S3C2442) |
171 | /* S3C2442 DMA contains the same selection table as the S3C2410 */ | |
4a858cfc KS |
172 | static struct subsys_interface s3c2442_dma_interface = { |
173 | .name = "s3c2442_dma", | |
174 | .subsys = &s3c2442_subsys, | |
175 | .add_dev = s3c2410_dma_add, | |
1da177e4 LT |
176 | }; |
177 | ||
48adbcf3 | 178 | static int __init s3c2442_dma_drvinit(void) |
505788cc | 179 | { |
4a858cfc | 180 | return subsys_interface_register(&s3c2442_dma_interface); |
505788cc BD |
181 | } |
182 | ||
48adbcf3 | 183 | arch_initcall(s3c2442_dma_drvinit); |
a21765a7 | 184 | #endif |
505788cc | 185 |