Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-s3c24xx / dma-s3c2410.c
CommitLineData
505788cc 1/* linux/arch/arm/mach-s3c2410/dma.c
1da177e4 2 *
a21765a7 3 * Copyright (c) 2006 Simtec Electronics
1da177e4
LT
4 * Ben Dooks <ben@simtec.co.uk>
5 *
a21765a7 6 * S3C2410 DMA selection
1da177e4 7 *
505788cc 8 * http://armlinux.simtec.co.uk/
1da177e4
LT
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
505788cc 13*/
1da177e4 14
a21765a7 15#include <linux/kernel.h>
1da177e4 16#include <linux/init.h>
4a858cfc 17#include <linux/device.h>
a21765a7 18#include <linux/serial_core.h>
1da177e4 19
20934cdb 20#include <mach/map.h>
a09e64fb 21#include <mach/dma.h>
a21765a7 22
a2b7ba9c 23#include <plat/cpu.h>
992426bf 24#include <plat/dma-s3c24xx.h>
a21765a7 25
a2b7ba9c 26#include <plat/regs-serial.h>
a09e64fb 27#include <mach/regs-gpio.h>
f74c95c2 28#include <plat/regs-ac97.h>
44dc9404 29#include <plat/regs-dma.h>
a09e64fb 30#include <mach/regs-lcd.h>
8150bc88 31#include <plat/regs-iis.h>
13622708 32#include <plat/regs-spi.h>
a21765a7
BD
33
34static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
35 [DMACH_XD0] = {
36 .name = "xdreq0",
37 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
38 },
39 [DMACH_XD1] = {
40 .name = "xdreq1",
41 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
42 },
43 [DMACH_SDI] = {
44 .name = "sdi",
45 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
46 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
47 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
a21765a7
BD
48 },
49 [DMACH_SPI0] = {
50 .name = "spi0",
51 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
a21765a7
BD
52 },
53 [DMACH_SPI1] = {
54 .name = "spi1",
55 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
a21765a7
BD
56 },
57 [DMACH_UART0] = {
58 .name = "uart0",
59 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
a21765a7
BD
60 },
61 [DMACH_UART1] = {
62 .name = "uart1",
63 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
a21765a7
BD
64 },
65 [DMACH_UART2] = {
66 .name = "uart2",
67 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
a21765a7
BD
68 },
69 [DMACH_TIMER] = {
70 .name = "timer",
71 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
72 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
73 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
74 },
75 [DMACH_I2S_IN] = {
76 .name = "i2s-sdi",
77 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
78 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
a21765a7
BD
79 },
80 [DMACH_I2S_OUT] = {
81 .name = "i2s-sdo",
82 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
a21765a7
BD
83 },
84 [DMACH_USB_EP1] = {
85 .name = "usb-ep1",
86 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
87 },
88 [DMACH_USB_EP2] = {
89 .name = "usb-ep2",
90 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
91 },
92 [DMACH_USB_EP3] = {
93 .name = "usb-ep3",
94 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
95 },
96 [DMACH_USB_EP4] = {
97 .name = "usb-ep4",
98 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
99 },
1da177e4
LT
100};
101
a21765a7
BD
102static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
103 struct s3c24xx_dma_map *map)
1da177e4 104{
a21765a7 105 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
1da177e4
LT
106}
107
a21765a7
BD
108static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
109 .select = s3c2410_dma_select,
110 .dcon_mask = 7 << 24,
111 .map = s3c2410_dma_mappings,
112 .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
113};
1da177e4 114
dad8d6c5
BD
115static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
116 .channels = {
117 [DMACH_SDI] = {
118 .list = {
119 [0] = 3 | DMA_CH_VALID,
120 [1] = 2 | DMA_CH_VALID,
121 [2] = 0 | DMA_CH_VALID,
122 },
123 },
124 [DMACH_I2S_IN] = {
125 .list = {
126 [0] = 1 | DMA_CH_VALID,
127 [1] = 2 | DMA_CH_VALID,
128 },
129 },
130 },
131};
132
04511a6f
HS
133static int __init s3c2410_dma_add(struct device *dev,
134 struct subsys_interface *sif)
1da177e4 135{
48adbcf3 136 s3c2410_dma_init();
dad8d6c5 137 s3c24xx_dma_order_set(&s3c2410_dma_order);
a21765a7 138 return s3c24xx_dma_init_map(&s3c2410_dma_sel);
1da177e4
LT
139}
140
a21765a7 141#if defined(CONFIG_CPU_S3C2410)
4a858cfc
KS
142static struct subsys_interface s3c2410_dma_interface = {
143 .name = "s3c2410_dma",
144 .subsys = &s3c2410_subsys,
145 .add_dev = s3c2410_dma_add,
a21765a7 146};
1da177e4 147
48adbcf3 148static int __init s3c2410_dma_drvinit(void)
f57e1abd 149{
04511a6f 150 return subsys_interface_register(&s3c2410_dma_interface);
f57e1abd
BD
151}
152
48adbcf3 153arch_initcall(s3c2410_dma_drvinit);
f0176794 154
4a858cfc
KS
155static struct subsys_interface s3c2410a_dma_interface = {
156 .name = "s3c2410a_dma",
157 .subsys = &s3c2410a_subsys,
158 .add_dev = s3c2410_dma_add,
f0176794
BD
159};
160
161static int __init s3c2410a_dma_drvinit(void)
162{
4a858cfc 163 return subsys_interface_register(&s3c2410a_dma_interface);
f0176794
BD
164}
165
166arch_initcall(s3c2410a_dma_drvinit);
f57e1abd
BD
167#endif
168
a21765a7
BD
169#if defined(CONFIG_CPU_S3C2442)
170/* S3C2442 DMA contains the same selection table as the S3C2410 */
4a858cfc
KS
171static struct subsys_interface s3c2442_dma_interface = {
172 .name = "s3c2442_dma",
173 .subsys = &s3c2442_subsys,
174 .add_dev = s3c2410_dma_add,
1da177e4
LT
175};
176
48adbcf3 177static int __init s3c2442_dma_drvinit(void)
505788cc 178{
4a858cfc 179 return subsys_interface_register(&s3c2442_dma_interface);
505788cc
BD
180}
181
48adbcf3 182arch_initcall(s3c2442_dma_drvinit);
a21765a7 183#endif
505788cc 184
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