[deliverable/linux.git] / arch / arm / mach-s3c24xx / dma-s3c2440.c

/* linux/arch/arm/mach-s3c2440/dma.c
 *
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2440 DMA selection
 *
 * http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial_core.h>

#include <mach/map.h>
#include <mach/dma.h>

#include <plat/dma-s3c24xx.h>
#include <plat/cpu.h>

#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <plat/regs-iis.h>
#include <plat/regs-spi.h>

static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
	[DMACH_XD0] = {
		.name		= "xdreq0",
		.channels[0]	= S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
	},
	[DMACH_XD1] = {
		.name		= "xdreq1",
		.channels[1]	= S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
	},
	[DMACH_SDI] = {
		.name		= "sdi",
		.channels[0]	= S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
		.channels[1]	= S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
	},
	[DMACH_SPI0] = {
		.name		= "spi0",
		.channels[1]	= S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
	},
	[DMACH_SPI1] = {
		.name		= "spi1",
		.channels[3]	= S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
	},
	[DMACH_UART0] = {
		.name		= "uart0",
		.channels[0]	= S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
	},
	[DMACH_UART1] = {
		.name		= "uart1",
		.channels[1]	= S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
	},
      	[DMACH_UART2] = {
		.name		= "uart2",
		.channels[3]	= S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
	},
	[DMACH_TIMER] = {
		.name		= "timer",
		.channels[0]	= S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
	},
	[DMACH_I2S_IN] = {
		.name		= "i2s-sdi",
		.channels[1]	= S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
	},
	[DMACH_I2S_OUT] = {
		.name		= "i2s-sdo",
		.channels[0]	= S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
	},
	[DMACH_PCM_IN] = {
		.name		= "pcm-in",
		.channels[0]	= S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
		.channels[2]	= S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
	},
	[DMACH_PCM_OUT] = {
		.name		= "pcm-out",
		.channels[1]	= S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
		.channels[3]	= S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
	},
	[DMACH_MIC_IN] = {
		.name		= "mic-in",
		.channels[2]	= S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
		.channels[3]	= S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
	},
	[DMACH_USB_EP1] = {
		.name		= "usb-ep1",
		.channels[0]	= S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
	},
	[DMACH_USB_EP2] = {
		.name		= "usb-ep2",
		.channels[1]	= S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
	},
	[DMACH_USB_EP3] = {
		.name		= "usb-ep3",
		.channels[2]	= S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
	},
	[DMACH_USB_EP4] = {
		.name		= "usb-ep4",
		.channels[3]	= S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
	},
};

static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
			       struct s3c24xx_dma_map *map)
{
	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
}

static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
	.select		= s3c2440_dma_select,
	.dcon_mask	= 7 << 24,
	.map		= s3c2440_dma_mappings,
	.map_size	= ARRAY_SIZE(s3c2440_dma_mappings),
};

static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
	.channels	= {
		[DMACH_SDI]	= {
			.list	= {
				[0]	= 3 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
				[2]	= 1 | DMA_CH_VALID,
				[3]	= 0 | DMA_CH_VALID,
			},
		},
		[DMACH_I2S_IN]	= {
			.list	= {
				[0]	= 1 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
			},
		},
		[DMACH_I2S_OUT]	= {
			.list	= {
				[0]	= 2 | DMA_CH_VALID,
				[1]	= 1 | DMA_CH_VALID,
			},
		},
		[DMACH_PCM_IN] = {
			.list	= {
				[0]	= 2 | DMA_CH_VALID,
				[1]	= 1 | DMA_CH_VALID,
			},
		},
		[DMACH_PCM_OUT] = {
			.list	= {
				[0]	= 1 | DMA_CH_VALID,
				[1]	= 3 | DMA_CH_VALID,
			},
		},
		[DMACH_MIC_IN] = {
			.list	= {
				[0]	= 3 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
			},
		},
	},
};

static int __init s3c2440_dma_add(struct device *dev,
				  struct subsys_interface *sif)
{
	s3c2410_dma_init();
	s3c24xx_dma_order_set(&s3c2440_dma_order);
	return s3c24xx_dma_init_map(&s3c2440_dma_sel);
}

static struct subsys_interface s3c2440_dma_interface = {
	.name		= "s3c2440_dma",
	.subsys		= &s3c2440_subsys,
	.add_dev	= s3c2440_dma_add,
};

static int __init s3c2440_dma_init(void)
{
	return subsys_interface_register(&s3c2440_dma_interface);
}

arch_initcall(s3c2440_dma_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/dma.c
98c418a0	2	*
c16f7bd8	3	* Copyright (c) 2006 Simtec Electronics
98c418a0 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2440 DMA selection
	7	*
	8	* http://armlinux.simtec.co.uk/
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
4a858cfc	17	#include <linux/device.h>
b6d1f542	18	#include <linux/serial_core.h>
98c418a0	19
44dc9404	20	#include <mach/map.h>
a09e64fb	21	#include <mach/dma.h>
98c418a0	22
992426bf	23	#include <plat/dma-s3c24xx.h>
a2b7ba9c	24	#include <plat/cpu.h>
98c418a0	25
a2b7ba9c	26	#include <plat/regs-serial.h>
a09e64fb	27	#include <mach/regs-gpio.h>
f74c95c2	28	#include <plat/regs-ac97.h>
44dc9404	29	#include <plat/regs-dma.h>
a09e64fb RK	30	#include <mach/regs-lcd.h>
a09e64fb RK	31	#include <mach/regs-sdi.h>
8150bc88	32	#include <plat/regs-iis.h>
13622708	33	#include <plat/regs-spi.h>
98c418a0 BD	34
	35	static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
	36	[DMACH_XD0] = {
	37	.name = "xdreq0",
	38	.channels[0] = S3C2410_DCON_CH0_XDREQ0 \| DMA_CH_VALID,
	39	},
	40	[DMACH_XD1] = {
	41	.name = "xdreq1",
	42	.channels[1] = S3C2410_DCON_CH1_XDREQ1 \| DMA_CH_VALID,
	43	},
	44	[DMACH_SDI] = {
	45	.name = "sdi",
	46	.channels[0] = S3C2410_DCON_CH0_SDI \| DMA_CH_VALID,
	47	.channels[1] = S3C2440_DCON_CH1_SDI \| DMA_CH_VALID,
	48	.channels[2] = S3C2410_DCON_CH2_SDI \| DMA_CH_VALID,
	49	.channels[3] = S3C2410_DCON_CH3_SDI \| DMA_CH_VALID,
98c418a0 BD	50	},
	51	[DMACH_SPI0] = {
	52	.name = "spi0",
	53	.channels[1] = S3C2410_DCON_CH1_SPI \| DMA_CH_VALID,
98c418a0 BD	54	},
	55	[DMACH_SPI1] = {
	56	.name = "spi1",
	57	.channels[3] = S3C2410_DCON_CH3_SPI \| DMA_CH_VALID,
98c418a0 BD	58	},
	59	[DMACH_UART0] = {
	60	.name = "uart0",
	61	.channels[0] = S3C2410_DCON_CH0_UART0 \| DMA_CH_VALID,
98c418a0 BD	62	},
	63	[DMACH_UART1] = {
	64	.name = "uart1",
	65	.channels[1] = S3C2410_DCON_CH1_UART1 \| DMA_CH_VALID,
98c418a0 BD	66	},
	67	[DMACH_UART2] = {
	68	.name = "uart2",
	69	.channels[3] = S3C2410_DCON_CH3_UART2 \| DMA_CH_VALID,
98c418a0 BD	70	},
	71	[DMACH_TIMER] = {
	72	.name = "timer",
	73	.channels[0] = S3C2410_DCON_CH0_TIMER \| DMA_CH_VALID,
	74	.channels[2] = S3C2410_DCON_CH2_TIMER \| DMA_CH_VALID,
	75	.channels[3] = S3C2410_DCON_CH3_TIMER \| DMA_CH_VALID,
	76	},
	77	[DMACH_I2S_IN] = {
	78	.name = "i2s-sdi",
	79	.channels[1] = S3C2410_DCON_CH1_I2SSDI \| DMA_CH_VALID,
	80	.channels[2] = S3C2410_DCON_CH2_I2SSDI \| DMA_CH_VALID,
98c418a0 BD	81	},
	82	[DMACH_I2S_OUT] = {
	83	.name = "i2s-sdo",
	84	.channels[0] = S3C2440_DCON_CH0_I2SSDO \| DMA_CH_VALID,
	85	.channels[2] = S3C2410_DCON_CH2_I2SSDO \| DMA_CH_VALID,
98c418a0 BD	86	},
	87	[DMACH_PCM_IN] = {
	88	.name = "pcm-in",
	89	.channels[0] = S3C2440_DCON_CH0_PCMIN \| DMA_CH_VALID,
	90	.channels[2] = S3C2440_DCON_CH2_PCMIN \| DMA_CH_VALID,
98c418a0 BD	91	},
	92	[DMACH_PCM_OUT] = {
	93	.name = "pcm-out",
	94	.channels[1] = S3C2440_DCON_CH1_PCMOUT \| DMA_CH_VALID,
	95	.channels[3] = S3C2440_DCON_CH3_PCMOUT \| DMA_CH_VALID,
98c418a0 BD	96	},
	97	[DMACH_MIC_IN] = {
	98	.name = "mic-in",
	99	.channels[2] = S3C2440_DCON_CH2_MICIN \| DMA_CH_VALID,
	100	.channels[3] = S3C2440_DCON_CH3_MICIN \| DMA_CH_VALID,
98c418a0 BD	101	},
	102	[DMACH_USB_EP1] = {
	103	.name = "usb-ep1",
	104	.channels[0] = S3C2410_DCON_CH0_USBEP1 \| DMA_CH_VALID,
	105	},
	106	[DMACH_USB_EP2] = {
	107	.name = "usb-ep2",
	108	.channels[1] = S3C2410_DCON_CH1_USBEP2 \| DMA_CH_VALID,
	109	},
	110	[DMACH_USB_EP3] = {
	111	.name = "usb-ep3",
	112	.channels[2] = S3C2410_DCON_CH2_USBEP3 \| DMA_CH_VALID,
	113	},
	114	[DMACH_USB_EP4] = {
	115	.name = "usb-ep4",
	116	.channels[3] = S3C2410_DCON_CH3_USBEP4 \| DMA_CH_VALID,
	117	},
	118	};
	119
	120	static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
	121	struct s3c24xx_dma_map *map)
	122	{
	123	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
	124	}
	125
	126	static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
	127	.select = s3c2440_dma_select,
	128	.dcon_mask = 7 << 24,
	129	.map = s3c2440_dma_mappings,
	130	.map_size = ARRAY_SIZE(s3c2440_dma_mappings),
	131	};
	132
bd65c82b BD	133	static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
	134	.channels = {
	135	[DMACH_SDI] = {
	136	.list = {
	137	[0] = 3 \| DMA_CH_VALID,
	138	[1] = 2 \| DMA_CH_VALID,
	139	[2] = 1 \| DMA_CH_VALID,
	140	[3] = 0 \| DMA_CH_VALID,
	141	},
	142	},
	143	[DMACH_I2S_IN] = {
	144	.list = {
	145	[0] = 1 \| DMA_CH_VALID,
	146	[1] = 2 \| DMA_CH_VALID,
	147	},
	148	},
	149	[DMACH_I2S_OUT] = {
	150	.list = {
	151	[0] = 2 \| DMA_CH_VALID,
	152	[1] = 1 \| DMA_CH_VALID,
	153	},
	154	},
	155	[DMACH_PCM_IN] = {
	156	.list = {
	157	[0] = 2 \| DMA_CH_VALID,
	158	[1] = 1 \| DMA_CH_VALID,
	159	},
	160	},
	161	[DMACH_PCM_OUT] = {
	162	.list = {
	163	[0] = 1 \| DMA_CH_VALID,
	164	[1] = 3 \| DMA_CH_VALID,
	165	},
	166	},
	167	[DMACH_MIC_IN] = {
	168	.list = {
	169	[0] = 3 \| DMA_CH_VALID,
	170	[1] = 2 \| DMA_CH_VALID,
	171	},
	172	},
	173	},
	174	};
	175
04511a6f HS	176	static int __init s3c2440_dma_add(struct device *dev,
04511a6f HS	177	struct subsys_interface *sif)
98c418a0	178	{
48adbcf3	179	s3c2410_dma_init();
bd65c82b	180	s3c24xx_dma_order_set(&s3c2440_dma_order);
98c418a0 BD	181	return s3c24xx_dma_init_map(&s3c2440_dma_sel);
	182	}
	183
4a858cfc KS	184	static struct subsys_interface s3c2440_dma_interface = {
	185	.name = "s3c2440_dma",
	186	.subsys = &s3c2440_subsys,
	187	.add_dev = s3c2440_dma_add,
98c418a0 BD	188	};
	189
	190	static int __init s3c2440_dma_init(void)
	191	{
4a858cfc	192	return subsys_interface_register(&s3c2440_dma_interface);
98c418a0 BD	193	}
	194
	195	arch_initcall(s3c2440_dma_init);
	196