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65fa22b7 BD |
1 | /* linux/arch/arm/plat-s3c24xx/irq-om.c |
2 | * | |
e02f8664 | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
65fa22b7 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * http://armlinux.simtec.co.uk/ | |
6 | * | |
7 | * S3C24XX - IRQ PM code | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/interrupt.h> | |
57436c2d | 17 | #include <linux/irq.h> |
d8fdec16 | 18 | #include <linux/syscore_ops.h> |
65fa22b7 BD |
19 | |
20 | #include <plat/cpu.h> | |
21 | #include <plat/pm.h> | |
22 | #include <plat/irq.h> | |
23 | ||
57436c2d LB |
24 | #include <asm/irq.h> |
25 | ||
65fa22b7 BD |
26 | /* state for IRQs over sleep */ |
27 | ||
28 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | |
29 | * | |
30 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | |
31 | */ | |
32 | ||
b4a343e5 | 33 | unsigned long s3c_irqwake_intallow = 1L << 30 | 0xfL; |
65fa22b7 | 34 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; |
65fa22b7 | 35 | |
57436c2d | 36 | int s3c_irq_wake(struct irq_data *data, unsigned int state) |
65fa22b7 | 37 | { |
b4a343e5 | 38 | unsigned long irqbit = 1 << data->hwirq; |
65fa22b7 BD |
39 | |
40 | if (!(s3c_irqwake_intallow & irqbit)) | |
41 | return -ENOENT; | |
42 | ||
b4a343e5 HS |
43 | pr_info("wake %s for hwirq %lu\n", |
44 | state ? "enabled" : "disabled", data->hwirq); | |
65fa22b7 BD |
45 | |
46 | if (!state) | |
47 | s3c_irqwake_intmask |= irqbit; | |
48 | else | |
49 | s3c_irqwake_intmask &= ~irqbit; | |
50 | ||
51 | return 0; | |
52 | } | |
53 | ||
65fa22b7 BD |
54 | static struct sleep_save irq_save[] = { |
55 | SAVE_ITEM(S3C2410_INTMSK), | |
56 | SAVE_ITEM(S3C2410_INTSUBMSK), | |
57 | }; | |
58 | ||
59 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | |
60 | * so we use an array to hold them, and to calculate the address of | |
61 | * the register at run-time | |
62 | */ | |
63 | ||
64 | static unsigned long save_extint[3]; | |
65 | static unsigned long save_eintflt[4]; | |
66 | static unsigned long save_eintmask; | |
67 | ||
d8fdec16 | 68 | static int s3c24xx_irq_suspend(void) |
65fa22b7 BD |
69 | { |
70 | unsigned int i; | |
71 | ||
72 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | |
73 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | |
74 | ||
75 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | |
76 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | |
77 | ||
78 | s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | |
79 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
d8fdec16 | 84 | static void s3c24xx_irq_resume(void) |
65fa22b7 BD |
85 | { |
86 | unsigned int i; | |
87 | ||
88 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | |
89 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | |
90 | ||
91 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | |
92 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | |
93 | ||
94 | s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | |
95 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | |
65fa22b7 | 96 | } |
d8fdec16 HS |
97 | |
98 | struct syscore_ops s3c24xx_irq_syscore_ops = { | |
99 | .suspend = s3c24xx_irq_suspend, | |
100 | .resume = s3c24xx_irq_resume, | |
101 | }; | |
ef602eb5 HS |
102 | |
103 | #ifdef CONFIG_CPU_S3C2416 | |
104 | static struct sleep_save s3c2416_irq_save[] = { | |
105 | SAVE_ITEM(S3C2416_INTMSK2), | |
106 | }; | |
107 | ||
108 | static int s3c2416_irq_suspend(void) | |
109 | { | |
110 | s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save)); | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | static void s3c2416_irq_resume(void) | |
116 | { | |
117 | s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save)); | |
118 | } | |
119 | ||
120 | struct syscore_ops s3c2416_irq_syscore_ops = { | |
121 | .suspend = s3c2416_irq_suspend, | |
122 | .resume = s3c2416_irq_resume, | |
123 | }; | |
124 | #endif |