[deliverable/linux.git] / arch / arm / mach-s3c24xx / irq-s3c2412.c

/* linux/arch/arm/mach-s3c2412/irq.c
 *
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#include <asm/mach/irq.h>

#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>

#include <plat/cpu.h>
#include <plat/irq.h>
#include <plat/pm.h>

#include "s3c2412-power.h"

#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))

/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
 * having them turn up in both the INT* and the EINT* registers. Whilst
 * both show the status, they both now need to be acked when the IRQs
 * go off.
*/

static void
s3c2412_irq_mask(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
	unsigned long mask;

	mask = __raw_readl(S3C2410_INTMSK);
	__raw_writel(mask | bitval, S3C2410_INTMSK);

	mask = __raw_readl(S3C2412_EINTMASK);
	__raw_writel(mask | bitval, S3C2412_EINTMASK);
}

static inline void
s3c2412_irq_ack(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);

	__raw_writel(bitval, S3C2412_EINTPEND);
	__raw_writel(bitval, S3C2410_SRCPND);
	__raw_writel(bitval, S3C2410_INTPND);
}

static inline void
s3c2412_irq_maskack(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
	unsigned long mask;

	mask = __raw_readl(S3C2410_INTMSK);
	__raw_writel(mask|bitval, S3C2410_INTMSK);

	mask = __raw_readl(S3C2412_EINTMASK);
	__raw_writel(mask | bitval, S3C2412_EINTMASK);

	__raw_writel(bitval, S3C2412_EINTPEND);
	__raw_writel(bitval, S3C2410_SRCPND);
	__raw_writel(bitval, S3C2410_INTPND);
}

static void
s3c2412_irq_unmask(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
	unsigned long mask;

	mask = __raw_readl(S3C2412_EINTMASK);
	__raw_writel(mask & ~bitval, S3C2412_EINTMASK);

	mask = __raw_readl(S3C2410_INTMSK);
	__raw_writel(mask & ~bitval, S3C2410_INTMSK);
}

static struct irq_chip s3c2412_irq_eint0t4 = {
	.irq_ack	= s3c2412_irq_ack,
	.irq_mask	= s3c2412_irq_mask,
	.irq_unmask	= s3c2412_irq_unmask,
	.irq_set_wake	= s3c_irq_wake,
	.irq_set_type	= s3c_irqext_type,
};

#define INTBIT(x)	(1 << ((x) - S3C2410_IRQSUB(0)))

/* CF and SDI sub interrupts */

static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
{
	unsigned int subsrc, submsk;

	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	submsk = __raw_readl(S3C2410_INTSUBMSK);

	subsrc  &= ~submsk;

	if (subsrc & INTBIT(IRQ_S3C2412_SDI))
		generic_handle_irq(IRQ_S3C2412_SDI);

	if (subsrc & INTBIT(IRQ_S3C2412_CF))
		generic_handle_irq(IRQ_S3C2412_CF);
}

#define INTMSK_CFSDI	(1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
#define SUBMSK_CFSDI	INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)

static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
{
	s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
}

static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
{
	s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
}

static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
{
	s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
}

static struct irq_chip s3c2412_irq_cfsdi = {
	.name		= "s3c2412-cfsdi",
	.irq_ack	= s3c2412_irq_cfsdi_ack,
	.irq_mask	= s3c2412_irq_cfsdi_mask,
	.irq_unmask	= s3c2412_irq_cfsdi_unmask,
};

static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
{
	unsigned long pwrcfg;

	pwrcfg = __raw_readl(S3C2412_PWRCFG);
	if (state)
		pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
	else
		pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
	__raw_writel(pwrcfg, S3C2412_PWRCFG);

	return s3c_irq_chip.irq_set_wake(data, state);
}

static struct irq_chip s3c2412_irq_rtc_chip;

static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
{
	unsigned int irqno;

	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
		irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
					 handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	/* add demux support for CF/SDI */

	irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);

	for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
		irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
					 handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	/* change RTC IRQ's set wake method */

	s3c2412_irq_rtc_chip = s3c_irq_chip;
	s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;

	irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);

	return 0;
}

static struct subsys_interface s3c2412_irq_interface = {
	.name		= "s3c2412_irq",
	.subsys		= &s3c2412_subsys,
	.add_dev	= s3c2412_irq_add,
};

static int s3c2412_irq_init(void)
{
	return subsys_interface_register(&s3c2412_irq_interface);
}

arch_initcall(s3c2412_irq_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2412/irq.c
c6e58ebb BD	2	*
	3	* Copyright (c) 2006 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*
	20	*/
	21
	22	#include <linux/init.h>
	23	#include <linux/module.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/ioport.h>
4a858cfc	26	#include <linux/device.h>
fced80c7	27	#include <linux/io.h>
c6e58ebb	28
a09e64fb	29	#include <mach/hardware.h>
c6e58ebb	30	#include <asm/irq.h>
c6e58ebb BD	31
	32	#include <asm/mach/irq.h>
	33
a09e64fb RK	34	#include <mach/regs-irq.h>
a09e64fb RK	35	#include <mach/regs-gpio.h>
c6e58ebb	36
a2b7ba9c BD	37	#include <plat/cpu.h>
	38	#include <plat/irq.h>
	39	#include <plat/pm.h>
c6e58ebb	40
14cce0e7 KK	41	#include "s3c2412-power.h"
14cce0e7 KK	42
f3fb5a55 BD	43	#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
	44	#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
	45
c6e58ebb BD	46	/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
	47	* having them turn up in both the INT* and the EINT* registers. Whilst
	48	* both show the status, they both now need to be acked when the IRQs
	49	* go off.
	50	*/
	51
	52	static void
57436c2d	53	s3c2412_irq_mask(struct irq_data *data)
c6e58ebb	54	{
57436c2d	55	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
c6e58ebb BD	56	unsigned long mask;
	57
	58	mask = __raw_readl(S3C2410_INTMSK);
	59	__raw_writel(mask \| bitval, S3C2410_INTMSK);
	60
	61	mask = __raw_readl(S3C2412_EINTMASK);
	62	__raw_writel(mask \| bitval, S3C2412_EINTMASK);
	63	}
	64
	65	static inline void
57436c2d	66	s3c2412_irq_ack(struct irq_data *data)
c6e58ebb	67	{
57436c2d	68	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
c6e58ebb BD	69
	70	__raw_writel(bitval, S3C2412_EINTPEND);
	71	__raw_writel(bitval, S3C2410_SRCPND);
	72	__raw_writel(bitval, S3C2410_INTPND);
	73	}
	74
	75	static inline void
57436c2d	76	s3c2412_irq_maskack(struct irq_data *data)
c6e58ebb	77	{
57436c2d	78	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
c6e58ebb BD	79	unsigned long mask;
	80
	81	mask = __raw_readl(S3C2410_INTMSK);
	82	__raw_writel(mask\|bitval, S3C2410_INTMSK);
	83
	84	mask = __raw_readl(S3C2412_EINTMASK);
	85	__raw_writel(mask \| bitval, S3C2412_EINTMASK);
	86
	87	__raw_writel(bitval, S3C2412_EINTPEND);
	88	__raw_writel(bitval, S3C2410_SRCPND);
	89	__raw_writel(bitval, S3C2410_INTPND);
	90	}
	91
	92	static void
57436c2d	93	s3c2412_irq_unmask(struct irq_data *data)
c6e58ebb	94	{
57436c2d	95	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
c6e58ebb BD	96	unsigned long mask;
	97
	98	mask = __raw_readl(S3C2412_EINTMASK);
	99	__raw_writel(mask & ~bitval, S3C2412_EINTMASK);
	100
	101	mask = __raw_readl(S3C2410_INTMSK);
	102	__raw_writel(mask & ~bitval, S3C2410_INTMSK);
	103	}
	104
10dd5ce2	105	static struct irq_chip s3c2412_irq_eint0t4 = {
57436c2d LB	106	.irq_ack = s3c2412_irq_ack,
	107	.irq_mask = s3c2412_irq_mask,
	108	.irq_unmask = s3c2412_irq_unmask,
	109	.irq_set_wake = s3c_irq_wake,
	110	.irq_set_type = s3c_irqext_type,
c6e58ebb BD	111	};
c6e58ebb BD	112
f3fb5a55 BD	113	#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
	114
	115	/* CF and SDI sub interrupts */
	116
	117	static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
	118	{
	119	unsigned int subsrc, submsk;
	120
	121	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	122	submsk = __raw_readl(S3C2410_INTSUBMSK);
	123
	124	subsrc &= ~submsk;
	125
	126	if (subsrc & INTBIT(IRQ_S3C2412_SDI))
d8aa0251	127	generic_handle_irq(IRQ_S3C2412_SDI);
f3fb5a55 BD	128
f3fb5a55 BD	129	if (subsrc & INTBIT(IRQ_S3C2412_CF))
d8aa0251	130	generic_handle_irq(IRQ_S3C2412_CF);
f3fb5a55 BD	131	}
	132
	133	#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
	134	#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
	135
57436c2d	136	static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
f3fb5a55	137	{
57436c2d	138	s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
f3fb5a55 BD	139	}
f3fb5a55 BD	140
57436c2d	141	static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
f3fb5a55	142	{
57436c2d	143	s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
f3fb5a55 BD	144	}
f3fb5a55 BD	145
57436c2d	146	static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
f3fb5a55	147	{
57436c2d	148	s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
f3fb5a55 BD	149	}
	150
	151	static struct irq_chip s3c2412_irq_cfsdi = {
	152	.name = "s3c2412-cfsdi",
57436c2d LB	153	.irq_ack = s3c2412_irq_cfsdi_ack,
	154	.irq_mask = s3c2412_irq_cfsdi_mask,
	155	.irq_unmask = s3c2412_irq_cfsdi_unmask,
f3fb5a55 BD	156	};
f3fb5a55 BD	157
57436c2d	158	static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
0baada27 BD	159	{
	160	unsigned long pwrcfg;
	161
	162	pwrcfg = __raw_readl(S3C2412_PWRCFG);
	163	if (state)
	164	pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
	165	else
	166	pwrcfg \|= S3C2412_PWRCFG_RTC_MASKIRQ;
	167	__raw_writel(pwrcfg, S3C2412_PWRCFG);
	168
57436c2d	169	return s3c_irq_chip.irq_set_wake(data, state);
0baada27 BD	170	}
	171
	172	static struct irq_chip s3c2412_irq_rtc_chip;
	173
04511a6f	174	static int s3c2412_irq_add(struct device dev, struct subsys_interface sif)
c6e58ebb BD	175	{
	176	unsigned int irqno;
	177
	178	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
f38c02f3 TG	179	irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
f38c02f3 TG	180	handle_edge_irq);
c6e58ebb BD	181	set_irq_flags(irqno, IRQF_VALID);
	182	}
	183
f3fb5a55 BD	184	/* add demux support for CF/SDI */
f3fb5a55 BD	185
6845664a	186	irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
f3fb5a55 BD	187
f3fb5a55 BD	188	for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
f38c02f3 TG	189	irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
f38c02f3 TG	190	handle_level_irq);
f3fb5a55 BD	191	set_irq_flags(irqno, IRQF_VALID);
	192	}
	193
0baada27 BD	194	/* change RTC IRQ's set wake method */
	195
	196	s3c2412_irq_rtc_chip = s3c_irq_chip;
57436c2d	197	s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
0baada27	198
6845664a	199	irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
0baada27	200
c6e58ebb BD	201	return 0;
	202	}
	203
4a858cfc KS	204	static struct subsys_interface s3c2412_irq_interface = {
	205	.name = "s3c2412_irq",
	206	.subsys = &s3c2412_subsys,
	207	.add_dev = s3c2412_irq_add,
c6e58ebb BD	208	};
	209
	210	static int s3c2412_irq_init(void)
	211	{
4a858cfc	212	return subsys_interface_register(&s3c2412_irq_interface);
c6e58ebb BD	213	}
	214
	215	arch_initcall(s3c2412_irq_init);