[deliverable/linux.git] / arch / arm / mach-s3c24xx / mach-anubis.c

/* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
 * Copyright 2003-2009 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <net/ax88796.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>

#include "anubis.h"
#include "common.h"
#include "simtec.h"

#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"

static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */

  {
	.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	.pfn		= __phys_to_pfn(0x0),
	.length		= SZ_4M,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)S3C24XX_VA_ISA_WORD,
	.pfn		= __phys_to_pfn(0x0),
	.length 	= SZ_4M,
	.type		= MT_DEVICE,
  },

  /* we could possibly compress the next set down into a set of smaller tables
   * pagetables, but that would mean using an L2 section, and it still means
   * we cannot actually feed the same register to an LDR due to 16K spacing
   */

  /* CPLD control registers */

  {
	.virtual	= (u32)ANUBIS_VA_CTRL1,
	.pfn		= __phys_to_pfn(ANUBIS_PA_CTRL1),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)ANUBIS_VA_IDREG,
	.pfn		= __phys_to_pfn(ANUBIS_PA_IDREG),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[1] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
};

/* NAND Flash on Anubis board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition __initdata anubis_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Anubis has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
};

static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	tmp |= slot;

	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);

	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}

static struct s3c2410_platform_nand __initdata anubis_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),
	.sets		= anubis_nand_sets,
	.select_chip	= anubis_nand_select,
};

/* IDE channels */

static struct pata_platform_info anubis_ide_platdata = {
	.ioport_shift	= 5,
};

static struct resource anubis_ide0_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
	[2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
	[3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
};

static struct platform_device anubis_device_ide0 = {
	.name		= "pata_platform",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_ide0_resource),
	.resource	= anubis_ide0_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

static struct resource anubis_ide1_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
	[1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
	[2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
};

static struct platform_device anubis_device_ide1 = {
	.name		= "pata_platform",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(anubis_ide1_resource),
	.resource	= anubis_ide1_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data anubis_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource anubis_asix_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
	[1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
};

static struct platform_device anubis_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_asix_resource),
	.resource	= anubis_asix_resource,
	.dev		= {
		.platform_data = &anubis_asix_platdata,
	}
};

/* SM501 */

static struct resource anubis_sm501_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
	[1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
	[2] = DEFINE_RES_IRQ(IRQ_EINT0),
};

static struct sm501_initdata anubis_sm501_initdata = {
	.gpio_high	= {
		.set	= 0x3F000000,		/* 24bit panel */
		.mask	= 0x0,
	},
	.misc_timing	= {
		.set	= 0x010100,		/* SDRAM timing */
		.mask	= 0x1F1F00,
	},
	.misc_control	= {
		.set	= SM501_MISC_PNL_24BIT,
		.mask	= 0,
	},

	.devices	= SM501_USE_GPIO,

	/* set the SDRAM and bus clocks */
	.mclk		= 72 * MHZ,
	.m1xclk		= 144 * MHZ,
};

static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	[0] = {
		.bus_num	= 1,
		.pin_scl	= 44,
		.pin_sda	= 45,
	},
	[1] = {
		.bus_num	= 2,
		.pin_scl	= 40,
		.pin_sda	= 41,
	},
};

static struct sm501_platdata anubis_sm501_platdata = {
	.init		= &anubis_sm501_initdata,
	.gpio_base	= -1,
	.gpio_i2c	= anubis_sm501_gpio_i2c,
	.gpio_i2c_nr	= ARRAY_SIZE(anubis_sm501_gpio_i2c),
};

static struct platform_device anubis_device_sm501 = {
	.name		= "sm501",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_sm501_resource),
	.resource	= anubis_sm501_resource,
	.dev		= {
		.platform_data = &anubis_sm501_platdata,
	},
};

/* Standard Anubis devices */

static struct platform_device *anubis_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&anubis_device_ide0,
	&anubis_device_ide1,
	&anubis_device_asix,
	&anubis_device_sm501,
};

static struct clk *anubis_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

/* I2C devices. */

static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
	}
};

/* Audio setup */
static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	.have_mic	= 1,
	.have_lout	= 1,
	.output_cdclk	= 1,
	.use_mpllin	= 1,
	.amp_gpio	= S3C2410_GPB(2),
	.amp_gain[0]	= S3C2410_GPD(10),
	.amp_gain[1]	= S3C2410_GPD(11),
};

static void __init anubis_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));

	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
		printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
		       __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
		anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
		anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	} else {
		/* ensure that the GPIO is setup */
		gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
		gpio_free(S3C2410_GPA(0));
	}
}

static void __init anubis_init(void)
{
	s3c_i2c0_set_platdata(NULL);
	s3c_nand_set_platdata(&anubis_nand_info);
	simtec_audio_add(NULL, false, &anubis_audio);

	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));

	i2c_register_board_info(0, anubis_i2c_devs,
				ARRAY_SIZE(anubis_i2c_devs));
}


MACHINE_START(ANUBIS, "Simtec-Anubis")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.atag_offset	= 0x100,
	.map_io		= anubis_map_io,
	.init_machine	= anubis_init,
	.init_irq	= s3c24xx_init_irq,
	.init_time	= s3c24xx_timer_init,
	.restart	= s3c244x_restart,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-anubis.c
7efb833d	2	*
50f430e3	3	* Copyright 2003-2009 Simtec Electronics
7efb833d BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
7efb833d BD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
7efb833d BD	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
b6d1f542	19	#include <linux/serial_core.h>
d052d1be	20	#include <linux/platform_device.h>
b9db83af	21	#include <linux/ata_platform.h>
7a28db61	22	#include <linux/i2c.h>
fced80c7	23	#include <linux/io.h>
8a9ccb7f BD	24	#include <linux/sm501.h>
	25	#include <linux/sm501-regs.h>
	26
7efb833d BD	27	#include <asm/mach/arch.h>
	28	#include <asm/mach/map.h>
	29	#include <asm/mach/irq.h>
	30
a09e64fb	31	#include <mach/hardware.h>
7efb833d BD	32	#include <asm/irq.h>
	33	#include <asm/mach-types.h>
	34
a2b7ba9c	35	#include <plat/regs-serial.h>
a09e64fb	36	#include <mach/regs-gpio.h>
a09e64fb	37	#include <mach/regs-lcd.h>
436d42c6 AB	38	#include <linux/platform_data/mtd-nand-s3c2410.h>
436d42c6 AB	39	#include <linux/platform_data/i2c-s3c2410.h>
7efb833d BD	40
	41	#include <linux/mtd/mtd.h>
	42	#include <linux/mtd/nand.h>
	43	#include <linux/mtd/nand_ecc.h>
	44	#include <linux/mtd/partitions.h>
	45
eac1d8da BD	46	#include <net/ax88796.h>
eac1d8da BD	47
d5120ae7	48	#include <plat/clock.h>
a2b7ba9c BD	49	#include <plat/devs.h>
a2b7ba9c BD	50	#include <plat/cpu.h>
436d42c6	51	#include <linux/platform_data/asoc-s3c24xx_simtec.h>
7efb833d	52
fc351246	53	#include "anubis.h"
b27b0727	54	#include "common.h"
fc351246	55	#include "simtec.h"
b27b0727	56
50f430e3	57	#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
7efb833d BD	58
	59	static struct map_desc anubis_iodesc[] __initdata = {
	60	/* ISA IO areas */
	61
8dd52311 BD	62	{
	63	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	64	.pfn = __phys_to_pfn(0x0),
	65	.length = SZ_4M,
705630db	66	.type = MT_DEVICE,
8dd52311 BD	67	}, {
	68	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	69	.pfn = __phys_to_pfn(0x0),
705630db BD	70	.length = SZ_4M,
705630db BD	71	.type = MT_DEVICE,
8dd52311	72	},
7efb833d BD	73
	74	/* we could possibly compress the next set down into a set of smaller tables
	75	* pagetables, but that would mean using an L2 section, and it still means
	76	* we cannot actually feed the same register to an LDR due to 16K spacing
	77	*/
	78
	79	/* CPLD control registers */
	80
8dd52311 BD	81	{
	82	.virtual = (u32)ANUBIS_VA_CTRL1,
	83	.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
	84	.length = SZ_4K,
705630db	85	.type = MT_DEVICE,
8dd52311	86	}, {
6c1640d5 BD	87	.virtual = (u32)ANUBIS_VA_IDREG,
6c1640d5 BD	88	.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
8dd52311	89	.length = SZ_4K,
705630db	90	.type = MT_DEVICE,
8dd52311	91	},
7efb833d BD	92	};
	93
	94	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	95	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	96	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	97
66a9b49a	98	static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
7efb833d BD	99	[0] = {
	100	.hwport = 0,
	101	.flags = 0,
	102	.ucon = UCON,
	103	.ulcon = ULCON,
	104	.ufcon = UFCON,
afba7f91	105	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
7efb833d BD	106	},
	107	[1] = {
	108	.hwport = 2,
	109	.flags = 0,
	110	.ucon = UCON,
	111	.ulcon = ULCON,
	112	.ufcon = UFCON,
afba7f91	113	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
7efb833d BD	114	},
	115	};
	116
	117	/* NAND Flash on Anubis board */
	118
	119	static int external_map[] = { 2 };
	120	static int chip0_map[] = { 0 };
	121	static int chip1_map[] = { 1 };
	122
2a3a1804	123	static struct mtd_partition __initdata anubis_default_nand_part[] = {
7efb833d BD	124	[0] = {
	125	.name = "Boot Agent",
	126	.size = SZ_16K,
705630db	127	.offset = 0,
7efb833d BD	128	},
	129	[1] = {
	130	.name = "/boot",
	131	.size = SZ_4M - SZ_16K,
	132	.offset = SZ_16K,
	133	},
	134	[2] = {
	135	.name = "user1",
	136	.offset = SZ_4M,
	137	.size = SZ_32M - SZ_4M,
	138	},
	139	[3] = {
	140	.name = "user2",
	141	.offset = SZ_32M,
	142	.size = MTDPART_SIZ_FULL,
	143	}
	144	};
	145
2a3a1804	146	static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
ad3613f4 BD	147	[0] = {
	148	.name = "Boot Agent",
	149	.size = SZ_128K,
	150	.offset = 0,
	151	},
	152	[1] = {
	153	.name = "/boot",
	154	.size = SZ_4M - SZ_128K,
	155	.offset = SZ_128K,
	156	},
	157	[2] = {
	158	.name = "user1",
	159	.offset = SZ_4M,
	160	.size = SZ_32M - SZ_4M,
	161	},
	162	[3] = {
	163	.name = "user2",
	164	.offset = SZ_32M,
	165	.size = MTDPART_SIZ_FULL,
	166	}
	167	};
	168
7efb833d BD	169	/* the Anubis has 3 selectable slots for nand-flash, the two
	170	* on-board chip areas, as well as the external slot.
	171	*
	172	* Note, there is no current hot-plug support for the External
	173	* socket.
	174	*/
	175
2a3a1804	176	static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
7efb833d BD	177	[1] = {
	178	.name = "External",
	179	.nr_chips = 1,
	180	.nr_map = external_map,
	181	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	182	.partitions = anubis_default_nand_part,
7efb833d BD	183	},
	184	[0] = {
	185	.name = "chip0",
	186	.nr_chips = 1,
	187	.nr_map = chip0_map,
	188	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	189	.partitions = anubis_default_nand_part,
7efb833d BD	190	},
	191	[2] = {
	192	.name = "chip1",
	193	.nr_chips = 1,
	194	.nr_map = chip1_map,
	195	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	196	.partitions = anubis_default_nand_part,
7efb833d BD	197	},
	198	};
	199
	200	static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
	201	{
	202	unsigned int tmp;
	203
	204	slot = set->nr_map[slot] & 3;
	205
	206	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
	207	slot, set, set->nr_map);
	208
	209	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	210	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	211	tmp \|= slot;
	212
	213	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
	214
	215	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
	216	}
	217
2a3a1804	218	static struct s3c2410_platform_nand __initdata anubis_nand_info = {
7efb833d	219	.tacls = 25,
661e6acf BD	220	.twrph0 = 55,
661e6acf BD	221	.twrph1 = 40,
7efb833d BD	222	.nr_sets = ARRAY_SIZE(anubis_nand_sets),
	223	.sets = anubis_nand_sets,
	224	.select_chip = anubis_nand_select,
	225	};
	226
bf1c56a3 BD	227	/* IDE channels */
bf1c56a3 BD	228
019dbaa1	229	static struct pata_platform_info anubis_ide_platdata = {
b9db83af BD	230	.ioport_shift = 5,
	231	};
	232
bf1c56a3	233	static struct resource anubis_ide0_resource[] = {
d1c14938 TB	234	[0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
d1c14938 TB	235	[2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
fc351246	236	[3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
bf1c56a3 BD	237	};
	238
	239	static struct platform_device anubis_device_ide0 = {
b9db83af	240	.name = "pata_platform",
bf1c56a3 BD	241	.id = 0,
	242	.num_resources = ARRAY_SIZE(anubis_ide0_resource),
	243	.resource = anubis_ide0_resource,
b9db83af BD	244	.dev = {
	245	.platform_data = &anubis_ide_platdata,
	246	.coherent_dma_mask = ~0,
	247	},
bf1c56a3 BD	248	};
	249
	250	static struct resource anubis_ide1_resource[] = {
d1c14938 TB	251	[0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
d1c14938 TB	252	[1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
fc351246	253	[2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
bf1c56a3 BD	254	};
bf1c56a3 BD	255
bf1c56a3	256	static struct platform_device anubis_device_ide1 = {
b9db83af	257	.name = "pata_platform",
bf1c56a3 BD	258	.id = 1,
	259	.num_resources = ARRAY_SIZE(anubis_ide1_resource),
	260	.resource = anubis_ide1_resource,
b9db83af BD	261	.dev = {
	262	.platform_data = &anubis_ide_platdata,
	263	.coherent_dma_mask = ~0,
	264	},
bf1c56a3	265	};
7efb833d	266
eac1d8da BD	267	/* Asix AX88796 10/100 ethernet controller */
	268
	269	static struct ax_plat_data anubis_asix_platdata = {
	270	.flags = AXFLG_MAC_FROMDEV,
	271	.wordlength = 2,
	272	.dcr_val = 0x48,
	273	.rcr_val = 0x40,
	274	};
	275
	276	static struct resource anubis_asix_resource[] = {
d1c14938	277	[0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
fc351246	278	[1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
eac1d8da BD	279	};
	280
	281	static struct platform_device anubis_device_asix = {
	282	.name = "ax88796",
	283	.id = 0,
	284	.num_resources = ARRAY_SIZE(anubis_asix_resource),
	285	.resource = anubis_asix_resource,
	286	.dev = {
	287	.platform_data = &anubis_asix_platdata,
	288	}
	289	};
	290
8a9ccb7f BD	291	/* SM501 */
	292
	293	static struct resource anubis_sm501_resource[] = {
d1c14938 TB	294	[0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
	295	[1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
	296	[2] = DEFINE_RES_IRQ(IRQ_EINT0),
8a9ccb7f BD	297	};
	298
	299	static struct sm501_initdata anubis_sm501_initdata = {
	300	.gpio_high = {
	301	.set = 0x3F000000, /* 24bit panel */
	302	.mask = 0x0,
	303	},
	304	.misc_timing = {
	305	.set = 0x010100, /* SDRAM timing */
	306	.mask = 0x1F1F00,
	307	},
	308	.misc_control = {
	309	.set = SM501_MISC_PNL_24BIT,
	310	.mask = 0,
	311	},
	312
6290ce30 BD	313	.devices = SM501_USE_GPIO,
6290ce30 BD	314
8a9ccb7f BD	315	/* set the SDRAM and bus clocks */
	316	.mclk = 72 * MHZ,
	317	.m1xclk = 144 * MHZ,
	318	};
	319
	320	static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	321	[0] = {
6290ce30	322	.bus_num = 1,
8a9ccb7f BD	323	.pin_scl = 44,
	324	.pin_sda = 45,
	325	},
	326	[1] = {
6290ce30	327	.bus_num = 2,
8a9ccb7f BD	328	.pin_scl = 40,
	329	.pin_sda = 41,
	330	},
	331	};
	332
	333	static struct sm501_platdata anubis_sm501_platdata = {
	334	.init = &anubis_sm501_initdata,
6290ce30	335	.gpio_base = -1,
8a9ccb7f BD	336	.gpio_i2c = anubis_sm501_gpio_i2c,
	337	.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
	338	};
	339
	340	static struct platform_device anubis_device_sm501 = {
	341	.name = "sm501",
	342	.id = 0,
	343	.num_resources = ARRAY_SIZE(anubis_sm501_resource),
	344	.resource = anubis_sm501_resource,
	345	.dev = {
	346	.platform_data = &anubis_sm501_platdata,
	347	},
	348	};
	349
7efb833d BD	350	/* Standard Anubis devices */
	351
	352	static struct platform_device *anubis_devices[] __initdata = {
b813248c	353	&s3c_device_ohci,
7efb833d BD	354	&s3c_device_wdt,
7efb833d BD	355	&s3c_device_adc,
3e1b776c	356	&s3c_device_i2c0,
7efb833d BD	357	&s3c_device_rtc,
7efb833d BD	358	&s3c_device_nand,
bf1c56a3 BD	359	&anubis_device_ide0,
bf1c56a3 BD	360	&anubis_device_ide1,
eac1d8da	361	&anubis_device_asix,
8a9ccb7f	362	&anubis_device_sm501,
7efb833d BD	363	};
7efb833d BD	364
2bc7509f	365	static struct clk *anubis_clocks[] __initdata = {
7efb833d BD	366	&s3c24xx_dclk0,
	367	&s3c24xx_dclk1,
	368	&s3c24xx_clkout0,
	369	&s3c24xx_clkout1,
	370	&s3c24xx_uclk,
	371	};
	372
7a28db61 BD	373	/* I2C devices. */
	374
	375	static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	376	{
	377	I2C_BOARD_INFO("tps65011", 0x48),
	378	.irq = IRQ_EINT20,
	379	}
	380	};
	381
4d3a3469 BD	382	/* Audio setup */
	383	static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	384	.have_mic = 1,
	385	.have_lout = 1,
	386	.output_cdclk = 1,
	387	.use_mpllin = 1,
	388	.amp_gpio = S3C2410_GPB(2),
	389	.amp_gain[0] = S3C2410_GPD(10),
	390	.amp_gain[1] = S3C2410_GPD(11),
	391	};
	392
5fe10ab1	393	static void __init anubis_map_io(void)
7efb833d BD	394	{
	395	/* initialise the clocks */
	396
d96a9804	397	s3c24xx_dclk0.parent = &clk_upll;
7efb833d BD	398	s3c24xx_dclk0.rate = 1210001000;
7efb833d BD	399
d96a9804	400	s3c24xx_dclk1.parent = &clk_upll;
7efb833d BD	401	s3c24xx_dclk1.rate = 2410001000;
	402
	403	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	404	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	405
	406	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	407
ce89c206 BD	408	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
ce89c206 BD	409
7efb833d BD	410	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	411	s3c24xx_init_clocks(0);
	412	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
7efb833d	413
ad3613f4 BD	414	/* check for the newer revision boards with large page nand */
	415
	416	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
	417	printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
	418	__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
	419	anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
	420	anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	421	} else {
	422	/* ensure that the GPIO is setup */
42aa322c SN	423	gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
42aa322c SN	424	gpio_free(S3C2410_GPA(0));
ad3613f4	425	}
7efb833d BD	426	}
7efb833d BD	427
57e5171c BD	428	static void __init anubis_init(void)
57e5171c BD	429	{
3e1b776c	430	s3c_i2c0_set_platdata(NULL);
2a3a1804	431	s3c_nand_set_platdata(&anubis_nand_info);
4d3a3469	432	simtec_audio_add(NULL, false, &anubis_audio);
2a3a1804	433
57e5171c	434	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
7a28db61 BD	435
	436	i2c_register_board_info(0, anubis_i2c_devs,
	437	ARRAY_SIZE(anubis_i2c_devs));
57e5171c BD	438	}
	439
	440
7efb833d BD	441	MACHINE_START(ANUBIS, "Simtec-Anubis")
7efb833d BD	442	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
69d50710	443	.atag_offset = 0x100,
7efb833d	444	.map_io = anubis_map_io,
57e5171c	445	.init_machine = anubis_init,
7efb833d	446	.init_irq = s3c24xx_init_irq,
6bb27d73	447	.init_time = s3c24xx_timer_init,
c1ba544f	448	.restart = s3c244x_restart,
7efb833d	449	MACHINE_END