[deliverable/linux.git] / arch / arm / mach-s3c24xx / mach-anubis.c

/* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
 * Copyright 2003-2009 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/anubis-map.h>
#include <mach/anubis-irq.h>
#include <mach/anubis-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <net/ax88796.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/audio-simtec.h>

#include "simtec.h"
#include "common.h"

#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"

static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */

  {
	.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	.pfn		= __phys_to_pfn(0x0),
	.length		= SZ_4M,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)S3C24XX_VA_ISA_WORD,
	.pfn		= __phys_to_pfn(0x0),
	.length 	= SZ_4M,
	.type		= MT_DEVICE,
  },

  /* we could possibly compress the next set down into a set of smaller tables
   * pagetables, but that would mean using an L2 section, and it still means
   * we cannot actually feed the same register to an LDR due to 16K spacing
   */

  /* CPLD control registers */

  {
	.virtual	= (u32)ANUBIS_VA_CTRL1,
	.pfn		= __phys_to_pfn(ANUBIS_PA_CTRL1),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)ANUBIS_VA_IDREG,
	.pfn		= __phys_to_pfn(ANUBIS_PA_IDREG),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[1] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
};

/* NAND Flash on Anubis board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition __initdata anubis_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Anubis has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
};

static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	tmp |= slot;

	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);

	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}

static struct s3c2410_platform_nand __initdata anubis_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),
	.sets		= anubis_nand_sets,
	.select_chip	= anubis_nand_select,
};

/* IDE channels */

static struct pata_platform_info anubis_ide_platdata = {
	.ioport_shift	= 5,
};

static struct resource anubis_ide0_resource[] = {
	{
		.start	= S3C2410_CS3,
		.end	= S3C2410_CS3 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS3 + (1<<26) + (6*32),
		.end	= S3C2410_CS3 + (1<<26) + (7*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide0 = {
	.name		= "pata_platform",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_ide0_resource),
	.resource	= anubis_ide0_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

static struct resource anubis_ide1_resource[] = {
	{
		.start	= S3C2410_CS4,
		.end	= S3C2410_CS4 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS4 + (1<<26) + (6*32),
		.end	= S3C2410_CS4 + (1<<26) + (7*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide1 = {
	.name		= "pata_platform",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(anubis_ide1_resource),
	.resource	= anubis_ide1_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data anubis_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource anubis_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5,
		.end   = S3C2410_CS5 + (0x20 * 0x20) -1,
		.flags = IORESOURCE_MEM
	},
	[1] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device anubis_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_asix_resource),
	.resource	= anubis_asix_resource,
	.dev		= {
		.platform_data = &anubis_asix_platdata,
	}
};

/* SM501 */

static struct resource anubis_sm501_resource[] = {
	[0] = {
		.start	= S3C2410_CS2,
		.end	= S3C2410_CS2 + SZ_8M,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= S3C2410_CS2 + SZ_64M - SZ_2M,
		.end	= S3C2410_CS2 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[2] = {
		.start	= IRQ_EINT0,
		.end	= IRQ_EINT0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct sm501_initdata anubis_sm501_initdata = {
	.gpio_high	= {
		.set	= 0x3F000000,		/* 24bit panel */
		.mask	= 0x0,
	},
	.misc_timing	= {
		.set	= 0x010100,		/* SDRAM timing */
		.mask	= 0x1F1F00,
	},
	.misc_control	= {
		.set	= SM501_MISC_PNL_24BIT,
		.mask	= 0,
	},

	.devices	= SM501_USE_GPIO,

	/* set the SDRAM and bus clocks */
	.mclk		= 72 * MHZ,
	.m1xclk		= 144 * MHZ,
};

static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	[0] = {
		.bus_num	= 1,
		.pin_scl	= 44,
		.pin_sda	= 45,
	},
	[1] = {
		.bus_num	= 2,
		.pin_scl	= 40,
		.pin_sda	= 41,
	},
};

static struct sm501_platdata anubis_sm501_platdata = {
	.init		= &anubis_sm501_initdata,
	.gpio_base	= -1,
	.gpio_i2c	= anubis_sm501_gpio_i2c,
	.gpio_i2c_nr	= ARRAY_SIZE(anubis_sm501_gpio_i2c),
};

static struct platform_device anubis_device_sm501 = {
	.name		= "sm501",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_sm501_resource),
	.resource	= anubis_sm501_resource,
	.dev		= {
		.platform_data = &anubis_sm501_platdata,
	},
};

/* Standard Anubis devices */

static struct platform_device *anubis_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&anubis_device_ide0,
	&anubis_device_ide1,
	&anubis_device_asix,
	&anubis_device_sm501,
};

static struct clk *anubis_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

/* I2C devices. */

static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
	}
};

/* Audio setup */
static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	.have_mic	= 1,
	.have_lout	= 1,
	.output_cdclk	= 1,
	.use_mpllin	= 1,
	.amp_gpio	= S3C2410_GPB(2),
	.amp_gain[0]	= S3C2410_GPD(10),
	.amp_gain[1]	= S3C2410_GPD(11),
};

static void __init anubis_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));

	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
		printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
		       __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
		anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
		anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	} else {
		/* ensure that the GPIO is setup */
		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
	}
}

static void __init anubis_init(void)
{
	s3c_i2c0_set_platdata(NULL);
	s3c_nand_set_platdata(&anubis_nand_info);
	simtec_audio_add(NULL, false, &anubis_audio);

	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));

	i2c_register_board_info(0, anubis_i2c_devs,
				ARRAY_SIZE(anubis_i2c_devs));
}


MACHINE_START(ANUBIS, "Simtec-Anubis")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.atag_offset	= 0x100,
	.map_io		= anubis_map_io,
	.init_machine	= anubis_init,
	.init_irq	= s3c24xx_init_irq,
	.timer		= &s3c24xx_timer,
	.restart	= s3c244x_restart,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-anubis.c
7efb833d	2	*
50f430e3	3	* Copyright 2003-2009 Simtec Electronics
7efb833d BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
7efb833d BD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
7efb833d BD	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
b6d1f542	19	#include <linux/serial_core.h>
d052d1be	20	#include <linux/platform_device.h>
b9db83af	21	#include <linux/ata_platform.h>
7a28db61	22	#include <linux/i2c.h>
fced80c7	23	#include <linux/io.h>
8a9ccb7f BD	24	#include <linux/sm501.h>
	25	#include <linux/sm501-regs.h>
	26
7efb833d BD	27	#include <asm/mach/arch.h>
	28	#include <asm/mach/map.h>
	29	#include <asm/mach/irq.h>
	30
a09e64fb RK	31	#include <mach/anubis-map.h>
	32	#include <mach/anubis-irq.h>
	33	#include <mach/anubis-cpld.h>
7efb833d	34
a09e64fb	35	#include <mach/hardware.h>
7efb833d BD	36	#include <asm/irq.h>
	37	#include <asm/mach-types.h>
	38
a2b7ba9c	39	#include <plat/regs-serial.h>
a09e64fb RK	40	#include <mach/regs-gpio.h>
	41	#include <mach/regs-mem.h>
	42	#include <mach/regs-lcd.h>
7926b5a3	43	#include <plat/nand.h>
3e1b776c	44	#include <plat/iic.h>
7efb833d BD	45
	46	#include <linux/mtd/mtd.h>
	47	#include <linux/mtd/nand.h>
	48	#include <linux/mtd/nand_ecc.h>
	49	#include <linux/mtd/partitions.h>
	50
eac1d8da BD	51	#include <net/ax88796.h>
eac1d8da BD	52
d5120ae7	53	#include <plat/clock.h>
a2b7ba9c BD	54	#include <plat/devs.h>
a2b7ba9c BD	55	#include <plat/cpu.h>
4d3a3469	56	#include <plat/audio-simtec.h>
7efb833d	57
ec2cc753	58	#include "simtec.h"
b27b0727 KK	59	#include "common.h"
b27b0727 KK	60
50f430e3	61	#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
7efb833d BD	62
	63	static struct map_desc anubis_iodesc[] __initdata = {
	64	/* ISA IO areas */
	65
8dd52311 BD	66	{
	67	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	68	.pfn = __phys_to_pfn(0x0),
	69	.length = SZ_4M,
705630db	70	.type = MT_DEVICE,
8dd52311 BD	71	}, {
	72	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	73	.pfn = __phys_to_pfn(0x0),
705630db BD	74	.length = SZ_4M,
705630db BD	75	.type = MT_DEVICE,
8dd52311	76	},
7efb833d BD	77
	78	/* we could possibly compress the next set down into a set of smaller tables
	79	* pagetables, but that would mean using an L2 section, and it still means
	80	* we cannot actually feed the same register to an LDR due to 16K spacing
	81	*/
	82
	83	/* CPLD control registers */
	84
8dd52311 BD	85	{
	86	.virtual = (u32)ANUBIS_VA_CTRL1,
	87	.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
	88	.length = SZ_4K,
705630db	89	.type = MT_DEVICE,
8dd52311	90	}, {
6c1640d5 BD	91	.virtual = (u32)ANUBIS_VA_IDREG,
6c1640d5 BD	92	.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
8dd52311	93	.length = SZ_4K,
705630db	94	.type = MT_DEVICE,
8dd52311	95	},
7efb833d BD	96	};
	97
	98	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	99	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	100	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	101
66a9b49a	102	static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
7efb833d BD	103	[0] = {
	104	.hwport = 0,
	105	.flags = 0,
	106	.ucon = UCON,
	107	.ulcon = ULCON,
	108	.ufcon = UFCON,
afba7f91	109	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
7efb833d BD	110	},
	111	[1] = {
	112	.hwport = 2,
	113	.flags = 0,
	114	.ucon = UCON,
	115	.ulcon = ULCON,
	116	.ufcon = UFCON,
afba7f91	117	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
7efb833d BD	118	},
	119	};
	120
	121	/* NAND Flash on Anubis board */
	122
	123	static int external_map[] = { 2 };
	124	static int chip0_map[] = { 0 };
	125	static int chip1_map[] = { 1 };
	126
2a3a1804	127	static struct mtd_partition __initdata anubis_default_nand_part[] = {
7efb833d BD	128	[0] = {
	129	.name = "Boot Agent",
	130	.size = SZ_16K,
705630db	131	.offset = 0,
7efb833d BD	132	},
	133	[1] = {
	134	.name = "/boot",
	135	.size = SZ_4M - SZ_16K,
	136	.offset = SZ_16K,
	137	},
	138	[2] = {
	139	.name = "user1",
	140	.offset = SZ_4M,
	141	.size = SZ_32M - SZ_4M,
	142	},
	143	[3] = {
	144	.name = "user2",
	145	.offset = SZ_32M,
	146	.size = MTDPART_SIZ_FULL,
	147	}
	148	};
	149
2a3a1804	150	static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
ad3613f4 BD	151	[0] = {
	152	.name = "Boot Agent",
	153	.size = SZ_128K,
	154	.offset = 0,
	155	},
	156	[1] = {
	157	.name = "/boot",
	158	.size = SZ_4M - SZ_128K,
	159	.offset = SZ_128K,
	160	},
	161	[2] = {
	162	.name = "user1",
	163	.offset = SZ_4M,
	164	.size = SZ_32M - SZ_4M,
	165	},
	166	[3] = {
	167	.name = "user2",
	168	.offset = SZ_32M,
	169	.size = MTDPART_SIZ_FULL,
	170	}
	171	};
	172
7efb833d BD	173	/* the Anubis has 3 selectable slots for nand-flash, the two
	174	* on-board chip areas, as well as the external slot.
	175	*
	176	* Note, there is no current hot-plug support for the External
	177	* socket.
	178	*/
	179
2a3a1804	180	static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
7efb833d BD	181	[1] = {
	182	.name = "External",
	183	.nr_chips = 1,
	184	.nr_map = external_map,
	185	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	186	.partitions = anubis_default_nand_part,
7efb833d BD	187	},
	188	[0] = {
	189	.name = "chip0",
	190	.nr_chips = 1,
	191	.nr_map = chip0_map,
	192	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	193	.partitions = anubis_default_nand_part,
7efb833d BD	194	},
	195	[2] = {
	196	.name = "chip1",
	197	.nr_chips = 1,
	198	.nr_map = chip1_map,
	199	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	200	.partitions = anubis_default_nand_part,
7efb833d BD	201	},
	202	};
	203
	204	static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
	205	{
	206	unsigned int tmp;
	207
	208	slot = set->nr_map[slot] & 3;
	209
	210	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
	211	slot, set, set->nr_map);
	212
	213	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	214	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	215	tmp \|= slot;
	216
	217	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
	218
	219	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
	220	}
	221
2a3a1804	222	static struct s3c2410_platform_nand __initdata anubis_nand_info = {
7efb833d	223	.tacls = 25,
661e6acf BD	224	.twrph0 = 55,
661e6acf BD	225	.twrph1 = 40,
7efb833d BD	226	.nr_sets = ARRAY_SIZE(anubis_nand_sets),
	227	.sets = anubis_nand_sets,
	228	.select_chip = anubis_nand_select,
	229	};
	230
bf1c56a3 BD	231	/* IDE channels */
bf1c56a3 BD	232
019dbaa1	233	static struct pata_platform_info anubis_ide_platdata = {
b9db83af BD	234	.ioport_shift = 5,
	235	};
	236
bf1c56a3 BD	237	static struct resource anubis_ide0_resource[] = {
	238	{
	239	.start = S3C2410_CS3,
	240	.end = S3C2410_CS3 + (8*32) - 1,
	241	.flags = IORESOURCE_MEM,
	242	}, {
b9db83af BD	243	.start = S3C2410_CS3 + (1<<26) + (6*32),
b9db83af BD	244	.end = S3C2410_CS3 + (1<<26) + (7*32) - 1,
bf1c56a3 BD	245	.flags = IORESOURCE_MEM,
	246	}, {
	247	.start = IRQ_IDE0,
	248	.end = IRQ_IDE0,
	249	.flags = IORESOURCE_IRQ,
	250	},
	251	};
	252
	253	static struct platform_device anubis_device_ide0 = {
b9db83af	254	.name = "pata_platform",
bf1c56a3 BD	255	.id = 0,
	256	.num_resources = ARRAY_SIZE(anubis_ide0_resource),
	257	.resource = anubis_ide0_resource,
b9db83af BD	258	.dev = {
	259	.platform_data = &anubis_ide_platdata,
	260	.coherent_dma_mask = ~0,
	261	},
bf1c56a3 BD	262	};
	263
	264	static struct resource anubis_ide1_resource[] = {
	265	{
	266	.start = S3C2410_CS4,
	267	.end = S3C2410_CS4 + (8*32) - 1,
	268	.flags = IORESOURCE_MEM,
	269	}, {
b9db83af BD	270	.start = S3C2410_CS4 + (1<<26) + (6*32),
b9db83af BD	271	.end = S3C2410_CS4 + (1<<26) + (7*32) - 1,
bf1c56a3 BD	272	.flags = IORESOURCE_MEM,
	273	}, {
	274	.start = IRQ_IDE0,
	275	.end = IRQ_IDE0,
	276	.flags = IORESOURCE_IRQ,
	277	},
	278	};
	279
bf1c56a3	280	static struct platform_device anubis_device_ide1 = {
b9db83af	281	.name = "pata_platform",
bf1c56a3 BD	282	.id = 1,
	283	.num_resources = ARRAY_SIZE(anubis_ide1_resource),
	284	.resource = anubis_ide1_resource,
b9db83af BD	285	.dev = {
	286	.platform_data = &anubis_ide_platdata,
	287	.coherent_dma_mask = ~0,
	288	},
bf1c56a3	289	};
7efb833d	290
eac1d8da BD	291	/* Asix AX88796 10/100 ethernet controller */
	292
	293	static struct ax_plat_data anubis_asix_platdata = {
	294	.flags = AXFLG_MAC_FROMDEV,
	295	.wordlength = 2,
	296	.dcr_val = 0x48,
	297	.rcr_val = 0x40,
	298	};
	299
	300	static struct resource anubis_asix_resource[] = {
	301	[0] = {
	302	.start = S3C2410_CS5,
	303	.end = S3C2410_CS5 + (0x20 * 0x20) -1,
	304	.flags = IORESOURCE_MEM
	305	},
	306	[1] = {
	307	.start = IRQ_ASIX,
	308	.end = IRQ_ASIX,
	309	.flags = IORESOURCE_IRQ
	310	}
	311	};
	312
	313	static struct platform_device anubis_device_asix = {
	314	.name = "ax88796",
	315	.id = 0,
	316	.num_resources = ARRAY_SIZE(anubis_asix_resource),
	317	.resource = anubis_asix_resource,
	318	.dev = {
	319	.platform_data = &anubis_asix_platdata,
	320	}
	321	};
	322
8a9ccb7f BD	323	/* SM501 */
	324
	325	static struct resource anubis_sm501_resource[] = {
	326	[0] = {
	327	.start = S3C2410_CS2,
	328	.end = S3C2410_CS2 + SZ_8M,
	329	.flags = IORESOURCE_MEM,
	330	},
	331	[1] = {
	332	.start = S3C2410_CS2 + SZ_64M - SZ_2M,
	333	.end = S3C2410_CS2 + SZ_64M - 1,
	334	.flags = IORESOURCE_MEM,
	335	},
	336	[2] = {
	337	.start = IRQ_EINT0,
	338	.end = IRQ_EINT0,
	339	.flags = IORESOURCE_IRQ,
	340	},
	341	};
	342
	343	static struct sm501_initdata anubis_sm501_initdata = {
	344	.gpio_high = {
	345	.set = 0x3F000000, /* 24bit panel */
	346	.mask = 0x0,
	347	},
	348	.misc_timing = {
	349	.set = 0x010100, /* SDRAM timing */
	350	.mask = 0x1F1F00,
	351	},
	352	.misc_control = {
	353	.set = SM501_MISC_PNL_24BIT,
	354	.mask = 0,
	355	},
	356
6290ce30 BD	357	.devices = SM501_USE_GPIO,
6290ce30 BD	358
8a9ccb7f BD	359	/* set the SDRAM and bus clocks */
	360	.mclk = 72 * MHZ,
	361	.m1xclk = 144 * MHZ,
	362	};
	363
	364	static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	365	[0] = {
6290ce30	366	.bus_num = 1,
8a9ccb7f BD	367	.pin_scl = 44,
	368	.pin_sda = 45,
	369	},
	370	[1] = {
6290ce30	371	.bus_num = 2,
8a9ccb7f BD	372	.pin_scl = 40,
	373	.pin_sda = 41,
	374	},
	375	};
	376
	377	static struct sm501_platdata anubis_sm501_platdata = {
	378	.init = &anubis_sm501_initdata,
6290ce30	379	.gpio_base = -1,
8a9ccb7f BD	380	.gpio_i2c = anubis_sm501_gpio_i2c,
	381	.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
	382	};
	383
	384	static struct platform_device anubis_device_sm501 = {
	385	.name = "sm501",
	386	.id = 0,
	387	.num_resources = ARRAY_SIZE(anubis_sm501_resource),
	388	.resource = anubis_sm501_resource,
	389	.dev = {
	390	.platform_data = &anubis_sm501_platdata,
	391	},
	392	};
	393
7efb833d BD	394	/* Standard Anubis devices */
	395
	396	static struct platform_device *anubis_devices[] __initdata = {
b813248c	397	&s3c_device_ohci,
7efb833d BD	398	&s3c_device_wdt,
7efb833d BD	399	&s3c_device_adc,
3e1b776c	400	&s3c_device_i2c0,
7efb833d BD	401	&s3c_device_rtc,
7efb833d BD	402	&s3c_device_nand,
bf1c56a3 BD	403	&anubis_device_ide0,
bf1c56a3 BD	404	&anubis_device_ide1,
eac1d8da	405	&anubis_device_asix,
8a9ccb7f	406	&anubis_device_sm501,
7efb833d BD	407	};
7efb833d BD	408
2bc7509f	409	static struct clk *anubis_clocks[] __initdata = {
7efb833d BD	410	&s3c24xx_dclk0,
	411	&s3c24xx_dclk1,
	412	&s3c24xx_clkout0,
	413	&s3c24xx_clkout1,
	414	&s3c24xx_uclk,
	415	};
	416
7a28db61 BD	417	/* I2C devices. */
	418
	419	static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	420	{
	421	I2C_BOARD_INFO("tps65011", 0x48),
	422	.irq = IRQ_EINT20,
	423	}
	424	};
	425
4d3a3469 BD	426	/* Audio setup */
	427	static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	428	.have_mic = 1,
	429	.have_lout = 1,
	430	.output_cdclk = 1,
	431	.use_mpllin = 1,
	432	.amp_gpio = S3C2410_GPB(2),
	433	.amp_gain[0] = S3C2410_GPD(10),
	434	.amp_gain[1] = S3C2410_GPD(11),
	435	};
	436
5fe10ab1	437	static void __init anubis_map_io(void)
7efb833d BD	438	{
	439	/* initialise the clocks */
	440
d96a9804	441	s3c24xx_dclk0.parent = &clk_upll;
7efb833d BD	442	s3c24xx_dclk0.rate = 1210001000;
7efb833d BD	443
d96a9804	444	s3c24xx_dclk1.parent = &clk_upll;
7efb833d BD	445	s3c24xx_dclk1.rate = 2410001000;
	446
	447	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	448	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	449
	450	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	451
ce89c206 BD	452	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
ce89c206 BD	453
7efb833d BD	454	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	455	s3c24xx_init_clocks(0);
	456	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
7efb833d	457
ad3613f4 BD	458	/* check for the newer revision boards with large page nand */
	459
	460	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
	461	printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
	462	__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
	463	anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
	464	anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	465	} else {
	466	/* ensure that the GPIO is setup */
070276d5	467	s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
ad3613f4	468	}
7efb833d BD	469	}
7efb833d BD	470
57e5171c BD	471	static void __init anubis_init(void)
57e5171c BD	472	{
3e1b776c	473	s3c_i2c0_set_platdata(NULL);
2a3a1804	474	s3c_nand_set_platdata(&anubis_nand_info);
4d3a3469	475	simtec_audio_add(NULL, false, &anubis_audio);
2a3a1804	476
57e5171c	477	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
7a28db61 BD	478
	479	i2c_register_board_info(0, anubis_i2c_devs,
	480	ARRAY_SIZE(anubis_i2c_devs));
57e5171c BD	481	}
	482
	483
7efb833d BD	484	MACHINE_START(ANUBIS, "Simtec-Anubis")
7efb833d BD	485	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
69d50710	486	.atag_offset = 0x100,
7efb833d	487	.map_io = anubis_map_io,
57e5171c	488	.init_machine = anubis_init,
7efb833d BD	489	.init_irq = s3c24xx_init_irq,
7efb833d BD	490	.timer = &s3c24xx_timer,
c1ba544f	491	.restart = s3c244x_restart,
7efb833d	492	MACHINE_END