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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/mach-bast.c |
2 | * | |
ccae941e | 3 | * Copyright 2003-2008 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * http://www.simtec.co.uk/products/EB2410ITX/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
1da177e4 LT |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
ec976d6e | 19 | #include <linux/gpio.h> |
bb072c3c | 20 | #include <linux/syscore_ops.h> |
b6d1f542 | 21 | #include <linux/serial_core.h> |
d052d1be | 22 | #include <linux/platform_device.h> |
d97a666f | 23 | #include <linux/dm9000.h> |
b7a12d19 | 24 | #include <linux/ata_platform.h> |
042cf0f2 | 25 | #include <linux/i2c.h> |
fced80c7 | 26 | #include <linux/io.h> |
bbd7e5e1 KK |
27 | #include <linux/serial_8250.h> |
28 | ||
29 | #include <linux/mtd/mtd.h> | |
30 | #include <linux/mtd/nand.h> | |
31 | #include <linux/mtd/nand_ecc.h> | |
32 | #include <linux/mtd/partitions.h> | |
33 | ||
34 | #include <linux/platform_data/asoc-s3c24xx_simtec.h> | |
35 | #include <linux/platform_data/hwmon-s3c.h> | |
36 | #include <linux/platform_data/i2c-s3c2410.h> | |
37 | #include <linux/platform_data/mtd-nand-s3c2410.h> | |
1da177e4 | 38 | |
5ce4b1fe BD |
39 | #include <net/ax88796.h> |
40 | ||
bbd7e5e1 | 41 | #include <asm/irq.h> |
1da177e4 LT |
42 | #include <asm/mach/arch.h> |
43 | #include <asm/mach/map.h> | |
44 | #include <asm/mach/irq.h> | |
1da177e4 LT |
45 | #include <asm/mach-types.h> |
46 | ||
bbd7e5e1 KK |
47 | #include <mach/fb.h> |
48 | #include <mach/hardware.h> | |
a09e64fb | 49 | #include <mach/regs-gpio.h> |
a09e64fb | 50 | #include <mach/regs-lcd.h> |
65cc3370 | 51 | |
d5120ae7 | 52 | #include <plat/clock.h> |
a2b7ba9c | 53 | #include <plat/cpu.h> |
ca0b4901 | 54 | #include <plat/cpu-freq.h> |
bbd7e5e1 | 55 | #include <plat/devs.h> |
40b956f0 | 56 | #include <plat/gpio-cfg.h> |
bbd7e5e1 | 57 | #include <plat/regs-serial.h> |
9d529c6e | 58 | |
bbd7e5e1 | 59 | #include "bast.h" |
b27b0727 | 60 | #include "common.h" |
bbd7e5e1 | 61 | #include "simtec.h" |
1da177e4 | 62 | |
ccae941e | 63 | #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics" |
1da177e4 LT |
64 | |
65 | /* macros for virtual address mods for the io space entries */ | |
66 | #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) | |
67 | #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) | |
68 | #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) | |
69 | #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) | |
70 | ||
71 | /* macros to modify the physical addresses for io space */ | |
72 | ||
1d23b65d BD |
73 | #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2)) |
74 | #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3)) | |
75 | #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4)) | |
76 | #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5)) | |
1da177e4 LT |
77 | |
78 | static struct map_desc bast_iodesc[] __initdata = { | |
79 | /* ISA IO areas */ | |
1d23b65d BD |
80 | { |
81 | .virtual = (u32)S3C24XX_VA_ISA_BYTE, | |
82 | .pfn = PA_CS2(BAST_PA_ISAIO), | |
83 | .length = SZ_16M, | |
84 | .type = MT_DEVICE, | |
85 | }, { | |
86 | .virtual = (u32)S3C24XX_VA_ISA_WORD, | |
87 | .pfn = PA_CS3(BAST_PA_ISAIO), | |
88 | .length = SZ_16M, | |
89 | .type = MT_DEVICE, | |
90 | }, | |
1da177e4 | 91 | /* bast CPLD control registers, and external interrupt controls */ |
1d23b65d BD |
92 | { |
93 | .virtual = (u32)BAST_VA_CTRL1, | |
94 | .pfn = __phys_to_pfn(BAST_PA_CTRL1), | |
95 | .length = SZ_1M, | |
96 | .type = MT_DEVICE, | |
97 | }, { | |
98 | .virtual = (u32)BAST_VA_CTRL2, | |
99 | .pfn = __phys_to_pfn(BAST_PA_CTRL2), | |
100 | .length = SZ_1M, | |
101 | .type = MT_DEVICE, | |
102 | }, { | |
103 | .virtual = (u32)BAST_VA_CTRL3, | |
104 | .pfn = __phys_to_pfn(BAST_PA_CTRL3), | |
105 | .length = SZ_1M, | |
106 | .type = MT_DEVICE, | |
107 | }, { | |
108 | .virtual = (u32)BAST_VA_CTRL4, | |
109 | .pfn = __phys_to_pfn(BAST_PA_CTRL4), | |
110 | .length = SZ_1M, | |
111 | .type = MT_DEVICE, | |
112 | }, | |
1da177e4 | 113 | /* PC104 IRQ mux */ |
1d23b65d BD |
114 | { |
115 | .virtual = (u32)BAST_VA_PC104_IRQREQ, | |
116 | .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ), | |
117 | .length = SZ_1M, | |
118 | .type = MT_DEVICE, | |
119 | }, { | |
120 | .virtual = (u32)BAST_VA_PC104_IRQRAW, | |
121 | .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW), | |
122 | .length = SZ_1M, | |
123 | .type = MT_DEVICE, | |
124 | }, { | |
125 | .virtual = (u32)BAST_VA_PC104_IRQMASK, | |
126 | .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK), | |
127 | .length = SZ_1M, | |
128 | .type = MT_DEVICE, | |
129 | }, | |
1da177e4 LT |
130 | |
131 | /* peripheral space... one for each of fast/slow/byte/16bit */ | |
132 | /* note, ide is only decoded in word space, even though some registers | |
133 | * are only 8bit */ | |
134 | ||
135 | /* slow, byte */ | |
136 | { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
137 | { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 138 | { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
139 | |
140 | /* slow, word */ | |
141 | { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
142 | { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 143 | { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
144 | |
145 | /* fast, byte */ | |
146 | { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
147 | { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 148 | { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
149 | |
150 | /* fast, word */ | |
151 | { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
152 | { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 153 | { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
154 | }; |
155 | ||
156 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | |
157 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | |
158 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
159 | ||
66a9b49a | 160 | static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { |
1da177e4 LT |
161 | [0] = { |
162 | .hwport = 0, | |
163 | .flags = 0, | |
164 | .ucon = UCON, | |
165 | .ulcon = ULCON, | |
166 | .ufcon = UFCON, | |
1da177e4 LT |
167 | }, |
168 | [1] = { | |
169 | .hwport = 1, | |
170 | .flags = 0, | |
171 | .ucon = UCON, | |
172 | .ulcon = ULCON, | |
173 | .ufcon = UFCON, | |
1da177e4 LT |
174 | }, |
175 | /* port 2 is not actually used */ | |
176 | [2] = { | |
177 | .hwport = 2, | |
178 | .flags = 0, | |
179 | .ucon = UCON, | |
180 | .ulcon = ULCON, | |
181 | .ufcon = UFCON, | |
1da177e4 LT |
182 | } |
183 | }; | |
184 | ||
1da177e4 LT |
185 | /* NAND Flash on BAST board */ |
186 | ||
6ddc4b07 | 187 | #ifdef CONFIG_PM |
bb072c3c | 188 | static int bast_pm_suspend(void) |
6ddc4b07 BD |
189 | { |
190 | /* ensure that an nRESET is not generated on resume. */ | |
408c8b8c | 191 | gpio_direction_output(S3C2410_GPA(21), 1); |
6ddc4b07 BD |
192 | return 0; |
193 | } | |
194 | ||
bb072c3c | 195 | static void bast_pm_resume(void) |
6ddc4b07 | 196 | { |
40b956f0 | 197 | s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); |
6ddc4b07 BD |
198 | } |
199 | ||
200 | #else | |
201 | #define bast_pm_suspend NULL | |
202 | #define bast_pm_resume NULL | |
203 | #endif | |
204 | ||
bb072c3c | 205 | static struct syscore_ops bast_pm_syscore_ops = { |
6ddc4b07 BD |
206 | .suspend = bast_pm_suspend, |
207 | .resume = bast_pm_resume, | |
208 | }; | |
209 | ||
1da177e4 LT |
210 | static int smartmedia_map[] = { 0 }; |
211 | static int chip0_map[] = { 1 }; | |
212 | static int chip1_map[] = { 2 }; | |
213 | static int chip2_map[] = { 3 }; | |
214 | ||
2a3a1804 | 215 | static struct mtd_partition __initdata bast_default_nand_part[] = { |
1da177e4 LT |
216 | [0] = { |
217 | .name = "Boot Agent", | |
218 | .size = SZ_16K, | |
b526bf23 | 219 | .offset = 0, |
1da177e4 LT |
220 | }, |
221 | [1] = { | |
222 | .name = "/boot", | |
223 | .size = SZ_4M - SZ_16K, | |
224 | .offset = SZ_16K, | |
225 | }, | |
226 | [2] = { | |
227 | .name = "user", | |
228 | .offset = SZ_4M, | |
229 | .size = MTDPART_SIZ_FULL, | |
230 | } | |
231 | }; | |
232 | ||
233 | /* the bast has 4 selectable slots for nand-flash, the three | |
234 | * on-board chip areas, as well as the external SmartMedia | |
235 | * slot. | |
236 | * | |
237 | * Note, there is no current hot-plug support for the SmartMedia | |
238 | * socket. | |
239 | */ | |
240 | ||
2a3a1804 | 241 | static struct s3c2410_nand_set __initdata bast_nand_sets[] = { |
1da177e4 LT |
242 | [0] = { |
243 | .name = "SmartMedia", | |
244 | .nr_chips = 1, | |
245 | .nr_map = smartmedia_map, | |
d3ef7ee4 | 246 | .options = NAND_SCAN_SILENT_NODEV, |
1da177e4 | 247 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), |
b526bf23 | 248 | .partitions = bast_default_nand_part, |
1da177e4 LT |
249 | }, |
250 | [1] = { | |
251 | .name = "chip0", | |
252 | .nr_chips = 1, | |
253 | .nr_map = chip0_map, | |
254 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), | |
b526bf23 | 255 | .partitions = bast_default_nand_part, |
1da177e4 LT |
256 | }, |
257 | [2] = { | |
258 | .name = "chip1", | |
259 | .nr_chips = 1, | |
260 | .nr_map = chip1_map, | |
d3ef7ee4 | 261 | .options = NAND_SCAN_SILENT_NODEV, |
1da177e4 | 262 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), |
b526bf23 | 263 | .partitions = bast_default_nand_part, |
1da177e4 LT |
264 | }, |
265 | [3] = { | |
266 | .name = "chip2", | |
267 | .nr_chips = 1, | |
268 | .nr_map = chip2_map, | |
d3ef7ee4 | 269 | .options = NAND_SCAN_SILENT_NODEV, |
1da177e4 | 270 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), |
b526bf23 | 271 | .partitions = bast_default_nand_part, |
1da177e4 LT |
272 | } |
273 | }; | |
274 | ||
275 | static void bast_nand_select(struct s3c2410_nand_set *set, int slot) | |
276 | { | |
277 | unsigned int tmp; | |
278 | ||
279 | slot = set->nr_map[slot] & 3; | |
280 | ||
281 | pr_debug("bast_nand: selecting slot %d (set %p,%p)\n", | |
282 | slot, set, set->nr_map); | |
283 | ||
284 | tmp = __raw_readb(BAST_VA_CTRL2); | |
285 | tmp &= BAST_CPLD_CTLR2_IDERST; | |
286 | tmp |= slot; | |
287 | tmp |= BAST_CPLD_CTRL2_WNAND; | |
288 | ||
289 | pr_debug("bast_nand: ctrl2 now %02x\n", tmp); | |
290 | ||
291 | __raw_writeb(tmp, BAST_VA_CTRL2); | |
292 | } | |
293 | ||
2a3a1804 | 294 | static struct s3c2410_platform_nand __initdata bast_nand_info = { |
b048dbf4 BD |
295 | .tacls = 30, |
296 | .twrph0 = 60, | |
297 | .twrph1 = 60, | |
1da177e4 LT |
298 | .nr_sets = ARRAY_SIZE(bast_nand_sets), |
299 | .sets = bast_nand_sets, | |
300 | .select_chip = bast_nand_select, | |
301 | }; | |
302 | ||
d97a666f BD |
303 | /* DM9000 */ |
304 | ||
305 | static struct resource bast_dm9k_resource[] = { | |
52df44d1 TB |
306 | [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4), |
307 | [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40), | |
bbd7e5e1 | 308 | [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \ |
52df44d1 | 309 | | IORESOURCE_IRQ_HIGHLEVEL), |
d97a666f BD |
310 | }; |
311 | ||
312 | /* for the moment we limit ourselves to 16bit IO until some | |
313 | * better IO routines can be written and tested | |
314 | */ | |
315 | ||
9f693d7b | 316 | static struct dm9000_plat_data bast_dm9k_platdata = { |
b526bf23 | 317 | .flags = DM9000_PLATF_16BITONLY, |
d97a666f BD |
318 | }; |
319 | ||
320 | static struct platform_device bast_device_dm9k = { | |
321 | .name = "dm9000", | |
322 | .id = 0, | |
323 | .num_resources = ARRAY_SIZE(bast_dm9k_resource), | |
324 | .resource = bast_dm9k_resource, | |
325 | .dev = { | |
326 | .platform_data = &bast_dm9k_platdata, | |
327 | } | |
328 | }; | |
329 | ||
65cc3370 BD |
330 | /* serial devices */ |
331 | ||
332 | #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO) | |
333 | #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ) | |
334 | #define SERIAL_CLK (1843200) | |
335 | ||
336 | static struct plat_serial8250_port bast_sio_data[] = { | |
337 | [0] = { | |
338 | .mapbase = SERIAL_BASE + 0x2f8, | |
bbd7e5e1 | 339 | .irq = BAST_IRQ_PCSERIAL1, |
65cc3370 BD |
340 | .flags = SERIAL_FLAGS, |
341 | .iotype = UPIO_MEM, | |
342 | .regshift = 0, | |
343 | .uartclk = SERIAL_CLK, | |
344 | }, | |
345 | [1] = { | |
346 | .mapbase = SERIAL_BASE + 0x3f8, | |
bbd7e5e1 | 347 | .irq = BAST_IRQ_PCSERIAL2, |
65cc3370 BD |
348 | .flags = SERIAL_FLAGS, |
349 | .iotype = UPIO_MEM, | |
350 | .regshift = 0, | |
351 | .uartclk = SERIAL_CLK, | |
352 | }, | |
353 | { } | |
354 | }; | |
355 | ||
356 | static struct platform_device bast_sio = { | |
357 | .name = "serial8250", | |
6df29deb | 358 | .id = PLAT8250_DEV_PLATFORM, |
65cc3370 BD |
359 | .dev = { |
360 | .platform_data = &bast_sio_data, | |
361 | }, | |
362 | }; | |
1da177e4 | 363 | |
1fcf8448 BD |
364 | /* we have devices on the bus which cannot work much over the |
365 | * standard 100KHz i2c bus frequency | |
366 | */ | |
367 | ||
3e1b776c | 368 | static struct s3c2410_platform_i2c __initdata bast_i2c_info = { |
1fcf8448 BD |
369 | .flags = 0, |
370 | .slave_addr = 0x10, | |
c564e6ae | 371 | .frequency = 100*1000, |
1fcf8448 BD |
372 | }; |
373 | ||
5ce4b1fe BD |
374 | /* Asix AX88796 10/100 ethernet controller */ |
375 | ||
376 | static struct ax_plat_data bast_asix_platdata = { | |
377 | .flags = AXFLG_MAC_FROMDEV, | |
378 | .wordlength = 2, | |
379 | .dcr_val = 0x48, | |
380 | .rcr_val = 0x40, | |
381 | }; | |
382 | ||
383 | static struct resource bast_asix_resource[] = { | |
52df44d1 TB |
384 | [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20), |
385 | [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1), | |
bbd7e5e1 | 386 | [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX), |
5ce4b1fe BD |
387 | }; |
388 | ||
389 | static struct platform_device bast_device_asix = { | |
390 | .name = "ax88796", | |
391 | .id = 0, | |
392 | .num_resources = ARRAY_SIZE(bast_asix_resource), | |
393 | .resource = bast_asix_resource, | |
394 | .dev = { | |
395 | .platform_data = &bast_asix_platdata | |
396 | } | |
397 | }; | |
398 | ||
399 | /* Asix AX88796 10/100 ethernet controller parallel port */ | |
400 | ||
401 | static struct resource bast_asixpp_resource[] = { | |
52df44d1 TB |
402 | [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \ |
403 | 0x30 * 0x20), | |
5ce4b1fe BD |
404 | }; |
405 | ||
406 | static struct platform_device bast_device_axpp = { | |
407 | .name = "ax88796-pp", | |
408 | .id = 0, | |
409 | .num_resources = ARRAY_SIZE(bast_asixpp_resource), | |
410 | .resource = bast_asixpp_resource, | |
411 | }; | |
412 | ||
413 | /* LCD/VGA controller */ | |
58c8d570 | 414 | |
09fe75f6 KH |
415 | static struct s3c2410fb_display __initdata bast_lcd_info[] = { |
416 | { | |
1f411537 | 417 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
418 | .width = 640, |
419 | .height = 480, | |
5f20f69b | 420 | |
69816699 | 421 | .pixclock = 33333, |
09fe75f6 KH |
422 | .xres = 640, |
423 | .yres = 480, | |
424 | .bpp = 4, | |
1f411537 KH |
425 | .left_margin = 40, |
426 | .right_margin = 20, | |
93d11f5a | 427 | .hsync_len = 88, |
5f20f69b KH |
428 | .upper_margin = 30, |
429 | .lower_margin = 32, | |
93d11f5a | 430 | .vsync_len = 3, |
09fe75f6 | 431 | |
f28ef573 | 432 | .lcdcon5 = 0x00014b02, |
58c8d570 | 433 | }, |
09fe75f6 | 434 | { |
1f411537 | 435 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
436 | .width = 640, |
437 | .height = 480, | |
438 | ||
69816699 | 439 | .pixclock = 33333, |
09fe75f6 KH |
440 | .xres = 640, |
441 | .yres = 480, | |
442 | .bpp = 8, | |
1f411537 KH |
443 | .left_margin = 40, |
444 | .right_margin = 20, | |
93d11f5a | 445 | .hsync_len = 88, |
5f20f69b KH |
446 | .upper_margin = 30, |
447 | .lower_margin = 32, | |
93d11f5a | 448 | .vsync_len = 3, |
09fe75f6 | 449 | |
f28ef573 | 450 | .lcdcon5 = 0x00014b02, |
09fe75f6 KH |
451 | }, |
452 | { | |
1f411537 | 453 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
454 | .width = 640, |
455 | .height = 480, | |
456 | ||
69816699 | 457 | .pixclock = 33333, |
09fe75f6 KH |
458 | .xres = 640, |
459 | .yres = 480, | |
460 | .bpp = 16, | |
1f411537 KH |
461 | .left_margin = 40, |
462 | .right_margin = 20, | |
93d11f5a | 463 | .hsync_len = 88, |
5f20f69b KH |
464 | .upper_margin = 30, |
465 | .lower_margin = 32, | |
93d11f5a | 466 | .vsync_len = 3, |
09fe75f6 | 467 | |
f28ef573 | 468 | .lcdcon5 = 0x00014b02, |
09fe75f6 KH |
469 | }, |
470 | }; | |
58c8d570 | 471 | |
09fe75f6 KH |
472 | /* LCD/VGA controller */ |
473 | ||
474 | static struct s3c2410fb_mach_info __initdata bast_fb_info = { | |
475 | ||
476 | .displays = bast_lcd_info, | |
477 | .num_displays = ARRAY_SIZE(bast_lcd_info), | |
9cbae12c | 478 | .default_display = 1, |
58c8d570 BD |
479 | }; |
480 | ||
042cf0f2 BD |
481 | /* I2C devices fitted. */ |
482 | ||
483 | static struct i2c_board_info bast_i2c_devs[] __initdata = { | |
484 | { | |
485 | I2C_BOARD_INFO("tlv320aic23", 0x1a), | |
486 | }, { | |
487 | I2C_BOARD_INFO("simtec-pmu", 0x6b), | |
488 | }, { | |
489 | I2C_BOARD_INFO("ch7013", 0x75), | |
490 | }, | |
491 | }; | |
b7a12d19 | 492 | |
885f9ebe BD |
493 | static struct s3c_hwmon_pdata bast_hwmon_info = { |
494 | /* LCD contrast (0-6.6V) */ | |
495 | .in[0] = &(struct s3c_hwmon_chcfg) { | |
496 | .name = "lcd-contrast", | |
497 | .mult = 3300, | |
498 | .div = 512, | |
499 | }, | |
500 | /* LED current feedback */ | |
501 | .in[1] = &(struct s3c_hwmon_chcfg) { | |
502 | .name = "led-feedback", | |
503 | .mult = 3300, | |
504 | .div = 1024, | |
505 | }, | |
506 | /* LCD feedback (0-6.6V) */ | |
507 | .in[2] = &(struct s3c_hwmon_chcfg) { | |
508 | .name = "lcd-feedback", | |
509 | .mult = 3300, | |
510 | .div = 512, | |
511 | }, | |
512 | /* Vcore (1.8-2.0V), Vref 3.3V */ | |
513 | .in[3] = &(struct s3c_hwmon_chcfg) { | |
514 | .name = "vcore", | |
515 | .mult = 3300, | |
516 | .div = 1024, | |
517 | }, | |
518 | }; | |
519 | ||
1da177e4 | 520 | /* Standard BAST devices */ |
885f9ebe | 521 | // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 |
1da177e4 LT |
522 | |
523 | static struct platform_device *bast_devices[] __initdata = { | |
b813248c | 524 | &s3c_device_ohci, |
1da177e4 LT |
525 | &s3c_device_lcd, |
526 | &s3c_device_wdt, | |
3e1b776c | 527 | &s3c_device_i2c0, |
1da177e4 LT |
528 | &s3c_device_rtc, |
529 | &s3c_device_nand, | |
885f9ebe BD |
530 | &s3c_device_adc, |
531 | &s3c_device_hwmon, | |
d97a666f | 532 | &bast_device_dm9k, |
5ce4b1fe BD |
533 | &bast_device_asix, |
534 | &bast_device_axpp, | |
65cc3370 | 535 | &bast_sio, |
1da177e4 LT |
536 | }; |
537 | ||
2bc7509f | 538 | static struct clk *bast_clocks[] __initdata = { |
1da177e4 LT |
539 | &s3c24xx_dclk0, |
540 | &s3c24xx_dclk1, | |
541 | &s3c24xx_clkout0, | |
542 | &s3c24xx_clkout1, | |
543 | &s3c24xx_uclk, | |
544 | }; | |
545 | ||
ca0b4901 BD |
546 | static struct s3c_cpufreq_board __initdata bast_cpufreq = { |
547 | .refresh = 7800, /* 7.8usec */ | |
548 | .auto_io = 1, | |
549 | .need_io = 1, | |
550 | }; | |
551 | ||
4d3a3469 BD |
552 | static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = { |
553 | .have_mic = 1, | |
554 | .have_lout = 1, | |
555 | }; | |
556 | ||
5fe10ab1 | 557 | static void __init bast_map_io(void) |
1da177e4 LT |
558 | { |
559 | /* initialise the clocks */ | |
560 | ||
d96a9804 | 561 | s3c24xx_dclk0.parent = &clk_upll; |
1da177e4 LT |
562 | s3c24xx_dclk0.rate = 12*1000*1000; |
563 | ||
d96a9804 | 564 | s3c24xx_dclk1.parent = &clk_upll; |
1da177e4 LT |
565 | s3c24xx_dclk1.rate = 24*1000*1000; |
566 | ||
567 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | |
568 | s3c24xx_clkout1.parent = &s3c24xx_dclk1; | |
569 | ||
570 | s3c24xx_uclk.parent = &s3c24xx_clkout1; | |
571 | ||
ce89c206 BD |
572 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); |
573 | ||
6cd82ffe | 574 | s3c_hwmon_set_platdata(&bast_hwmon_info); |
3e1b776c | 575 | |
1da177e4 LT |
576 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); |
577 | s3c24xx_init_clocks(0); | |
578 | s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); | |
1da177e4 LT |
579 | } |
580 | ||
58c8d570 BD |
581 | static void __init bast_init(void) |
582 | { | |
bb072c3c | 583 | register_syscore_ops(&bast_pm_syscore_ops); |
6ddc4b07 | 584 | |
a8af6de0 | 585 | s3c_i2c0_set_platdata(&bast_i2c_info); |
2a3a1804 | 586 | s3c_nand_set_platdata(&bast_nand_info); |
09fe75f6 | 587 | s3c24xx_fb_set_platdata(&bast_fb_info); |
57e5171c | 588 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); |
9d529c6e | 589 | |
042cf0f2 BD |
590 | i2c_register_board_info(0, bast_i2c_devs, |
591 | ARRAY_SIZE(bast_i2c_devs)); | |
592 | ||
7a05a2cb | 593 | usb_simtec_init(); |
9d529c6e | 594 | nor_simtec_init(); |
4d3a3469 | 595 | simtec_audio_add(NULL, true, &bast_audio); |
ca0b4901 | 596 | |
408c8b8c BD |
597 | WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset")); |
598 | ||
ca0b4901 | 599 | s3c_cpufreq_setboard(&bast_cpufreq); |
58c8d570 | 600 | } |
1da177e4 LT |
601 | |
602 | MACHINE_START(BAST, "Simtec-BAST") | |
e9dea0c6 | 603 | /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ |
69d50710 | 604 | .atag_offset = 0x100, |
f705b1ae BD |
605 | .map_io = bast_map_io, |
606 | .init_irq = s3c24xx_init_irq, | |
58c8d570 | 607 | .init_machine = bast_init, |
6bb27d73 | 608 | .init_time = s3c24xx_timer_init, |
b27b0727 | 609 | .restart = s3c2410_restart, |
1da177e4 | 610 | MACHINE_END |