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c6184e27 BD |
1 | /* linux/arch/arm/mach-s3c2410/mach-qt2410.c |
2 | * | |
3 | * Copyright (C) 2006 by OpenMoko, Inc. | |
4 | * Author: Harald Welte <laforge@openmoko.org> | |
5 | * All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/timer.h> | |
29 | #include <linux/init.h> | |
ec976d6e | 30 | #include <linux/gpio.h> |
edbaa603 | 31 | #include <linux/device.h> |
c6184e27 BD |
32 | #include <linux/platform_device.h> |
33 | #include <linux/serial_core.h> | |
c6184e27 | 34 | #include <linux/spi/spi.h> |
aa353169 | 35 | #include <linux/spi/spi_gpio.h> |
fced80c7 | 36 | #include <linux/io.h> |
c6184e27 BD |
37 | #include <linux/mtd/mtd.h> |
38 | #include <linux/mtd/nand.h> | |
39 | #include <linux/mtd/nand_ecc.h> | |
40 | #include <linux/mtd/partitions.h> | |
41 | ||
42 | #include <asm/mach/arch.h> | |
43 | #include <asm/mach/map.h> | |
44 | #include <asm/mach/irq.h> | |
45 | ||
a09e64fb | 46 | #include <mach/hardware.h> |
c6184e27 BD |
47 | #include <asm/irq.h> |
48 | #include <asm/mach-types.h> | |
49 | ||
a09e64fb | 50 | #include <mach/leds-gpio.h> |
61c542bf | 51 | #include <mach/regs-lcd.h> |
a2b7ba9c | 52 | #include <plat/regs-serial.h> |
a09e64fb | 53 | #include <mach/fb.h> |
7926b5a3 | 54 | #include <plat/nand.h> |
57bd4b91 | 55 | #include <plat/udc.h> |
3e1b776c | 56 | #include <plat/iic.h> |
c6184e27 | 57 | |
d5120ae7 | 58 | #include <plat/common-smdk.h> |
40b956f0 | 59 | #include <plat/gpio-cfg.h> |
a2b7ba9c BD |
60 | #include <plat/devs.h> |
61 | #include <plat/cpu.h> | |
62 | #include <plat/pm.h> | |
c6184e27 | 63 | |
b27b0727 KK |
64 | #include "common.h" |
65 | ||
c6184e27 BD |
66 | static struct map_desc qt2410_iodesc[] __initdata = { |
67 | { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } | |
68 | }; | |
69 | ||
70 | #define UCON S3C2410_UCON_DEFAULT | |
71 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | |
72 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
73 | ||
74 | static struct s3c2410_uartcfg smdk2410_uartcfgs[] = { | |
75 | [0] = { | |
76 | .hwport = 0, | |
77 | .flags = 0, | |
78 | .ucon = UCON, | |
79 | .ulcon = ULCON, | |
80 | .ufcon = UFCON, | |
81 | }, | |
82 | [1] = { | |
83 | .hwport = 1, | |
84 | .flags = 0, | |
85 | .ucon = UCON, | |
86 | .ulcon = ULCON, | |
87 | .ufcon = UFCON, | |
88 | }, | |
89 | [2] = { | |
90 | .hwport = 2, | |
91 | .flags = 0, | |
92 | .ucon = UCON, | |
93 | .ulcon = ULCON, | |
94 | .ufcon = UFCON, | |
95 | } | |
96 | }; | |
97 | ||
98 | /* LCD driver info */ | |
99 | ||
09fe75f6 KH |
100 | static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = { |
101 | { | |
102 | /* Configuration for 640x480 SHARP LQ080V3DG01 */ | |
f28ef573 KH |
103 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | |
104 | S3C2410_LCDCON5_INVVLINE | | |
105 | S3C2410_LCDCON5_INVVFRAME | | |
106 | S3C2410_LCDCON5_PWREN | | |
107 | S3C2410_LCDCON5_HWSWP, | |
09fe75f6 | 108 | |
1f411537 | 109 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
110 | .width = 640, |
111 | .height = 480, | |
112 | ||
69816699 | 113 | .pixclock = 40000, /* HCLK/4 */ |
09fe75f6 KH |
114 | .xres = 640, |
115 | .yres = 480, | |
116 | .bpp = 16, | |
1f411537 KH |
117 | .left_margin = 44, |
118 | .right_margin = 116, | |
93d11f5a | 119 | .hsync_len = 96, |
5f20f69b KH |
120 | .upper_margin = 19, |
121 | .lower_margin = 11, | |
93d11f5a | 122 | .vsync_len = 15, |
c6184e27 | 123 | }, |
09fe75f6 KH |
124 | { |
125 | /* Configuration for 480x640 toppoly TD028TTEC1 */ | |
f28ef573 KH |
126 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | |
127 | S3C2410_LCDCON5_INVVLINE | | |
128 | S3C2410_LCDCON5_INVVFRAME | | |
129 | S3C2410_LCDCON5_PWREN | | |
130 | S3C2410_LCDCON5_HWSWP, | |
09fe75f6 | 131 | |
1f411537 | 132 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
133 | .width = 480, |
134 | .height = 640, | |
69816699 | 135 | .pixclock = 40000, /* HCLK/4 */ |
09fe75f6 KH |
136 | .xres = 480, |
137 | .yres = 640, | |
138 | .bpp = 16, | |
1f411537 KH |
139 | .left_margin = 8, |
140 | .right_margin = 24, | |
93d11f5a | 141 | .hsync_len = 8, |
5f20f69b KH |
142 | .upper_margin = 2, |
143 | .lower_margin = 4, | |
93d11f5a | 144 | .vsync_len = 2, |
c6184e27 | 145 | }, |
09fe75f6 KH |
146 | { |
147 | /* Config for 240x320 LCD */ | |
f28ef573 KH |
148 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | |
149 | S3C2410_LCDCON5_INVVLINE | | |
150 | S3C2410_LCDCON5_INVVFRAME | | |
151 | S3C2410_LCDCON5_PWREN | | |
152 | S3C2410_LCDCON5_HWSWP, | |
09fe75f6 | 153 | |
1f411537 | 154 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
155 | .width = 240, |
156 | .height = 320, | |
69816699 | 157 | .pixclock = 100000, /* HCLK/10 */ |
09fe75f6 KH |
158 | .xres = 240, |
159 | .yres = 320, | |
160 | .bpp = 16, | |
1f411537 KH |
161 | .left_margin = 13, |
162 | .right_margin = 8, | |
93d11f5a | 163 | .hsync_len = 4, |
5f20f69b KH |
164 | .upper_margin = 2, |
165 | .lower_margin = 7, | |
93d11f5a | 166 | .vsync_len = 4, |
c6184e27 BD |
167 | }, |
168 | }; | |
169 | ||
c6184e27 | 170 | |
09fe75f6 KH |
171 | static struct s3c2410fb_mach_info qt2410_fb_info __initdata = { |
172 | .displays = qt2410_lcd_cfg, | |
173 | .num_displays = ARRAY_SIZE(qt2410_lcd_cfg), | |
174 | .default_display = 0, | |
c6184e27 BD |
175 | |
176 | .lpcsel = ((0xCE6) & ~7) | 1<<4, | |
c6184e27 BD |
177 | }; |
178 | ||
179 | /* CS8900 */ | |
180 | ||
181 | static struct resource qt2410_cs89x0_resources[] = { | |
5fdbdd1d TB |
182 | [0] = DEFINE_RES_MEM(0x19000000, 17), |
183 | [1] = DEFINE_RES_IRQ(IRQ_EINT9), | |
c6184e27 BD |
184 | }; |
185 | ||
186 | static struct platform_device qt2410_cs89x0 = { | |
187 | .name = "cirrus-cs89x0", | |
188 | .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources), | |
189 | .resource = qt2410_cs89x0_resources, | |
190 | }; | |
191 | ||
192 | /* LED */ | |
193 | ||
194 | static struct s3c24xx_led_platdata qt2410_pdata_led = { | |
070276d5 | 195 | .gpio = S3C2410_GPB(0), |
c6184e27 BD |
196 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, |
197 | .name = "led", | |
198 | .def_trigger = "timer", | |
199 | }; | |
200 | ||
201 | static struct platform_device qt2410_led = { | |
202 | .name = "s3c24xx_led", | |
203 | .id = 0, | |
204 | .dev = { | |
205 | .platform_data = &qt2410_pdata_led, | |
206 | }, | |
207 | }; | |
208 | ||
209 | /* SPI */ | |
210 | ||
aa353169 PK |
211 | static struct spi_gpio_platform_data spi_gpio_cfg = { |
212 | .sck = S3C2410_GPG(7), | |
213 | .mosi = S3C2410_GPG(6), | |
214 | .miso = S3C2410_GPG(5), | |
c6184e27 BD |
215 | }; |
216 | ||
c6184e27 | 217 | static struct platform_device qt2410_spi = { |
aa353169 PK |
218 | .name = "spi-gpio", |
219 | .id = 1, | |
220 | .dev.platform_data = &spi_gpio_cfg, | |
c6184e27 BD |
221 | }; |
222 | ||
223 | /* Board devices */ | |
224 | ||
225 | static struct platform_device *qt2410_devices[] __initdata = { | |
b813248c | 226 | &s3c_device_ohci, |
c6184e27 BD |
227 | &s3c_device_lcd, |
228 | &s3c_device_wdt, | |
3e1b776c | 229 | &s3c_device_i2c0, |
c6184e27 BD |
230 | &s3c_device_iis, |
231 | &s3c_device_sdi, | |
232 | &s3c_device_usbgadget, | |
233 | &qt2410_spi, | |
234 | &qt2410_cs89x0, | |
235 | &qt2410_led, | |
236 | }; | |
237 | ||
2a3a1804 | 238 | static struct mtd_partition __initdata qt2410_nand_part[] = { |
c6184e27 BD |
239 | [0] = { |
240 | .name = "U-Boot", | |
241 | .size = 0x30000, | |
242 | .offset = 0, | |
243 | }, | |
244 | [1] = { | |
245 | .name = "U-Boot environment", | |
246 | .offset = 0x30000, | |
247 | .size = 0x4000, | |
248 | }, | |
249 | [2] = { | |
250 | .name = "kernel", | |
251 | .offset = 0x34000, | |
252 | .size = SZ_2M, | |
253 | }, | |
254 | [3] = { | |
255 | .name = "initrd", | |
256 | .offset = 0x234000, | |
257 | .size = SZ_4M, | |
258 | }, | |
259 | [4] = { | |
260 | .name = "jffs2", | |
261 | .offset = 0x634000, | |
262 | .size = 0x39cc000, | |
263 | }, | |
264 | }; | |
265 | ||
2a3a1804 | 266 | static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = { |
c6184e27 BD |
267 | [0] = { |
268 | .name = "NAND", | |
269 | .nr_chips = 1, | |
270 | .nr_partitions = ARRAY_SIZE(qt2410_nand_part), | |
271 | .partitions = qt2410_nand_part, | |
272 | }, | |
273 | }; | |
274 | ||
275 | /* choose a set of timings which should suit most 512Mbit | |
276 | * chips and beyond. | |
277 | */ | |
278 | ||
2a3a1804 | 279 | static struct s3c2410_platform_nand __initdata qt2410_nand_info = { |
c6184e27 BD |
280 | .tacls = 20, |
281 | .twrph0 = 60, | |
282 | .twrph1 = 20, | |
283 | .nr_sets = ARRAY_SIZE(qt2410_nand_sets), | |
284 | .sets = qt2410_nand_sets, | |
285 | }; | |
286 | ||
287 | /* UDC */ | |
288 | ||
289 | static struct s3c2410_udc_mach_info qt2410_udc_cfg = { | |
290 | }; | |
291 | ||
292 | static char tft_type = 's'; | |
293 | ||
294 | static int __init qt2410_tft_setup(char *str) | |
295 | { | |
296 | tft_type = str[0]; | |
297 | return 1; | |
298 | } | |
299 | ||
300 | __setup("tft=", qt2410_tft_setup); | |
301 | ||
302 | static void __init qt2410_map_io(void) | |
303 | { | |
304 | s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); | |
305 | s3c24xx_init_clocks(12*1000*1000); | |
306 | s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); | |
c6184e27 BD |
307 | } |
308 | ||
309 | static void __init qt2410_machine_init(void) | |
310 | { | |
2a3a1804 | 311 | s3c_nand_set_platdata(&qt2410_nand_info); |
c6184e27 BD |
312 | |
313 | switch (tft_type) { | |
314 | case 'p': /* production */ | |
09fe75f6 | 315 | qt2410_fb_info.default_display = 1; |
c6184e27 BD |
316 | break; |
317 | case 'b': /* big */ | |
09fe75f6 | 318 | qt2410_fb_info.default_display = 0; |
c6184e27 BD |
319 | break; |
320 | case 's': /* small */ | |
321 | default: | |
09fe75f6 | 322 | qt2410_fb_info.default_display = 2; |
c6184e27 BD |
323 | break; |
324 | } | |
09fe75f6 | 325 | s3c24xx_fb_set_platdata(&qt2410_fb_info); |
c6184e27 | 326 | |
5c9fb56b SN |
327 | /* set initial state of the LED GPIO */ |
328 | WARN_ON(gpio_request_one(S3C2410_GPB(0), GPIOF_OUT_INIT_HIGH, NULL)); | |
329 | gpio_free(S3C2410_GPB(0)); | |
c6184e27 BD |
330 | |
331 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); | |
3e1b776c | 332 | s3c_i2c0_set_platdata(NULL); |
c6184e27 | 333 | |
2d2e0c89 BD |
334 | WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs")); |
335 | gpio_direction_output(S3C2410_GPB(5), 1); | |
c6184e27 | 336 | |
57e5171c | 337 | platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); |
4e59c25d | 338 | s3c_pm_init(); |
c6184e27 BD |
339 | } |
340 | ||
341 | MACHINE_START(QT2410, "QT2410") | |
69d50710 | 342 | .atag_offset = 0x100, |
c6184e27 BD |
343 | .map_io = qt2410_map_io, |
344 | .init_irq = s3c24xx_init_irq, | |
345 | .init_machine = qt2410_machine_init, | |
346 | .timer = &s3c24xx_timer, | |
b27b0727 | 347 | .restart = s3c2410_restart, |
c6184e27 | 348 | MACHINE_END |