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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/pm.c |
2 | * | |
a21765a7 | 3 | * Copyright (c) 2006 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
a21765a7 | 6 | * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
21 | */ |
22 | ||
1da177e4 LT |
23 | #include <linux/init.h> |
24 | #include <linux/suspend.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/time.h> | |
4a858cfc | 27 | #include <linux/device.h> |
bb072c3c | 28 | #include <linux/syscore_ops.h> |
ec976d6e | 29 | #include <linux/gpio.h> |
fced80c7 | 30 | #include <linux/io.h> |
1da177e4 | 31 | |
a21765a7 | 32 | #include <asm/mach-types.h> |
1da177e4 | 33 | |
232910d6 | 34 | #include <mach/hardware.h> |
a09e64fb | 35 | #include <mach/regs-gpio.h> |
b0161caa | 36 | #include <mach/gpio-samsung.h> |
1da177e4 | 37 | |
36437412 | 38 | #include <plat/gpio-cfg.h> |
a2b7ba9c BD |
39 | #include <plat/cpu.h> |
40 | #include <plat/pm.h> | |
1da177e4 | 41 | |
232910d6 KK |
42 | #include "h1940.h" |
43 | ||
a21765a7 | 44 | static void s3c2410_pm_prepare(void) |
1da177e4 | 45 | { |
a21765a7 | 46 | /* ensure at least GSTATUS3 has the resume address */ |
1da177e4 | 47 | |
ef30e144 | 48 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); |
1da177e4 | 49 | |
6419711a BD |
50 | S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); |
51 | S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); | |
1da177e4 | 52 | |
a21765a7 BD |
53 | if (machine_is_h1940()) { |
54 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); | |
55 | unsigned long ptr; | |
56 | unsigned long calc = 0; | |
1da177e4 | 57 | |
a21765a7 | 58 | /* generate check for the bootloader to check on resume */ |
1da177e4 | 59 | |
a21765a7 BD |
60 | for (ptr = 0; ptr < 0x40000; ptr += 0x400) |
61 | calc += __raw_readl(base+ptr); | |
1da177e4 | 62 | |
a21765a7 | 63 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); |
1da177e4 LT |
64 | } |
65 | ||
0741b7d2 | 66 | /* RX3715 and RX1950 use similar to H1940 code and the |
a21765a7 | 67 | * same offsets for resume and checksum pointers */ |
1da177e4 | 68 | |
0741b7d2 | 69 | if (machine_is_rx3715() || machine_is_rx1950()) { |
a21765a7 BD |
70 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); |
71 | unsigned long ptr; | |
72 | unsigned long calc = 0; | |
1da177e4 | 73 | |
a21765a7 | 74 | /* generate check for the bootloader to check on resume */ |
1da177e4 | 75 | |
a21765a7 BD |
76 | for (ptr = 0; ptr < 0x40000; ptr += 0x4) |
77 | calc += __raw_readl(base+ptr); | |
1da177e4 | 78 | |
a21765a7 | 79 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); |
1da177e4 LT |
80 | } |
81 | ||
94911735 SN |
82 | if (machine_is_aml_m5900()) { |
83 | gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL); | |
84 | gpio_free(S3C2410_GPF(2)); | |
85 | } | |
1da177e4 | 86 | |
192ff91f VK |
87 | if (machine_is_rx1950()) { |
88 | /* According to S3C2442 user's manual, page 7-17, | |
89 | * when the system is operating in NAND boot mode, | |
90 | * the hardware pin configuration - EINT[23:21] – | |
91 | * must be set as input for starting up after | |
92 | * wakeup from sleep mode | |
93 | */ | |
94 | s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT); | |
95 | s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT); | |
96 | s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT); | |
97 | } | |
1da177e4 LT |
98 | } |
99 | ||
bb072c3c | 100 | static void s3c2410_pm_resume(void) |
1da177e4 | 101 | { |
a21765a7 | 102 | unsigned long tmp; |
1da177e4 | 103 | |
a21765a7 | 104 | /* unset the return-from-sleep flag, to ensure reset */ |
1da177e4 | 105 | |
a21765a7 BD |
106 | tmp = __raw_readl(S3C2410_GSTATUS2); |
107 | tmp &= S3C2410_GSTATUS2_OFFRESET; | |
108 | __raw_writel(tmp, S3C2410_GSTATUS2); | |
1da177e4 | 109 | |
94911735 SN |
110 | if (machine_is_aml_m5900()) { |
111 | gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL); | |
112 | gpio_free(S3C2410_GPF(2)); | |
113 | } | |
1da177e4 LT |
114 | } |
115 | ||
bb072c3c RW |
116 | struct syscore_ops s3c2410_pm_syscore_ops = { |
117 | .resume = s3c2410_pm_resume, | |
118 | }; | |
119 | ||
04511a6f | 120 | static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif) |
1da177e4 | 121 | { |
a21765a7 BD |
122 | pm_cpu_prep = s3c2410_pm_prepare; |
123 | pm_cpu_sleep = s3c2410_cpu_suspend; | |
1da177e4 | 124 | |
a21765a7 | 125 | return 0; |
1da177e4 LT |
126 | } |
127 | ||
a21765a7 | 128 | #if defined(CONFIG_CPU_S3C2410) |
4a858cfc KS |
129 | static struct subsys_interface s3c2410_pm_interface = { |
130 | .name = "s3c2410_pm", | |
131 | .subsys = &s3c2410_subsys, | |
132 | .add_dev = s3c2410_pm_add, | |
a21765a7 | 133 | }; |
1da177e4 | 134 | |
a21765a7 | 135 | /* register ourselves */ |
1da177e4 | 136 | |
a21765a7 | 137 | static int __init s3c2410_pm_drvinit(void) |
1da177e4 | 138 | { |
4a858cfc | 139 | return subsys_interface_register(&s3c2410_pm_interface); |
1da177e4 LT |
140 | } |
141 | ||
a21765a7 | 142 | arch_initcall(s3c2410_pm_drvinit); |
f0176794 | 143 | |
4a858cfc KS |
144 | static struct subsys_interface s3c2410a_pm_interface = { |
145 | .name = "s3c2410a_pm", | |
ea04018e | 146 | .subsys = &s3c2410a_subsys, |
4a858cfc | 147 | .add_dev = s3c2410_pm_add, |
f0176794 BD |
148 | }; |
149 | ||
150 | static int __init s3c2410a_pm_drvinit(void) | |
151 | { | |
4a858cfc | 152 | return subsys_interface_register(&s3c2410a_pm_interface); |
f0176794 BD |
153 | } |
154 | ||
155 | arch_initcall(s3c2410a_pm_drvinit); | |
a21765a7 | 156 | #endif |
1da177e4 | 157 | |
a21765a7 | 158 | #if defined(CONFIG_CPU_S3C2440) |
4a858cfc KS |
159 | static struct subsys_interface s3c2440_pm_interface = { |
160 | .name = "s3c2440_pm", | |
161 | .subsys = &s3c2440_subsys, | |
162 | .add_dev = s3c2410_pm_add, | |
a21765a7 | 163 | }; |
1da177e4 | 164 | |
a21765a7 | 165 | static int __init s3c2440_pm_drvinit(void) |
1da177e4 | 166 | { |
4a858cfc | 167 | return subsys_interface_register(&s3c2440_pm_interface); |
1da177e4 LT |
168 | } |
169 | ||
a21765a7 BD |
170 | arch_initcall(s3c2440_pm_drvinit); |
171 | #endif | |
1da177e4 | 172 | |
a21765a7 | 173 | #if defined(CONFIG_CPU_S3C2442) |
4a858cfc KS |
174 | static struct subsys_interface s3c2442_pm_interface = { |
175 | .name = "s3c2442_pm", | |
176 | .subsys = &s3c2442_subsys, | |
177 | .add_dev = s3c2410_pm_add, | |
1da177e4 LT |
178 | }; |
179 | ||
a21765a7 | 180 | static int __init s3c2442_pm_drvinit(void) |
1da177e4 | 181 | { |
4a858cfc | 182 | return subsys_interface_register(&s3c2442_pm_interface); |
1da177e4 | 183 | } |
a21765a7 BD |
184 | |
185 | arch_initcall(s3c2442_pm_drvinit); | |
186 | #endif |