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1 | /* linux/arch/arm/plat-s3c24xx/pm.c |
2 | * | |
ccae941e | 3 | * Copyright (c) 2004-2006 Simtec Electronics |
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4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C24XX Power Manager (Suspend-To-RAM) support | |
7 | * | |
8 | * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Parts based on arch/arm/mach-pxa/pm.c | |
25 | * | |
26 | * Thanks to Dimitry Andric for debugging | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/suspend.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/time.h> | |
ec976d6e | 33 | #include <linux/gpio.h> |
a21765a7 | 34 | #include <linux/interrupt.h> |
a21765a7 | 35 | #include <linux/serial_core.h> |
fced80c7 | 36 | #include <linux/io.h> |
c67d0f29 | 37 | #include <linux/platform_data/gpio-samsung-s3c24xx.h> |
a21765a7 | 38 | |
a2b7ba9c | 39 | #include <plat/regs-serial.h> |
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40 | #include <mach/regs-clock.h> |
41 | #include <mach/regs-gpio.h> | |
a09e64fb | 42 | #include <mach/regs-irq.h> |
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43 | |
44 | #include <asm/mach/time.h> | |
45 | ||
40b956f0 | 46 | #include <plat/gpio-cfg.h> |
a2b7ba9c | 47 | #include <plat/pm.h> |
a21765a7 | 48 | |
37c3adca KK |
49 | #include "regs-mem.h" |
50 | ||
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51 | #define PFX "s3c24xx-pm: " |
52 | ||
53 | static struct sleep_save core_save[] = { | |
54 | SAVE_ITEM(S3C2410_LOCKTIME), | |
55 | SAVE_ITEM(S3C2410_CLKCON), | |
56 | ||
57 | /* we restore the timings here, with the proviso that the board | |
58 | * brings the system up in an slower, or equal frequency setting | |
59 | * to the original system. | |
60 | * | |
61 | * if we cannot guarantee this, then things are going to go very | |
62 | * wrong here, as we modify the refresh and both pll settings. | |
63 | */ | |
64 | ||
65 | SAVE_ITEM(S3C2410_BWSCON), | |
66 | SAVE_ITEM(S3C2410_BANKCON0), | |
67 | SAVE_ITEM(S3C2410_BANKCON1), | |
68 | SAVE_ITEM(S3C2410_BANKCON2), | |
69 | SAVE_ITEM(S3C2410_BANKCON3), | |
70 | SAVE_ITEM(S3C2410_BANKCON4), | |
71 | SAVE_ITEM(S3C2410_BANKCON5), | |
72 | ||
e425382e | 73 | #ifndef CONFIG_CPU_FREQ |
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74 | SAVE_ITEM(S3C2410_CLKDIVN), |
75 | SAVE_ITEM(S3C2410_MPLLCON), | |
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76 | SAVE_ITEM(S3C2410_REFRESH), |
77 | #endif | |
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78 | SAVE_ITEM(S3C2410_UPLLCON), |
79 | SAVE_ITEM(S3C2410_CLKSLOW), | |
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80 | }; |
81 | ||
62feee64 | 82 | static struct sleep_save misc_save[] = { |
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83 | SAVE_ITEM(S3C2410_DCLKCON), |
84 | }; | |
85 | ||
549c7e33 | 86 | /* s3c_pm_check_resume_pin |
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87 | * |
88 | * check to see if the pin is configured correctly for sleep mode, and | |
89 | * make any necessary adjustments if it is not | |
90 | */ | |
91 | ||
549c7e33 | 92 | static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) |
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93 | { |
94 | unsigned long irqstate; | |
95 | unsigned long pinstate; | |
5690a626 | 96 | int irq = gpio_to_irq(pin); |
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97 | |
98 | if (irqoffs < 4) | |
99 | irqstate = s3c_irqwake_intmask & (1L<<irqoffs); | |
100 | else | |
101 | irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); | |
102 | ||
9933847b | 103 | pinstate = s3c_gpio_getcfg(pin); |
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104 | |
105 | if (!irqstate) { | |
106 | if (pinstate == S3C2410_GPIO_IRQ) | |
9933847b | 107 | S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin); |
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108 | } else { |
109 | if (pinstate == S3C2410_GPIO_IRQ) { | |
6419711a | 110 | S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); |
40b956f0 | 111 | s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); |
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112 | } |
113 | } | |
114 | } | |
115 | ||
2261e0e6 | 116 | /* s3c_pm_configure_extint |
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117 | * |
118 | * configure all external interrupt pins | |
119 | */ | |
120 | ||
2261e0e6 | 121 | void s3c_pm_configure_extint(void) |
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122 | { |
123 | int pin; | |
124 | ||
125 | /* for each of the external interrupts (EINT0..EINT15) we | |
48fc7f7e | 126 | * need to check whether it is an external interrupt source, |
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127 | * and then configure it as an input if it is not |
128 | */ | |
129 | ||
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130 | for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) { |
131 | s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0)); | |
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132 | } |
133 | ||
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134 | for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) { |
135 | s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8); | |
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136 | } |
137 | } | |
138 | ||
62feee64 | 139 | |
2261e0e6 | 140 | void s3c_pm_restore_core(void) |
a21765a7 | 141 | { |
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142 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); |
143 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | |
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144 | } |
145 | ||
2261e0e6 | 146 | void s3c_pm_save_core(void) |
a21765a7 | 147 | { |
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148 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); |
149 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | |
a21765a7 | 150 | } |
2261e0e6 | 151 |