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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/s3c2410.c |
2 | * | |
3 | * Copyright (c) 2003-2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * http://www.simtec.co.uk/products/EB2410ITX/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
1da177e4 LT |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
1ec7269f | 19 | #include <linux/gpio.h> |
e425382e | 20 | #include <linux/clk.h> |
4a858cfc | 21 | #include <linux/device.h> |
bb072c3c | 22 | #include <linux/syscore_ops.h> |
b6d1f542 | 23 | #include <linux/serial_core.h> |
334a1c70 | 24 | #include <linux/serial_s3c.h> |
d052d1be | 25 | #include <linux/platform_device.h> |
7b6d864b | 26 | #include <linux/reboot.h> |
fced80c7 | 27 | #include <linux/io.h> |
1da177e4 LT |
28 | |
29 | #include <asm/mach/arch.h> | |
30 | #include <asm/mach/map.h> | |
31 | #include <asm/mach/irq.h> | |
32 | ||
a09e64fb | 33 | #include <mach/hardware.h> |
b0161caa | 34 | #include <mach/gpio-samsung.h> |
1da177e4 | 35 | #include <asm/irq.h> |
9f97da78 | 36 | #include <asm/system_misc.h> |
1da177e4 | 37 | |
e425382e BD |
38 | #include <plat/cpu-freq.h> |
39 | ||
a09e64fb | 40 | #include <mach/regs-clock.h> |
1da177e4 | 41 | |
a2b7ba9c BD |
42 | #include <plat/cpu.h> |
43 | #include <plat/devs.h> | |
bb072c3c | 44 | #include <plat/pm.h> |
1da177e4 | 45 | |
1ec7269f BD |
46 | #include <plat/gpio-core.h> |
47 | #include <plat/gpio-cfg.h> | |
48 | #include <plat/gpio-cfg-helpers.h> | |
49 | ||
d8fdec16 HS |
50 | #include "common.h" |
51 | ||
1da177e4 LT |
52 | /* Initial IO mappings */ |
53 | ||
54 | static struct map_desc s3c2410_iodesc[] __initdata = { | |
1da177e4 | 55 | IODESC_ENT(CLKPWR), |
1da177e4 | 56 | IODESC_ENT(TIMER), |
62ee914e | 57 | IODESC_ENT(WATCHDOG), |
1da177e4 LT |
58 | }; |
59 | ||
1da177e4 LT |
60 | /* our uart devices */ |
61 | ||
1da177e4 LT |
62 | /* uart registration process */ |
63 | ||
64 | void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
65 | { | |
66a9b49a | 66 | s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no); |
1da177e4 LT |
67 | } |
68 | ||
69 | /* s3c2410_map_io | |
70 | * | |
71 | * register the standard cpu IO areas, and any passed in from the | |
72 | * machine specific initialisation. | |
73 | */ | |
74 | ||
74b265d4 | 75 | void __init s3c2410_map_io(void) |
1da177e4 | 76 | { |
782d8a3c KK |
77 | s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; |
78 | s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; | |
1ec7269f | 79 | |
1da177e4 | 80 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); |
1da177e4 LT |
81 | } |
82 | ||
4a858cfc | 83 | struct bus_type s3c2410_subsys = { |
af5ca3f4 | 84 | .name = "s3c2410-core", |
4a858cfc | 85 | .dev_name = "s3c2410-core", |
a341305e BD |
86 | }; |
87 | ||
f0176794 | 88 | /* Note, we would have liked to name this s3c2410-core, but we cannot |
4a858cfc | 89 | * register two subsystems with the same name. |
f0176794 | 90 | */ |
4a858cfc | 91 | struct bus_type s3c2410a_subsys = { |
f0176794 | 92 | .name = "s3c2410a-core", |
4a858cfc | 93 | .dev_name = "s3c2410a-core", |
f0176794 BD |
94 | }; |
95 | ||
4a858cfc KS |
96 | static struct device s3c2410_dev = { |
97 | .bus = &s3c2410_subsys, | |
a341305e BD |
98 | }; |
99 | ||
4a858cfc | 100 | /* need to register the subsystem before we actually register the device, and |
a341305e | 101 | * we also need to ensure that it has been initialised before any of the |
6db3eee4 | 102 | * drivers even try to use it (even if not on an s3c2410 based system) |
a341305e BD |
103 | * as a driver which may support both 2410 and 2440 may try and use it. |
104 | */ | |
105 | ||
106 | static int __init s3c2410_core_init(void) | |
107 | { | |
4a858cfc | 108 | return subsys_system_register(&s3c2410_subsys, NULL); |
a341305e BD |
109 | } |
110 | ||
111 | core_initcall(s3c2410_core_init); | |
112 | ||
f0176794 BD |
113 | static int __init s3c2410a_core_init(void) |
114 | { | |
4a858cfc | 115 | return subsys_system_register(&s3c2410a_subsys, NULL); |
f0176794 BD |
116 | } |
117 | ||
118 | core_initcall(s3c2410a_core_init); | |
119 | ||
1da177e4 LT |
120 | int __init s3c2410_init(void) |
121 | { | |
122 | printk("S3C2410: Initialising architecture\n"); | |
123 | ||
4f506daf | 124 | #ifdef CONFIG_PM_SLEEP |
bb072c3c RW |
125 | register_syscore_ops(&s3c2410_pm_syscore_ops); |
126 | register_syscore_ops(&s3c24xx_irq_syscore_ops); | |
d8fdec16 | 127 | #endif |
bb072c3c | 128 | |
4a858cfc | 129 | return device_register(&s3c2410_dev); |
1da177e4 | 130 | } |
f0176794 BD |
131 | |
132 | int __init s3c2410a_init(void) | |
133 | { | |
4a858cfc | 134 | s3c2410_dev.bus = &s3c2410a_subsys; |
f0176794 BD |
135 | return s3c2410_init(); |
136 | } |