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fd4e5a5b | 1 | /* |
68d9ab39 BD |
2 | * Copyright (c) 2006 Simtec Electronics |
3 | * Ben Dooks <ben@simtec.co.uk> | |
4 | * | |
5 | * http://armlinux.simtec.co.uk/. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
68d9ab39 BD |
10 | */ |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/timer.h> | |
17 | #include <linux/init.h> | |
e425382e | 18 | #include <linux/clk.h> |
eca8c242 | 19 | #include <linux/delay.h> |
4a858cfc | 20 | #include <linux/device.h> |
bb072c3c | 21 | #include <linux/syscore_ops.h> |
b6d1f542 | 22 | #include <linux/serial_core.h> |
68d9ab39 | 23 | #include <linux/platform_device.h> |
fced80c7 | 24 | #include <linux/io.h> |
68d9ab39 BD |
25 | |
26 | #include <asm/mach/arch.h> | |
27 | #include <asm/mach/map.h> | |
28 | #include <asm/mach/irq.h> | |
29 | ||
c84cbb24 | 30 | #include <asm/proc-fns.h> |
68d9ab39 | 31 | #include <asm/irq.h> |
9f97da78 | 32 | #include <asm/system_misc.h> |
68d9ab39 | 33 | |
fd4e5a5b | 34 | #include <mach/hardware.h> |
a09e64fb | 35 | #include <mach/regs-clock.h> |
fd4e5a5b | 36 | #include <mach/regs-gpio.h> |
68d9ab39 | 37 | |
fd4e5a5b | 38 | #include <plat/clock.h> |
a2b7ba9c | 39 | #include <plat/cpu.h> |
fd4e5a5b | 40 | #include <plat/cpu-freq.h> |
a2b7ba9c | 41 | #include <plat/devs.h> |
ef3f2dd4 | 42 | #include <plat/nand-core.h> |
fd4e5a5b KK |
43 | #include <plat/pll.h> |
44 | #include <plat/pm.h> | |
45 | #include <plat/regs-serial.h> | |
46 | #include <plat/regs-spi.h> | |
fd4e5a5b | 47 | |
d8fdec16 | 48 | #include "common.h" |
b4353784 | 49 | #include "regs-dsc.h" |
14cce0e7 | 50 | #include "s3c2412-power.h" |
b4353784 | 51 | |
fd4e5a5b KK |
52 | #define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) |
53 | #define S3C2412_SWRST_RESET (0x533C2412) | |
68d9ab39 BD |
54 | |
55 | #ifndef CONFIG_CPU_S3C2412_ONLY | |
56 | void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; | |
50dedf16 BD |
57 | |
58 | static inline void s3c2412_init_gpio2(void) | |
59 | { | |
60 | s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10; | |
61 | } | |
62 | #else | |
63 | #define s3c2412_init_gpio2() do { } while(0) | |
68d9ab39 BD |
64 | #endif |
65 | ||
66 | /* Initial IO mappings */ | |
67 | ||
68 | static struct map_desc s3c2412_iodesc[] __initdata = { | |
69 | IODESC_ENT(CLKPWR), | |
68d9ab39 | 70 | IODESC_ENT(TIMER), |
68d9ab39 | 71 | IODESC_ENT(WATCHDOG), |
25400036 BD |
72 | { |
73 | .virtual = (unsigned long)S3C2412_VA_SSMC, | |
74 | .pfn = __phys_to_pfn(S3C2412_PA_SSMC), | |
75 | .length = SZ_1M, | |
76 | .type = MT_DEVICE, | |
77 | }, | |
78 | { | |
79 | .virtual = (unsigned long)S3C2412_VA_EBI, | |
80 | .pfn = __phys_to_pfn(S3C2412_PA_EBI), | |
81 | .length = SZ_1M, | |
82 | .type = MT_DEVICE, | |
83 | }, | |
68d9ab39 BD |
84 | }; |
85 | ||
86 | /* uart registration process */ | |
87 | ||
88 | void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
89 | { | |
90 | s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no); | |
91 | ||
92 | /* rename devices that are s3c2412/s3c2413 specific */ | |
93 | s3c_device_sdi.name = "s3c2412-sdi"; | |
72d70d06 | 94 | s3c_device_lcd.name = "s3c2412-lcd"; |
ef3f2dd4 | 95 | s3c_nand_setname("s3c2412-nand"); |
e903382c | 96 | |
f3fb5a55 BD |
97 | /* alter IRQ of SDI controller */ |
98 | ||
99 | s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI; | |
100 | s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI; | |
101 | ||
e903382c SSP |
102 | /* spi channel related changes, s3c2412/13 specific */ |
103 | s3c_device_spi0.name = "s3c2412-spi"; | |
104 | s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24; | |
105 | s3c_device_spi1.name = "s3c2412-spi"; | |
106 | s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1; | |
107 | s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24; | |
108 | ||
68d9ab39 BD |
109 | } |
110 | ||
c84cbb24 BD |
111 | /* s3c2412_idle |
112 | * | |
113 | * use the standard idle call by ensuring the idle mode | |
114 | * in power config, then issuing the idle co-processor | |
115 | * instruction | |
116 | */ | |
117 | ||
118 | static void s3c2412_idle(void) | |
119 | { | |
120 | unsigned long tmp; | |
121 | ||
122 | /* ensure our idle mode is to go to idle */ | |
123 | ||
124 | tmp = __raw_readl(S3C2412_PWRCFG); | |
125 | tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK; | |
126 | tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; | |
127 | __raw_writel(tmp, S3C2412_PWRCFG); | |
128 | ||
129 | cpu_do_idle(); | |
130 | } | |
131 | ||
57538975 | 132 | void s3c2412_restart(char mode, const char *cmd) |
eca8c242 | 133 | { |
57538975 HS |
134 | if (mode == 's') |
135 | soft_restart(0); | |
136 | ||
eca8c242 BD |
137 | /* errata "Watch-dog/Software Reset Problem" specifies that |
138 | * this reset must be done with the SYSCLK sourced from | |
139 | * EXTCLK instead of FOUT to avoid a glitch in the reset | |
140 | * mechanism. | |
141 | * | |
142 | * See the watchdog section of the S3C2412 manual for more | |
143 | * information on this fix. | |
144 | */ | |
145 | ||
146 | __raw_writel(0x00, S3C2412_CLKSRC); | |
147 | __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST); | |
148 | ||
149 | mdelay(1); | |
150 | } | |
151 | ||
68d9ab39 BD |
152 | /* s3c2412_map_io |
153 | * | |
154 | * register the standard cpu IO areas, and any passed in from the | |
155 | * machine specific initialisation. | |
156 | */ | |
157 | ||
74b265d4 | 158 | void __init s3c2412_map_io(void) |
68d9ab39 BD |
159 | { |
160 | /* move base of IO */ | |
161 | ||
50dedf16 | 162 | s3c2412_init_gpio2(); |
68d9ab39 | 163 | |
c84cbb24 BD |
164 | /* set our idle function */ |
165 | ||
92311272 | 166 | arm_pm_idle = s3c2412_idle; |
c84cbb24 | 167 | |
68d9ab39 BD |
168 | /* register our io-tables */ |
169 | ||
170 | iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); | |
68d9ab39 BD |
171 | } |
172 | ||
e425382e | 173 | void __init_or_cpufreq s3c2412_setup_clocks(void) |
68d9ab39 | 174 | { |
e425382e | 175 | struct clk *xtal_clk; |
68d9ab39 | 176 | unsigned long tmp; |
e425382e | 177 | unsigned long xtal; |
68d9ab39 BD |
178 | unsigned long fclk; |
179 | unsigned long hclk; | |
180 | unsigned long pclk; | |
181 | ||
e425382e BD |
182 | xtal_clk = clk_get(NULL, "xtal"); |
183 | xtal = clk_get_rate(xtal_clk); | |
184 | clk_put(xtal_clk); | |
185 | ||
68d9ab39 BD |
186 | /* now we've got our machine bits initialised, work out what |
187 | * clocks we've got */ | |
188 | ||
e425382e | 189 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); |
68d9ab39 | 190 | |
cca851d7 BD |
191 | clk_mpll.rate = fclk; |
192 | ||
68d9ab39 BD |
193 | tmp = __raw_readl(S3C2410_CLKDIVN); |
194 | ||
195 | /* work out clock scalings */ | |
196 | ||
197 | hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); | |
1017be88 | 198 | hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); |
68d9ab39 BD |
199 | pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); |
200 | ||
201 | /* print brieft summary of clocks, etc */ | |
202 | ||
203 | printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | |
204 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | |
205 | ||
e425382e BD |
206 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
207 | } | |
208 | ||
209 | void __init s3c2412_init_clocks(int xtal) | |
210 | { | |
68d9ab39 BD |
211 | /* initialise the clocks here, to allow other things like the |
212 | * console to use them | |
213 | */ | |
214 | ||
e425382e BD |
215 | s3c24xx_register_baseclocks(xtal); |
216 | s3c2412_setup_clocks(); | |
68d9ab39 BD |
217 | s3c2412_baseclk_add(); |
218 | } | |
219 | ||
4a858cfc | 220 | /* need to register the subsystem before we actually register the device, and |
68d9ab39 BD |
221 | * we also need to ensure that it has been initialised before any of the |
222 | * drivers even try to use it (even if not on an s3c2412 based system) | |
223 | * as a driver which may support both 2410 and 2440 may try and use it. | |
224 | */ | |
225 | ||
4a858cfc | 226 | struct bus_type s3c2412_subsys = { |
af5ca3f4 | 227 | .name = "s3c2412-core", |
4a858cfc | 228 | .dev_name = "s3c2412-core", |
68d9ab39 BD |
229 | }; |
230 | ||
231 | static int __init s3c2412_core_init(void) | |
232 | { | |
4a858cfc | 233 | return subsys_system_register(&s3c2412_subsys, NULL); |
68d9ab39 BD |
234 | } |
235 | ||
236 | core_initcall(s3c2412_core_init); | |
237 | ||
4a858cfc KS |
238 | static struct device s3c2412_dev = { |
239 | .bus = &s3c2412_subsys, | |
68d9ab39 BD |
240 | }; |
241 | ||
242 | int __init s3c2412_init(void) | |
243 | { | |
244 | printk("S3C2412: Initialising architecture\n"); | |
245 | ||
fb630b9f | 246 | #ifdef CONFIG_PM |
bb072c3c RW |
247 | register_syscore_ops(&s3c2412_pm_syscore_ops); |
248 | register_syscore_ops(&s3c24xx_irq_syscore_ops); | |
d8fdec16 | 249 | #endif |
bb072c3c | 250 | |
4a858cfc | 251 | return device_register(&s3c2412_dev); |
68d9ab39 | 252 | } |