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a21765a7 | 1 | /* linux/arch/arm/plat-s3c24xx/s3c244x.c |
96ce2385 BD |
2 | * |
3 | * Copyright (c) 2004-2006 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
e4d06e39 | 6 | * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443) |
96ce2385 BD |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
b6d1f542 | 19 | #include <linux/serial_core.h> |
334a1c70 | 20 | #include <linux/serial_s3c.h> |
96ce2385 | 21 | #include <linux/platform_device.h> |
7b6d864b | 22 | #include <linux/reboot.h> |
4a858cfc | 23 | #include <linux/device.h> |
bb072c3c | 24 | #include <linux/syscore_ops.h> |
96ce2385 | 25 | #include <linux/clk.h> |
fced80c7 | 26 | #include <linux/io.h> |
96ce2385 | 27 | |
9f97da78 | 28 | #include <asm/system_misc.h> |
96ce2385 BD |
29 | #include <asm/mach/arch.h> |
30 | #include <asm/mach/map.h> | |
31 | #include <asm/mach/irq.h> | |
32 | ||
a09e64fb | 33 | #include <mach/hardware.h> |
96ce2385 BD |
34 | #include <asm/irq.h> |
35 | ||
e425382e BD |
36 | #include <plat/cpu-freq.h> |
37 | ||
a09e64fb | 38 | #include <mach/regs-clock.h> |
a09e64fb | 39 | #include <mach/regs-gpio.h> |
96ce2385 | 40 | |
d5120ae7 | 41 | #include <plat/clock.h> |
a2b7ba9c BD |
42 | #include <plat/devs.h> |
43 | #include <plat/cpu.h> | |
44 | #include <plat/pm.h> | |
e24b864a | 45 | #include <plat/pll.h> |
ef3f2dd4 | 46 | #include <plat/nand-core.h> |
c1ba544f | 47 | #include <plat/watchdog-reset.h> |
96ce2385 | 48 | |
51cb1289 | 49 | #include "common.h" |
b4353784 KK |
50 | #include "regs-dsc.h" |
51 | ||
96ce2385 BD |
52 | static struct map_desc s3c244x_iodesc[] __initdata = { |
53 | IODESC_ENT(CLKPWR), | |
54 | IODESC_ENT(TIMER), | |
55 | IODESC_ENT(WATCHDOG), | |
96ce2385 BD |
56 | }; |
57 | ||
58 | /* uart initialisation */ | |
59 | ||
60 | void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
61 | { | |
62 | s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); | |
63 | } | |
64 | ||
74b265d4 | 65 | void __init s3c244x_map_io(void) |
96ce2385 BD |
66 | { |
67 | /* register our io-tables */ | |
68 | ||
69 | iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc)); | |
96ce2385 BD |
70 | |
71 | /* rename any peripherals used differing from the s3c2410 */ | |
72 | ||
90239bbd | 73 | s3c_device_sdi.name = "s3c2440-sdi"; |
3e1b776c | 74 | s3c_device_i2c0.name = "s3c2440-i2c"; |
ef3f2dd4 | 75 | s3c_nand_setname("s3c2440-nand"); |
ce8877b5 | 76 | s3c_device_ts.name = "s3c2440-ts"; |
b8ccca4a | 77 | s3c_device_usbgadget.name = "s3c2440-usbgadget"; |
51cb1289 | 78 | s3c2410_device_dclk.name = "s3c2440-dclk"; |
96ce2385 BD |
79 | } |
80 | ||
4659c534 HS |
81 | void __init_or_cpufreq s3c244x_setup_clocks(void) |
82 | { | |
83 | } | |
96ce2385 | 84 | |
4a858cfc | 85 | /* Since the S3C2442 and S3C2440 share items, put both subsystems here */ |
96ce2385 | 86 | |
4a858cfc | 87 | struct bus_type s3c2440_subsys = { |
af5ca3f4 | 88 | .name = "s3c2440-core", |
4a858cfc | 89 | .dev_name = "s3c2440-core", |
96ce2385 BD |
90 | }; |
91 | ||
4a858cfc | 92 | struct bus_type s3c2442_subsys = { |
af5ca3f4 | 93 | .name = "s3c2442-core", |
4a858cfc | 94 | .dev_name = "s3c2442-core", |
96ce2385 BD |
95 | }; |
96 | ||
4a858cfc | 97 | /* need to register the subsystem before we actually register the device, and |
96ce2385 BD |
98 | * we also need to ensure that it has been initialised before any of the |
99 | * drivers even try to use it (even if not on an s3c2440 based system) | |
100 | * as a driver which may support both 2410 and 2440 may try and use it. | |
101 | */ | |
102 | ||
103 | static int __init s3c2440_core_init(void) | |
104 | { | |
4a858cfc | 105 | return subsys_system_register(&s3c2440_subsys, NULL); |
96ce2385 BD |
106 | } |
107 | ||
108 | core_initcall(s3c2440_core_init); | |
109 | ||
110 | static int __init s3c2442_core_init(void) | |
111 | { | |
4a858cfc | 112 | return subsys_system_register(&s3c2442_subsys, NULL); |
96ce2385 BD |
113 | } |
114 | ||
115 | core_initcall(s3c2442_core_init); | |
bb072c3c RW |
116 | |
117 | ||
118 | #ifdef CONFIG_PM | |
119 | static struct sleep_save s3c244x_sleep[] = { | |
120 | SAVE_ITEM(S3C2440_DSC0), | |
121 | SAVE_ITEM(S3C2440_DSC1), | |
122 | SAVE_ITEM(S3C2440_GPJDAT), | |
123 | SAVE_ITEM(S3C2440_GPJCON), | |
124 | SAVE_ITEM(S3C2440_GPJUP) | |
125 | }; | |
126 | ||
127 | static int s3c244x_suspend(void) | |
128 | { | |
129 | s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); | |
130 | return 0; | |
131 | } | |
132 | ||
133 | static void s3c244x_resume(void) | |
134 | { | |
135 | s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); | |
136 | } | |
137 | #else | |
138 | #define s3c244x_suspend NULL | |
139 | #define s3c244x_resume NULL | |
140 | #endif | |
141 | ||
142 | struct syscore_ops s3c244x_pm_syscore_ops = { | |
143 | .suspend = s3c244x_suspend, | |
144 | .resume = s3c244x_resume, | |
145 | }; | |
c1ba544f | 146 | |
7b6d864b | 147 | void s3c244x_restart(enum reboot_mode mode, const char *cmd) |
c1ba544f | 148 | { |
7b6d864b | 149 | if (mode == REBOOT_SOFT) |
c1ba544f HS |
150 | soft_restart(0); |
151 | ||
88f59738 | 152 | samsung_wdt_reset(); |
c1ba544f HS |
153 | |
154 | /* we'll take a jump through zero as a poor second */ | |
155 | soft_restart(0); | |
48546cc0 | 156 | } |