Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-s3c24xx / s3c244x.c
CommitLineData
a21765a7 1/* linux/arch/arm/plat-s3c24xx/s3c244x.c
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2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
e4d06e39 6 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
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7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
b6d1f542 19#include <linux/serial_core.h>
96ce2385 20#include <linux/platform_device.h>
4a858cfc 21#include <linux/device.h>
bb072c3c 22#include <linux/syscore_ops.h>
96ce2385 23#include <linux/clk.h>
fced80c7 24#include <linux/io.h>
96ce2385 25
9f97da78 26#include <asm/system_misc.h>
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27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
a09e64fb 31#include <mach/hardware.h>
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32#include <asm/irq.h>
33
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34#include <plat/cpu-freq.h>
35
a09e64fb 36#include <mach/regs-clock.h>
a2b7ba9c 37#include <plat/regs-serial.h>
a09e64fb 38#include <mach/regs-gpio.h>
96ce2385 39
a2b7ba9c 40#include <plat/s3c2410.h>
58bac7b8 41#include <plat/s3c244x.h>
d5120ae7 42#include <plat/clock.h>
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43#include <plat/devs.h>
44#include <plat/cpu.h>
45#include <plat/pm.h>
e24b864a 46#include <plat/pll.h>
ef3f2dd4 47#include <plat/nand-core.h>
c1ba544f 48#include <plat/watchdog-reset.h>
96ce2385 49
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50#include "regs-dsc.h"
51
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52static struct map_desc s3c244x_iodesc[] __initdata = {
53 IODESC_ENT(CLKPWR),
54 IODESC_ENT(TIMER),
55 IODESC_ENT(WATCHDOG),
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56};
57
58/* uart initialisation */
59
60void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
61{
62 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
63}
64
74b265d4 65void __init s3c244x_map_io(void)
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66{
67 /* register our io-tables */
68
69 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
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70
71 /* rename any peripherals used differing from the s3c2410 */
72
90239bbd 73 s3c_device_sdi.name = "s3c2440-sdi";
3e1b776c 74 s3c_device_i2c0.name = "s3c2440-i2c";
ef3f2dd4 75 s3c_nand_setname("s3c2440-nand");
ce8877b5 76 s3c_device_ts.name = "s3c2440-ts";
b8ccca4a 77 s3c_device_usbgadget.name = "s3c2440-usbgadget";
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78}
79
e425382e 80void __init_or_cpufreq s3c244x_setup_clocks(void)
96ce2385 81{
e425382e 82 struct clk *xtal_clk;
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83 unsigned long clkdiv;
84 unsigned long camdiv;
e425382e 85 unsigned long xtal;
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86 unsigned long hclk, fclk, pclk;
87 int hdiv = 1;
88
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89 xtal_clk = clk_get(NULL, "xtal");
90 xtal = clk_get_rate(xtal_clk);
91 clk_put(xtal_clk);
96ce2385 92
e24b864a 93 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
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94
95 clkdiv = __raw_readl(S3C2410_CLKDIVN);
96 camdiv = __raw_readl(S3C2440_CAMDIVN);
97
98 /* work out clock scalings */
99
100 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
101 case S3C2440_CLKDIVN_HDIVN_1:
102 hdiv = 1;
103 break;
104
105 case S3C2440_CLKDIVN_HDIVN_2:
106 hdiv = 2;
107 break;
108
109 case S3C2440_CLKDIVN_HDIVN_4_8:
110 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
111 break;
112
113 case S3C2440_CLKDIVN_HDIVN_3_6:
114 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
115 break;
116 }
117
118 hclk = fclk / hdiv;
e425382e 119 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
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120
121 /* print brief summary of clocks, etc */
122
123 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
124 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
125
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126 s3c24xx_setup_clocks(fclk, hclk, pclk);
127}
128
129void __init s3c244x_init_clocks(int xtal)
130{
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131 /* initialise the clocks here, to allow other things like the
132 * console to use them, and to add new ones after the initialisation
133 */
134
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135 s3c24xx_register_baseclocks(xtal);
136 s3c244x_setup_clocks();
99c13853 137 s3c2410_baseclk_add();
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138}
139
4a858cfc 140/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
96ce2385 141
4a858cfc 142struct bus_type s3c2440_subsys = {
af5ca3f4 143 .name = "s3c2440-core",
4a858cfc 144 .dev_name = "s3c2440-core",
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145};
146
4a858cfc 147struct bus_type s3c2442_subsys = {
af5ca3f4 148 .name = "s3c2442-core",
4a858cfc 149 .dev_name = "s3c2442-core",
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150};
151
4a858cfc 152/* need to register the subsystem before we actually register the device, and
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153 * we also need to ensure that it has been initialised before any of the
154 * drivers even try to use it (even if not on an s3c2440 based system)
155 * as a driver which may support both 2410 and 2440 may try and use it.
156*/
157
158static int __init s3c2440_core_init(void)
159{
4a858cfc 160 return subsys_system_register(&s3c2440_subsys, NULL);
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161}
162
163core_initcall(s3c2440_core_init);
164
165static int __init s3c2442_core_init(void)
166{
4a858cfc 167 return subsys_system_register(&s3c2442_subsys, NULL);
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168}
169
170core_initcall(s3c2442_core_init);
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171
172
173#ifdef CONFIG_PM
174static struct sleep_save s3c244x_sleep[] = {
175 SAVE_ITEM(S3C2440_DSC0),
176 SAVE_ITEM(S3C2440_DSC1),
177 SAVE_ITEM(S3C2440_GPJDAT),
178 SAVE_ITEM(S3C2440_GPJCON),
179 SAVE_ITEM(S3C2440_GPJUP)
180};
181
182static int s3c244x_suspend(void)
183{
184 s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
185 return 0;
186}
187
188static void s3c244x_resume(void)
189{
190 s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
191}
192#else
193#define s3c244x_suspend NULL
194#define s3c244x_resume NULL
195#endif
196
197struct syscore_ops s3c244x_pm_syscore_ops = {
198 .suspend = s3c244x_suspend,
199 .resume = s3c244x_resume,
200};
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201
202void s3c244x_restart(char mode, const char *cmd)
203{
204 if (mode == 's')
205 soft_restart(0);
206
207 arch_wdt_reset();
208
209 /* we'll take a jump through zero as a poor second */
210 soft_restart(0);
48546cc0 211}
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