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1 | /* linux/arch/arm/mach-s3c6410/cpu.c |
2 | * | |
3 | * Copyright 2008 Simtec Electronics | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/sysdev.h> | |
22 | #include <linux/serial_core.h> | |
23 | #include <linux/platform_device.h> | |
24 | ||
25 | #include <asm/mach/arch.h> | |
26 | #include <asm/mach/map.h> | |
27 | #include <asm/mach/irq.h> | |
28 | ||
29 | #include <mach/hardware.h> | |
30 | #include <asm/irq.h> | |
31 | ||
32 | #include <plat/cpu-freq.h> | |
33 | #include <plat/regs-serial.h> | |
496a3f09 | 34 | #include <plat/regs-clock.h> |
d626aeed BD |
35 | |
36 | #include <plat/cpu.h> | |
37 | #include <plat/devs.h> | |
38 | #include <plat/clock.h> | |
5cc7fd88 | 39 | #include <plat/sdhci.h> |
4f507d19 | 40 | #include <plat/iic-core.h> |
cf18acf0 | 41 | #include <plat/s3c6400.h> |
d626aeed BD |
42 | #include <plat/s3c6410.h> |
43 | ||
44 | /* Initial IO mappings */ | |
45 | ||
46 | static struct map_desc s3c6410_iodesc[] __initdata = { | |
47 | }; | |
48 | ||
49 | /* s3c6410_map_io | |
50 | * | |
51 | * register the standard cpu IO areas | |
52 | */ | |
53 | ||
54 | void __init s3c6410_map_io(void) | |
55 | { | |
56 | iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc)); | |
5cc7fd88 BD |
57 | |
58 | /* initialise device information early */ | |
59 | s3c6410_default_sdhci0(); | |
a2205cd2 | 60 | s3c6410_default_sdhci1(); |
4f507d19 BD |
61 | |
62 | /* the i2c devices are directly compatible with s3c2440 */ | |
63 | s3c_i2c0_setname("s3c2440-i2c"); | |
64 | s3c_i2c1_setname("s3c2440-i2c"); | |
14077ea6 PK |
65 | |
66 | s3c_device_nand.name = "s3c6400-nand"; | |
d626aeed BD |
67 | } |
68 | ||
69 | void __init s3c6410_init_clocks(int xtal) | |
70 | { | |
39669f59 | 71 | printk(KERN_DEBUG "%s: initialising clocks\n", __func__); |
d626aeed | 72 | s3c24xx_register_baseclocks(xtal); |
4b31d8b2 | 73 | s3c64xx_register_clocks(); |
496a3f09 | 74 | s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK); |
cf18acf0 | 75 | s3c6400_setup_clocks(); |
d626aeed BD |
76 | } |
77 | ||
d9b79fb5 BD |
78 | void __init s3c6410_init_irq(void) |
79 | { | |
80 | /* VIC0 is missing IRQ7, VIC1 is fully populated. */ | |
81 | s3c64xx_init_irq(~0 & ~(1 << 7), ~0); | |
82 | } | |
83 | ||
d626aeed BD |
84 | struct sysdev_class s3c6410_sysclass = { |
85 | .name = "s3c6410-core", | |
86 | }; | |
87 | ||
88 | static struct sys_device s3c6410_sysdev = { | |
89 | .cls = &s3c6410_sysclass, | |
90 | }; | |
91 | ||
92 | static int __init s3c6410_core_init(void) | |
93 | { | |
94 | return sysdev_class_register(&s3c6410_sysclass); | |
95 | } | |
96 | ||
97 | core_initcall(s3c6410_core_init); | |
98 | ||
99 | int __init s3c6410_init(void) | |
100 | { | |
101 | printk("S3C6410: Initialising architecture\n"); | |
102 | ||
103 | return sysdev_register(&s3c6410_sysdev); | |
104 | } |