[deliverable/linux.git] / arch / arm / mach-s3c64xx / clock.c

/* linux/arch/arm/plat-s3c64xx/clock.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C64XX Base clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/map.h>

#include <mach/regs-sys.h>
#include <mach/regs-clock.h>
#include <mach/pll.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>

/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
 * ext_xtal_mux for want of an actual name from the manual.
*/

static struct clk clk_ext_xtal_mux = {
	.name		= "ext_xtal",
	.id		= -1,
};

#define clk_fin_apll clk_ext_xtal_mux
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux

#define clk_fout_mpll	clk_mpll
#define clk_fout_epll	clk_epll

struct clk clk_h2 = {
	.name		= "hclk2",
	.id		= -1,
	.rate		= 0,
};

struct clk clk_27m = {
	.name		= "clk_27m",
	.id		= -1,
	.rate		= 27000000,
};

static int clk_48m_ctrl(struct clk *clk, int enable)
{
	unsigned long flags;
	u32 val;

	/* can't rely on clock lock, this register has other usages */
	local_irq_save(flags);

	val = __raw_readl(S3C64XX_OTHERS);
	if (enable)
		val |= S3C64XX_OTHERS_USBMASK;
	else
		val &= ~S3C64XX_OTHERS_USBMASK;

	__raw_writel(val, S3C64XX_OTHERS);
	local_irq_restore(flags);

	return 0;
}

struct clk clk_48m = {
	.name		= "clk_48m",
	.id		= -1,
	.rate		= 48000000,
	.enable		= clk_48m_ctrl,
};

struct clk clk_xusbxti = {
	.name		= "xusbxti",
	.id		= -1,
	.rate		= 48000000,
};

static int inline s3c64xx_gate(void __iomem *reg,
				struct clk *clk,
				int enable)
{
	unsigned int ctrlbit = clk->ctrlbit;
	u32 con;

	con = __raw_readl(reg);

	if (enable)
		con |= ctrlbit;
	else
		con &= ~ctrlbit;

	__raw_writel(con, reg);
	return 0;
}

static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
{
	return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
}

static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
{
	return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
}

int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
{
	return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
}

static struct clk init_clocks_disable[] = {
	{
		.name		= "nand",
		.id		= -1,
		.parent		= &clk_h,
	}, {
		.name		= "adc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_TSADC,
	}, {
		.name		= "i2c",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_IIC,
	}, {
		.name		= "iis",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_IIS0,
	}, {
		.name		= "iis",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_IIS1,
	}, {
#ifdef CONFIG_CPU_S3C6410
		.name		= "iis",
		.id		= -1,  /* There's only one IISv4 port */
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C6410_CLKCON_PCLK_IIS2,
	}, {
#endif
		.name		= "spi",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_SPI0,
	}, {
		.name		= "spi",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_SPI1,
	}, {
		.name		= "spi_48m",
		.id		= 0,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_SPI0_48,
	}, {
		.name		= "spi_48m",
		.id		= 1,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_SPI1_48,
	}, {
		.name		= "48m",
		.id		= 0,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_MMC0_48,
	}, {
		.name		= "48m",
		.id		= 1,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_MMC1_48,
	}, {
		.name		= "48m",
		.id		= 2,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_MMC2_48,
	}, {
		.name		= "dma0",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_DMA0,
	}, {
		.name		= "dma1",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_DMA1,
	},
};

static struct clk init_clocks[] = {
	{
		.name		= "lcd",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_LCD,
	}, {
		.name		= "gpio",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_GPIO,
	}, {
		.name		= "usb-host",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_UHOST,
	}, {
		.name		= "hsmmc",
		.id		= 0,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_HSMMC0,
	}, {
		.name		= "hsmmc",
		.id		= 1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_HSMMC1,
	}, {
		.name		= "hsmmc",
		.id		= 2,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_HSMMC2,
	}, {
		.name		= "timers",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_PWM,
	}, {
		.name		= "uart",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART0,
	}, {
		.name		= "uart",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART1,
	}, {
		.name		= "uart",
		.id		= 2,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART2,
	}, {
		.name		= "uart",
		.id		= 3,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART3,
	}, {
		.name		= "rtc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_RTC,
	}, {
		.name		= "watchdog",
		.id		= -1,
		.parent		= &clk_p,
		.ctrlbit	= S3C_CLKCON_PCLK_WDT,
	}, {
		.name		= "ac97",
		.id		= -1,
		.parent		= &clk_p,
		.ctrlbit	= S3C_CLKCON_PCLK_AC97,
	}
};


static struct clk clk_fout_apll = {
	.name		= "fout_apll",
	.id		= -1,
};

static struct clk *clk_src_apll_list[] = {
	[0] = &clk_fin_apll,
	[1] = &clk_fout_apll,
};

static struct clksrc_sources clk_src_apll = {
	.sources	= clk_src_apll_list,
	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
};

static struct clksrc_clk clk_mout_apll = {
	.clk	= {
		.name		= "mout_apll",
		.id		= -1,
	},
	.reg_src	= { .reg = S3C_CLK_SRC, .shift = 0, .size = 1  },
	.sources	= &clk_src_apll,
};

static struct clk *clk_src_epll_list[] = {
	[0] = &clk_fin_epll,
	[1] = &clk_fout_epll,
};

static struct clksrc_sources clk_src_epll = {
	.sources	= clk_src_epll_list,
	.nr_sources	= ARRAY_SIZE(clk_src_epll_list),
};

static struct clksrc_clk clk_mout_epll = {
	.clk	= {
		.name		= "mout_epll",
		.id		= -1,
	},
	.reg_src	= { .reg = S3C_CLK_SRC, .shift = 2, .size = 1  },
	.sources	= &clk_src_epll,
};

static struct clk *clk_src_mpll_list[] = {
	[0] = &clk_fin_mpll,
	[1] = &clk_fout_mpll,
};

static struct clksrc_sources clk_src_mpll = {
	.sources	= clk_src_mpll_list,
	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),
};

static struct clksrc_clk clk_mout_mpll = {
	.clk = {
		.name		= "mout_mpll",
		.id		= -1,
	},
	.reg_src	= { .reg = S3C_CLK_SRC, .shift = 1, .size = 1  },
	.sources	= &clk_src_mpll,
};

static unsigned int armclk_mask;

static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);
	u32 clkdiv;

	/* divisor mask starts at bit0, so no need to shift */
	clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;

	return rate / (clkdiv + 1);
}

static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
						unsigned long rate)
{
	unsigned long parent = clk_get_rate(clk->parent);
	u32 div;

	if (parent < rate)
		return parent;

	div = (parent / rate) - 1;
	if (div > armclk_mask)
		div = armclk_mask;

	return parent / (div + 1);
}

static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long parent = clk_get_rate(clk->parent);
	u32 div;
	u32 val;

	if (rate < parent / (armclk_mask + 1))
		return -EINVAL;

	rate = clk_round_rate(clk, rate);
	div = clk_get_rate(clk->parent) / rate;

	val = __raw_readl(S3C_CLK_DIV0);
	val &= ~armclk_mask;
	val |= (div - 1);
	__raw_writel(val, S3C_CLK_DIV0);

	return 0;

}

static struct clk clk_arm = {
	.name		= "armclk",
	.id		= -1,
	.parent		= &clk_mout_apll.clk,
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c64xx_clk_arm_get_rate,
		.set_rate	= s3c64xx_clk_arm_set_rate,
		.round_rate	= s3c64xx_clk_arm_round_rate,
	},
};

static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);

	printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);

	if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
		rate /= 2;

	return rate;
}

static struct clk_ops clk_dout_ops = {
	.get_rate	= s3c64xx_clk_doutmpll_get_rate,
};

static struct clk clk_dout_mpll = {
	.name		= "dout_mpll",
	.id		= -1,
	.parent		= &clk_mout_mpll.clk,
	.ops		= &clk_dout_ops,
};

static struct clk *clkset_spi_mmc_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	&clk_fin_epll,
	&clk_27m,
};

static struct clksrc_sources clkset_spi_mmc = {
	.sources	= clkset_spi_mmc_list,
	.nr_sources	= ARRAY_SIZE(clkset_spi_mmc_list),
};

static struct clk *clkset_irda_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	NULL,
	&clk_27m,
};

static struct clksrc_sources clkset_irda = {
	.sources	= clkset_irda_list,
	.nr_sources	= ARRAY_SIZE(clkset_irda_list),
};

static struct clk *clkset_uart_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	NULL,
	NULL
};

static struct clksrc_sources clkset_uart = {
	.sources	= clkset_uart_list,
	.nr_sources	= ARRAY_SIZE(clkset_uart_list),
};

static struct clk *clkset_uhost_list[] = {
	&clk_48m,
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	&clk_fin_epll,
};

static struct clksrc_sources clkset_uhost = {
	.sources	= clkset_uhost_list,
	.nr_sources	= ARRAY_SIZE(clkset_uhost_list),
};

/* The peripheral clocks are all controlled via clocksource followed
 * by an optional divider and gate stage. We currently roll this into
 * one clock which hides the intermediate clock from the mux.
 *
 * Note, the JPEG clock can only be an even divider...
 *
 * The scaler and LCD clocks depend on the S3C64XX version, and also
 * have a common parent divisor so are not included here.
 */

/* clocks that feed other parts of the clock source tree */

static struct clk clk_iis_cd0 = {
	.name		= "iis_cdclk0",
	.id		= -1,
};

static struct clk clk_iis_cd1 = {
	.name		= "iis_cdclk1",
	.id		= -1,
};

static struct clk clk_iisv4_cd = {
	.name		= "iis_cdclk_v4",
	.id		= -1,
};

static struct clk clk_pcm_cd = {
	.name		= "pcm_cdclk",
	.id		= -1,
};

static struct clk *clkset_audio0_list[] = {
	[0] = &clk_mout_epll.clk,
	[1] = &clk_dout_mpll,
	[2] = &clk_fin_epll,
	[3] = &clk_iis_cd0,
	[4] = &clk_pcm_cd,
};

static struct clksrc_sources clkset_audio0 = {
	.sources	= clkset_audio0_list,
	.nr_sources	= ARRAY_SIZE(clkset_audio0_list),
};

static struct clk *clkset_audio1_list[] = {
	[0] = &clk_mout_epll.clk,
	[1] = &clk_dout_mpll,
	[2] = &clk_fin_epll,
	[3] = &clk_iis_cd1,
	[4] = &clk_pcm_cd,
};

static struct clksrc_sources clkset_audio1 = {
	.sources	= clkset_audio1_list,
	.nr_sources	= ARRAY_SIZE(clkset_audio1_list),
};

static struct clk *clkset_audio2_list[] = {
	[0] = &clk_mout_epll.clk,
	[1] = &clk_dout_mpll,
	[2] = &clk_fin_epll,
	[3] = &clk_iisv4_cd,
	[4] = &clk_pcm_cd,
};

static struct clksrc_sources clkset_audio2 = {
	.sources	= clkset_audio2_list,
	.nr_sources	= ARRAY_SIZE(clkset_audio2_list),
};

static struct clk *clkset_camif_list[] = {
	&clk_h2,
};

static struct clksrc_sources clkset_camif = {
	.sources	= clkset_camif_list,
	.nr_sources	= ARRAY_SIZE(clkset_camif_list),
};

static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "mmc_bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_MMC0,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "mmc_bus",
			.id		= 1,
			.ctrlbit        = S3C_CLKCON_SCLK_MMC1,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "mmc_bus",
			.id		= 2,
			.ctrlbit        = S3C_CLKCON_SCLK_MMC2,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
		.reg_div 	= { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "usb-bus-host",
			.id		= -1,
			.ctrlbit        = S3C_CLKCON_SCLK_UHOST,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src 	= { .reg = S3C_CLK_SRC, .shift = 5, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },
		.sources	= &clkset_uhost,
	}, {
		.clk	= {
			.name		= "uclk1",
			.id		= -1,
			.ctrlbit        = S3C_CLKCON_SCLK_UART,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
		.sources	= &clkset_uart,
	}, {
/* Where does UCLK0 come from? */
		.clk	= {
			.name		= "spi-bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_SPI0,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 14, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "spi-bus",
			.id		= 1,
			.ctrlbit        = S3C_CLKCON_SCLK_SPI1,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 16, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "audio-bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 7, .size = 3  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4  },
		.sources	= &clkset_audio0,
	}, {
		.clk	= {
			.name		= "audio-bus",
			.id		= 1,
			.ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 10, .size = 3  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4  },
		.sources	= &clkset_audio1,
	}, {
		.clk	= {
			.name		= "audio-bus",
			.id		= -1,  /* There's only one IISv4 port */
			.ctrlbit        = S3C6410_CLKCON_SCLK_AUDIO2,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4  },
		.sources	= &clkset_audio2,
	}, {
		.clk	= {
			.name		= "irda-bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_IRDA,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 24, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4  },
		.sources	= &clkset_irda,
	}, {
		.clk	= {
			.name		= "camera",
			.id		= -1,
			.ctrlbit        = S3C_CLKCON_SCLK_CAM,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_div	= { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
		.reg_src	= { .reg = NULL, .shift = 0, .size = 0  },
		.sources	= &clkset_camif,
	},
};

/* Clock initialisation code */

static struct clksrc_clk *init_parents[] = {
	&clk_mout_apll,
	&clk_mout_epll,
	&clk_mout_mpll,
};

#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

void __init_or_cpufreq s3c6400_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk2;
	unsigned long pclk;
	unsigned long epll;
	unsigned long apll;
	unsigned long mpll;
	unsigned int ptr;
	u32 clkdiv0;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	clkdiv0 = __raw_readl(S3C_CLK_DIV0);
	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	/* For now assume the mux always selects the crystal */
	clk_ext_xtal_mux.parent = xtal_clk;

	epll = s3c6400_get_epll(xtal);
	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));

	fclk = mpll;

	printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
	       apll, mpll, epll);

	hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
	hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
	pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);

	printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
	       hclk2, hclk, pclk);

	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_apll.rate = apll;

	clk_h2.rate = hclk2;
	clk_h.rate = hclk;
	clk_p.rate = pclk;
	clk_f.rate = fclk;

	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
		s3c_set_clksrc(init_parents[ptr], true);

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}

static struct clk *clks1[] __initdata = {
	&clk_ext_xtal_mux,
	&clk_iis_cd0,
	&clk_iis_cd1,
	&clk_iisv4_cd,
	&clk_pcm_cd,
	&clk_mout_epll.clk,
	&clk_mout_mpll.clk,
	&clk_dout_mpll,
	&clk_arm,
};

static struct clk *clks[] __initdata = {
	&clk_ext,
	&clk_epll,
	&clk_27m,
	&clk_48m,
	&clk_h2,
	&clk_xusbxti,
};

/**
 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
 * @xtal: The rate for the clock crystal feeding the PLLs.
 * @armclk_divlimit: Divisor mask for ARMCLK.
 *
 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
 * as ARMCLK as well as the necessary parent clocks.
 *
 * This call does not setup the clocks, which is left to the
 * s3c6400_setup_clocks() call which may be needed by the cpufreq
 * or resume code to re-set the clocks if the bootloader has changed
 * them.
 */
void __init s3c64xx_register_clocks(unsigned long xtal, 
				    unsigned armclk_divlimit)
{
	struct clk *clkp;
	int ret;
	int ptr;

	armclk_mask = armclk_divlimit;

	s3c24xx_register_baseclocks(xtal);
	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	clkp = init_clocks_disable;
	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {

		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}

		(clkp->enable)(clkp, 0);
	}

	s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	s3c_pwmclk_init();
}
Commit	Line	Data
4b31d8b2 BD	1	/* linux/arch/arm/plat-s3c64xx/clock.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C64XX Base clock support
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/ioport.h>
62acb2f8 BD	19	#include <linux/clk.h>
62acb2f8 BD	20	#include <linux/err.h>
4b31d8b2 BD	21	#include <linux/io.h>
	22
	23	#include <mach/hardware.h>
	24	#include <mach/map.h>
	25
3501c9ae BD	26	#include <mach/regs-sys.h>
3501c9ae BD	27	#include <mach/regs-clock.h>
f7be9aba BD	28	#include <mach/pll.h>
f7be9aba BD	29
4b31d8b2 BD	30	#include <plat/cpu.h>
4b31d8b2 BD	31	#include <plat/devs.h>
62acb2f8	32	#include <plat/cpu-freq.h>
4b31d8b2	33	#include <plat/clock.h>
62acb2f8 BD	34	#include <plat/clock-clksrc.h>
	35
	36	/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
	37	* ext_xtal_mux for want of an actual name from the manual.
	38	*/
	39
	40	static struct clk clk_ext_xtal_mux = {
	41	.name = "ext_xtal",
	42	.id = -1,
	43	};
	44
	45	#define clk_fin_apll clk_ext_xtal_mux
	46	#define clk_fin_mpll clk_ext_xtal_mux
	47	#define clk_fin_epll clk_ext_xtal_mux
	48
	49	#define clk_fout_mpll clk_mpll
	50	#define clk_fout_epll clk_epll
4b31d8b2	51
a03f7daf WA	52	struct clk clk_h2 = {
	53	.name = "hclk2",
	54	.id = -1,
	55	.rate = 0,
	56	};
	57
4b31d8b2 BD	58	struct clk clk_27m = {
	59	.name = "clk_27m",
	60	.id = -1,
	61	.rate = 27000000,
	62	};
	63
3627379f BD	64	static int clk_48m_ctrl(struct clk *clk, int enable)
	65	{
	66	unsigned long flags;
	67	u32 val;
	68
	69	/* can't rely on clock lock, this register has other usages */
	70	local_irq_save(flags);
	71
	72	val = __raw_readl(S3C64XX_OTHERS);
	73	if (enable)
	74	val \|= S3C64XX_OTHERS_USBMASK;
	75	else
	76	val &= ~S3C64XX_OTHERS_USBMASK;
	77
	78	__raw_writel(val, S3C64XX_OTHERS);
	79	local_irq_restore(flags);
	80
	81	return 0;
	82	}
	83
4b31d8b2 BD	84	struct clk clk_48m = {
	85	.name = "clk_48m",
	86	.id = -1,
	87	.rate = 48000000,
3627379f	88	.enable = clk_48m_ctrl,
4b31d8b2 BD	89	};
4b31d8b2 BD	90
05e021f0 MC	91	struct clk clk_xusbxti = {
	92	.name = "xusbxti",
	93	.id = -1,
	94	.rate = 48000000,
	95	};
	96
4b31d8b2 BD	97	static int inline s3c64xx_gate(void __iomem *reg,
	98	struct clk *clk,
	99	int enable)
	100	{
	101	unsigned int ctrlbit = clk->ctrlbit;
	102	u32 con;
	103
	104	con = __raw_readl(reg);
	105
	106	if (enable)
	107	con \|= ctrlbit;
	108	else
	109	con &= ~ctrlbit;
	110
	111	__raw_writel(con, reg);
	112	return 0;
	113	}
	114
	115	static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
	116	{
	117	return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
	118	}
	119
	120	static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
	121	{
	122	return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
	123	}
	124
cf18acf0	125	int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
4b31d8b2 BD	126	{
	127	return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
	128	}
	129
	130	static struct clk init_clocks_disable[] = {
	131	{
	132	.name = "nand",
	133	.id = -1,
	134	.parent = &clk_h,
	135	}, {
	136	.name = "adc",
	137	.id = -1,
	138	.parent = &clk_p,
	139	.enable = s3c64xx_pclk_ctrl,
	140	.ctrlbit = S3C_CLKCON_PCLK_TSADC,
	141	}, {
	142	.name = "i2c",
	143	.id = -1,
	144	.parent = &clk_p,
	145	.enable = s3c64xx_pclk_ctrl,
	146	.ctrlbit = S3C_CLKCON_PCLK_IIC,
	147	}, {
	148	.name = "iis",
	149	.id = 0,
	150	.parent = &clk_p,
	151	.enable = s3c64xx_pclk_ctrl,
	152	.ctrlbit = S3C_CLKCON_PCLK_IIS0,
	153	}, {
	154	.name = "iis",
	155	.id = 1,
	156	.parent = &clk_p,
	157	.enable = s3c64xx_pclk_ctrl,
	158	.ctrlbit = S3C_CLKCON_PCLK_IIS1,
	159	}, {
2e5070bc JB	160	#ifdef CONFIG_CPU_S3C6410
	161	.name = "iis",
	162	.id = -1, /* There's only one IISv4 port */
	163	.parent = &clk_p,
	164	.enable = s3c64xx_pclk_ctrl,
	165	.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
	166	}, {
	167	#endif
4b31d8b2 BD	168	.name = "spi",
	169	.id = 0,
	170	.parent = &clk_p,
	171	.enable = s3c64xx_pclk_ctrl,
	172	.ctrlbit = S3C_CLKCON_PCLK_SPI0,
	173	}, {
	174	.name = "spi",
	175	.id = 1,
	176	.parent = &clk_p,
	177	.enable = s3c64xx_pclk_ctrl,
	178	.ctrlbit = S3C_CLKCON_PCLK_SPI1,
87315a80 JB	179	}, {
	180	.name = "spi_48m",
	181	.id = 0,
	182	.parent = &clk_48m,
	183	.enable = s3c64xx_sclk_ctrl,
	184	.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
	185	}, {
	186	.name = "spi_48m",
	187	.id = 1,
	188	.parent = &clk_48m,
	189	.enable = s3c64xx_sclk_ctrl,
	190	.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
4b31d8b2 BD	191	}, {
	192	.name = "48m",
	193	.id = 0,
	194	.parent = &clk_48m,
	195	.enable = s3c64xx_sclk_ctrl,
	196	.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
	197	}, {
	198	.name = "48m",
	199	.id = 1,
	200	.parent = &clk_48m,
	201	.enable = s3c64xx_sclk_ctrl,
	202	.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
	203	}, {
	204	.name = "48m",
	205	.id = 2,
	206	.parent = &clk_48m,
	207	.enable = s3c64xx_sclk_ctrl,
	208	.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
8f1ecf1d MB	209	}, {
	210	.name = "dma0",
	211	.id = -1,
	212	.parent = &clk_h,
	213	.enable = s3c64xx_hclk_ctrl,
	214	.ctrlbit = S3C_CLKCON_HCLK_DMA0,
	215	}, {
	216	.name = "dma1",
	217	.id = -1,
	218	.parent = &clk_h,
	219	.enable = s3c64xx_hclk_ctrl,
	220	.ctrlbit = S3C_CLKCON_HCLK_DMA1,
4b31d8b2 BD	221	},
	222	};
	223
	224	static struct clk init_clocks[] = {
	225	{
	226	.name = "lcd",
	227	.id = -1,
	228	.parent = &clk_h,
	229	.enable = s3c64xx_hclk_ctrl,
	230	.ctrlbit = S3C_CLKCON_HCLK_LCD,
	231	}, {
	232	.name = "gpio",
	233	.id = -1,
	234	.parent = &clk_p,
	235	.enable = s3c64xx_pclk_ctrl,
	236	.ctrlbit = S3C_CLKCON_PCLK_GPIO,
	237	}, {
	238	.name = "usb-host",
	239	.id = -1,
	240	.parent = &clk_h,
	241	.enable = s3c64xx_hclk_ctrl,
386f4351	242	.ctrlbit = S3C_CLKCON_HCLK_UHOST,
4b31d8b2 BD	243	}, {
	244	.name = "hsmmc",
	245	.id = 0,
	246	.parent = &clk_h,
	247	.enable = s3c64xx_hclk_ctrl,
	248	.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
	249	}, {
	250	.name = "hsmmc",
	251	.id = 1,
	252	.parent = &clk_h,
	253	.enable = s3c64xx_hclk_ctrl,
	254	.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
	255	}, {
	256	.name = "hsmmc",
	257	.id = 2,
	258	.parent = &clk_h,
	259	.enable = s3c64xx_hclk_ctrl,
	260	.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
	261	}, {
	262	.name = "timers",
	263	.id = -1,
	264	.parent = &clk_p,
	265	.enable = s3c64xx_pclk_ctrl,
	266	.ctrlbit = S3C_CLKCON_PCLK_PWM,
	267	}, {
	268	.name = "uart",
	269	.id = 0,
	270	.parent = &clk_p,
	271	.enable = s3c64xx_pclk_ctrl,
	272	.ctrlbit = S3C_CLKCON_PCLK_UART0,
	273	}, {
	274	.name = "uart",
	275	.id = 1,
	276	.parent = &clk_p,
	277	.enable = s3c64xx_pclk_ctrl,
	278	.ctrlbit = S3C_CLKCON_PCLK_UART1,
	279	}, {
	280	.name = "uart",
	281	.id = 2,
	282	.parent = &clk_p,
	283	.enable = s3c64xx_pclk_ctrl,
	284	.ctrlbit = S3C_CLKCON_PCLK_UART2,
	285	}, {
	286	.name = "uart",
	287	.id = 3,
	288	.parent = &clk_p,
	289	.enable = s3c64xx_pclk_ctrl,
	290	.ctrlbit = S3C_CLKCON_PCLK_UART3,
	291	}, {
	292	.name = "rtc",
	293	.id = -1,
	294	.parent = &clk_p,
	295	.enable = s3c64xx_pclk_ctrl,
	296	.ctrlbit = S3C_CLKCON_PCLK_RTC,
	297	}, {
	298	.name = "watchdog",
	299	.id = -1,
	300	.parent = &clk_p,
	301	.ctrlbit = S3C_CLKCON_PCLK_WDT,
	302	}, {
	303	.name = "ac97",
	304	.id = -1,
	305	.parent = &clk_p,
	306	.ctrlbit = S3C_CLKCON_PCLK_AC97,
307	}
308	};
309
62acb2f8 BD	310
	311	static struct clk clk_fout_apll = {
	312	.name = "fout_apll",
	313	.id = -1,
	314	};
	315
	316	static struct clk *clk_src_apll_list[] = {
	317	[0] = &clk_fin_apll,
	318	[1] = &clk_fout_apll,
	319	};
	320
	321	static struct clksrc_sources clk_src_apll = {
	322	.sources = clk_src_apll_list,
	323	.nr_sources = ARRAY_SIZE(clk_src_apll_list),
	324	};
	325
	326	static struct clksrc_clk clk_mout_apll = {
	327	.clk = {
	328	.name = "mout_apll",
	329	.id = -1,
	330	},
	331	.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
	332	.sources = &clk_src_apll,
	333	};
	334
	335	static struct clk *clk_src_epll_list[] = {
	336	[0] = &clk_fin_epll,
	337	[1] = &clk_fout_epll,
	338	};
	339
	340	static struct clksrc_sources clk_src_epll = {
	341	.sources = clk_src_epll_list,
	342	.nr_sources = ARRAY_SIZE(clk_src_epll_list),
	343	};
	344
	345	static struct clksrc_clk clk_mout_epll = {
	346	.clk = {
	347	.name = "mout_epll",
	348	.id = -1,
	349	},
	350	.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
	351	.sources = &clk_src_epll,
	352	};
	353
	354	static struct clk *clk_src_mpll_list[] = {
	355	[0] = &clk_fin_mpll,
	356	[1] = &clk_fout_mpll,
	357	};
	358
	359	static struct clksrc_sources clk_src_mpll = {
	360	.sources = clk_src_mpll_list,
	361	.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
	362	};
	363
	364	static struct clksrc_clk clk_mout_mpll = {
	365	.clk = {
	366	.name = "mout_mpll",
	367	.id = -1,
	368	},
	369	.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
	370	.sources = &clk_src_mpll,
	371	};
	372
	373	static unsigned int armclk_mask;
374
375	static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
376	{
377	unsigned long rate = clk_get_rate(clk->parent);
378	u32 clkdiv;
379
380	/* divisor mask starts at bit0, so no need to shift */
381	clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
382
383	return rate / (clkdiv + 1);
384	}
385
386	static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
387	unsigned long rate)
388	{
389	unsigned long parent = clk_get_rate(clk->parent);
390	u32 div;
391
392	if (parent < rate)
393	return parent;
394
395	div = (parent / rate) - 1;
396	if (div > armclk_mask)
397	div = armclk_mask;
398
399	return parent / (div + 1);
400	}
401
402	static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
403	{
404	unsigned long parent = clk_get_rate(clk->parent);
405	u32 div;
406	u32 val;
407
408	if (rate < parent / (armclk_mask + 1))
409	return -EINVAL;
410
411	rate = clk_round_rate(clk, rate);
412	div = clk_get_rate(clk->parent) / rate;
413
414	val = __raw_readl(S3C_CLK_DIV0);
415	val &= ~armclk_mask;
416	val \|= (div - 1);
417	__raw_writel(val, S3C_CLK_DIV0);
418
419	return 0;
420
421	}
422
423	static struct clk clk_arm = {
424	.name = "armclk",
425	.id = -1,
426	.parent = &clk_mout_apll.clk,
427	.ops = &(struct clk_ops) {
428	.get_rate = s3c64xx_clk_arm_get_rate,
429	.set_rate = s3c64xx_clk_arm_set_rate,
430	.round_rate = s3c64xx_clk_arm_round_rate,
431	},
432	};
433
434	static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
435	{
436	unsigned long rate = clk_get_rate(clk->parent);
437
438	printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
439
440	if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
441	rate /= 2;
442
443	return rate;
444	}
445
446	static struct clk_ops clk_dout_ops = {
447	.get_rate = s3c64xx_clk_doutmpll_get_rate,
448	};
449
450	static struct clk clk_dout_mpll = {
451	.name = "dout_mpll",
452	.id = -1,
453	.parent = &clk_mout_mpll.clk,
454	.ops = &clk_dout_ops,
455	};
456
457	static struct clk *clkset_spi_mmc_list[] = {
458	&clk_mout_epll.clk,
459	&clk_dout_mpll,
460	&clk_fin_epll,
461	&clk_27m,
462	};
463
464	static struct clksrc_sources clkset_spi_mmc = {
465	.sources = clkset_spi_mmc_list,
466	.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
467	};
468
469	static struct clk *clkset_irda_list[] = {
470	&clk_mout_epll.clk,
471	&clk_dout_mpll,
472	NULL,
473	&clk_27m,
474	};
475
476	static struct clksrc_sources clkset_irda = {
477	.sources = clkset_irda_list,
478	.nr_sources = ARRAY_SIZE(clkset_irda_list),
479	};
480
481	static struct clk *clkset_uart_list[] = {
482	&clk_mout_epll.clk,
483	&clk_dout_mpll,
484	NULL,
485	NULL
486	};
487
488	static struct clksrc_sources clkset_uart = {
489	.sources = clkset_uart_list,
490	.nr_sources = ARRAY_SIZE(clkset_uart_list),
491	};
492
493	static struct clk *clkset_uhost_list[] = {
494	&clk_48m,
495	&clk_mout_epll.clk,
496	&clk_dout_mpll,
497	&clk_fin_epll,
498	};
499
500	static struct clksrc_sources clkset_uhost = {
501	.sources = clkset_uhost_list,
502	.nr_sources = ARRAY_SIZE(clkset_uhost_list),
503	};
504
505	/* The peripheral clocks are all controlled via clocksource followed
506	* by an optional divider and gate stage. We currently roll this into
507	* one clock which hides the intermediate clock from the mux.
508	*
509	* Note, the JPEG clock can only be an even divider...
510	*
511	* The scaler and LCD clocks depend on the S3C64XX version, and also
512	* have a common parent divisor so are not included here.
513	*/
514
515	/* clocks that feed other parts of the clock source tree */
516
517	static struct clk clk_iis_cd0 = {
518	.name = "iis_cdclk0",
519	.id = -1,
520	};
521
522	static struct clk clk_iis_cd1 = {
523	.name = "iis_cdclk1",
524	.id = -1,
525	};
526
bc8eb1e2 JB	527	static struct clk clk_iisv4_cd = {
	528	.name = "iis_cdclk_v4",
	529	.id = -1,
	530	};
	531
62acb2f8 BD	532	static struct clk clk_pcm_cd = {
	533	.name = "pcm_cdclk",
	534	.id = -1,
	535	};
	536
	537	static struct clk *clkset_audio0_list[] = {
	538	[0] = &clk_mout_epll.clk,
	539	[1] = &clk_dout_mpll,
	540	[2] = &clk_fin_epll,
	541	[3] = &clk_iis_cd0,
	542	[4] = &clk_pcm_cd,
	543	};
	544
	545	static struct clksrc_sources clkset_audio0 = {
	546	.sources = clkset_audio0_list,
	547	.nr_sources = ARRAY_SIZE(clkset_audio0_list),
	548	};
	549
	550	static struct clk *clkset_audio1_list[] = {
	551	[0] = &clk_mout_epll.clk,
	552	[1] = &clk_dout_mpll,
	553	[2] = &clk_fin_epll,
	554	[3] = &clk_iis_cd1,
	555	[4] = &clk_pcm_cd,
	556	};
	557
	558	static struct clksrc_sources clkset_audio1 = {
	559	.sources = clkset_audio1_list,
	560	.nr_sources = ARRAY_SIZE(clkset_audio1_list),
	561	};
	562
1aede2ea JB	563	static struct clk *clkset_audio2_list[] = {
	564	[0] = &clk_mout_epll.clk,
	565	[1] = &clk_dout_mpll,
	566	[2] = &clk_fin_epll,
	567	[3] = &clk_iisv4_cd,
	568	[4] = &clk_pcm_cd,
	569	};
	570
	571	static struct clksrc_sources clkset_audio2 = {
	572	.sources = clkset_audio2_list,
	573	.nr_sources = ARRAY_SIZE(clkset_audio2_list),
	574	};
	575
62acb2f8 BD	576	static struct clk *clkset_camif_list[] = {
	577	&clk_h2,
	578	};
	579
	580	static struct clksrc_sources clkset_camif = {
	581	.sources = clkset_camif_list,
	582	.nr_sources = ARRAY_SIZE(clkset_camif_list),
	583	};
	584
	585	static struct clksrc_clk clksrcs[] = {
	586	{
	587	.clk = {
	588	.name = "mmc_bus",
	589	.id = 0,
	590	.ctrlbit = S3C_CLKCON_SCLK_MMC0,
	591	.enable = s3c64xx_sclk_ctrl,
	592	},
	593	.reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
	594	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
	595	.sources = &clkset_spi_mmc,
	596	}, {
	597	.clk = {
	598	.name = "mmc_bus",
	599	.id = 1,
	600	.ctrlbit = S3C_CLKCON_SCLK_MMC1,
	601	.enable = s3c64xx_sclk_ctrl,
	602	},
	603	.reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
	604	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
	605	.sources = &clkset_spi_mmc,
	606	}, {
	607	.clk = {
	608	.name = "mmc_bus",
	609	.id = 2,
	610	.ctrlbit = S3C_CLKCON_SCLK_MMC2,
	611	.enable = s3c64xx_sclk_ctrl,
	612	},
	613	.reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
	614	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
	615	.sources = &clkset_spi_mmc,
	616	}, {
	617	.clk = {
	618	.name = "usb-bus-host",
	619	.id = -1,
	620	.ctrlbit = S3C_CLKCON_SCLK_UHOST,
	621	.enable = s3c64xx_sclk_ctrl,
	622	},
	623	.reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
	624	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
	625	.sources = &clkset_uhost,
	626	}, {
	627	.clk = {
	628	.name = "uclk1",
	629	.id = -1,
	630	.ctrlbit = S3C_CLKCON_SCLK_UART,
	631	.enable = s3c64xx_sclk_ctrl,
	632	},
	633	.reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
	634	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
	635	.sources = &clkset_uart,
	636	}, {
	637	/* Where does UCLK0 come from? */
	638	.clk = {
	639	.name = "spi-bus",
640	.id = 0,
641	.ctrlbit = S3C_CLKCON_SCLK_SPI0,
642	.enable = s3c64xx_sclk_ctrl,
643	},
644	.reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
645	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
646	.sources = &clkset_spi_mmc,
647	}, {
648	.clk = {
649	.name = "spi-bus",
650	.id = 1,
651	.ctrlbit = S3C_CLKCON_SCLK_SPI1,
652	.enable = s3c64xx_sclk_ctrl,
653	},
654	.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
655	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
656	.sources = &clkset_spi_mmc,
657	}, {
658	.clk = {
659	.name = "audio-bus",
660	.id = 0,
661	.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
662	.enable = s3c64xx_sclk_ctrl,
663	},
664	.reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
665	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
666	.sources = &clkset_audio0,
667	}, {
668	.clk = {
669	.name = "audio-bus",
670	.id = 1,
671	.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
672	.enable = s3c64xx_sclk_ctrl,
673	},
674	.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
675	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
676	.sources = &clkset_audio1,
835879a8 JB	677	}, {
	678	.clk = {
	679	.name = "audio-bus",
	680	.id = -1, /* There's only one IISv4 port */
	681	.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
	682	.enable = s3c64xx_sclk_ctrl,
	683	},
	684	.reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
	685	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
	686	.sources = &clkset_audio2,
62acb2f8 BD	687	}, {
	688	.clk = {
	689	.name = "irda-bus",
	690	.id = 0,
	691	.ctrlbit = S3C_CLKCON_SCLK_IRDA,
	692	.enable = s3c64xx_sclk_ctrl,
	693	},
	694	.reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
	695	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
	696	.sources = &clkset_irda,
	697	}, {
	698	.clk = {
	699	.name = "camera",
	700	.id = -1,
	701	.ctrlbit = S3C_CLKCON_SCLK_CAM,
	702	.enable = s3c64xx_sclk_ctrl,
	703	},
	704	.reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
	705	.reg_src = { .reg = NULL, .shift = 0, .size = 0 },
	706	.sources = &clkset_camif,
	707	},
	708	};
	709
	710	/* Clock initialisation code */
	711
	712	static struct clksrc_clk *init_parents[] = {
	713	&clk_mout_apll,
	714	&clk_mout_epll,
	715	&clk_mout_mpll,
	716	};
	717
	718	#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
	719
	720	void __init_or_cpufreq s3c6400_setup_clocks(void)
	721	{
	722	struct clk *xtal_clk;
	723	unsigned long xtal;
	724	unsigned long fclk;
	725	unsigned long hclk;
	726	unsigned long hclk2;
	727	unsigned long pclk;
	728	unsigned long epll;
	729	unsigned long apll;
	730	unsigned long mpll;
	731	unsigned int ptr;
	732	u32 clkdiv0;
	733
	734	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
	735
	736	clkdiv0 = __raw_readl(S3C_CLK_DIV0);
	737	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
	738
	739	xtal_clk = clk_get(NULL, "xtal");
	740	BUG_ON(IS_ERR(xtal_clk));
	741
	742	xtal = clk_get_rate(xtal_clk);
	743	clk_put(xtal_clk);
	744
	745	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
	746
	747	/* For now assume the mux always selects the crystal */
	748	clk_ext_xtal_mux.parent = xtal_clk;
	749
	750	epll = s3c6400_get_epll(xtal);
751	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
752	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
753
754	fclk = mpll;
755
756	printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
757	apll, mpll, epll);
758
759	hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
760	hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
761	pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
762
763	printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
764	hclk2, hclk, pclk);
765
766	clk_fout_mpll.rate = mpll;
767	clk_fout_epll.rate = epll;
768	clk_fout_apll.rate = apll;
769
770	clk_h2.rate = hclk2;
771	clk_h.rate = hclk;
772	clk_p.rate = pclk;
773	clk_f.rate = fclk;
774
775	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
776	s3c_set_clksrc(init_parents[ptr], true);
777
778	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
779	s3c_set_clksrc(&clksrcs[ptr], true);
780	}
781
782	static struct clk *clks1[] __initdata = {
783	&clk_ext_xtal_mux,
784	&clk_iis_cd0,
785	&clk_iis_cd1,
bc8eb1e2	786	&clk_iisv4_cd,
62acb2f8 BD	787	&clk_pcm_cd,
	788	&clk_mout_epll.clk,
	789	&clk_mout_mpll.clk,
	790	&clk_dout_mpll,
	791	&clk_arm,
	792	};
	793
55bf9267 BD	794	static struct clk *clks[] __initdata = {
	795	&clk_ext,
	796	&clk_epll,
	797	&clk_27m,
	798	&clk_48m,
	799	&clk_h2,
05e021f0	800	&clk_xusbxti,
55bf9267 BD	801	};
55bf9267 BD	802
62acb2f8	803	/**
55bf9267 BD	804	* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
	805	* @xtal: The rate for the clock crystal feeding the PLLs.
	806	* @armclk_divlimit: Divisor mask for ARMCLK.
62acb2f8	807	*
55bf9267 BD	808	* Register the clocks for the S3C6400 and S3C6410 SoC range, such
55bf9267 BD	809	* as ARMCLK as well as the necessary parent clocks.
62acb2f8 BD	810	*
	811	* This call does not setup the clocks, which is left to the
	812	* s3c6400_setup_clocks() call which may be needed by the cpufreq
	813	* or resume code to re-set the clocks if the bootloader has changed
	814	* them.
	815	*/
55bf9267 BD	816	void __init s3c64xx_register_clocks(unsigned long xtal,
55bf9267 BD	817	unsigned armclk_divlimit)
62acb2f8 BD	818	{
	819	struct clk *clkp;
	820	int ret;
	821	int ptr;
	822
	823	armclk_mask = armclk_divlimit;
	824
55bf9267	825	s3c24xx_register_baseclocks(xtal);
4b31d8b2	826	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
55bf9267	827
1d9f13c4	828	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
4b31d8b2 BD	829
	830	clkp = init_clocks_disable;
	831	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
	832
	833	ret = s3c24xx_register_clock(clkp);
	834	if (ret < 0) {
	835	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	836	clkp->name, ret);
	837	}
	838
	839	(clkp->enable)(clkp, 0);
	840	}
9d325f23	841
55bf9267 BD	842	s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
55bf9267 BD	843	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
9d325f23	844	s3c_pwmclk_init();
4b31d8b2	845	}