[deliverable/linux.git] / arch / arm / mach-s3c64xx / clock.c

/* linux/arch/arm/plat-s3c64xx/clock.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C64XX Base clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/map.h>

#include <mach/regs-sys.h>
#include <mach/regs-clock.h>
#include <mach/pll.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>

/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
 * ext_xtal_mux for want of an actual name from the manual.
*/

static struct clk clk_ext_xtal_mux = {
	.name		= "ext_xtal",
	.id		= -1,
};

#define clk_fin_apll clk_ext_xtal_mux
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux

#define clk_fout_mpll	clk_mpll
#define clk_fout_epll	clk_epll

struct clk clk_h2 = {
	.name		= "hclk2",
	.id		= -1,
	.rate		= 0,
};

struct clk clk_27m = {
	.name		= "clk_27m",
	.id		= -1,
	.rate		= 27000000,
};

static int clk_48m_ctrl(struct clk *clk, int enable)
{
	unsigned long flags;
	u32 val;

	/* can't rely on clock lock, this register has other usages */
	local_irq_save(flags);

	val = __raw_readl(S3C64XX_OTHERS);
	if (enable)
		val |= S3C64XX_OTHERS_USBMASK;
	else
		val &= ~S3C64XX_OTHERS_USBMASK;

	__raw_writel(val, S3C64XX_OTHERS);
	local_irq_restore(flags);

	return 0;
}

struct clk clk_48m = {
	.name		= "clk_48m",
	.id		= -1,
	.rate		= 48000000,
	.enable		= clk_48m_ctrl,
};

static int inline s3c64xx_gate(void __iomem *reg,
				struct clk *clk,
				int enable)
{
	unsigned int ctrlbit = clk->ctrlbit;
	u32 con;

	con = __raw_readl(reg);

	if (enable)
		con |= ctrlbit;
	else
		con &= ~ctrlbit;

	__raw_writel(con, reg);
	return 0;
}

static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
{
	return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
}

static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
{
	return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
}

int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
{
	return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
}

static struct clk init_clocks_disable[] = {
	{
		.name		= "nand",
		.id		= -1,
		.parent		= &clk_h,
	}, {
		.name		= "adc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_TSADC,
	}, {
		.name		= "i2c",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_IIC,
	}, {
		.name		= "iis",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_IIS0,
	}, {
		.name		= "iis",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_IIS1,
	}, {
#ifdef CONFIG_CPU_S3C6410
		.name		= "iis",
		.id		= -1,  /* There's only one IISv4 port */
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C6410_CLKCON_PCLK_IIS2,
	}, {
#endif
		.name		= "spi",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_SPI0,
	}, {
		.name		= "spi",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_SPI1,
	}, {
		.name		= "spi_48m",
		.id		= 0,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_SPI0_48,
	}, {
		.name		= "spi_48m",
		.id		= 1,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_SPI1_48,
	}, {
		.name		= "48m",
		.id		= 0,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_MMC0_48,
	}, {
		.name		= "48m",
		.id		= 1,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_MMC1_48,
	}, {
		.name		= "48m",
		.id		= 2,
		.parent		= &clk_48m,
		.enable		= s3c64xx_sclk_ctrl,
		.ctrlbit	= S3C_CLKCON_SCLK_MMC2_48,
	}, {
		.name		= "dma0",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_DMA0,
	}, {
		.name		= "dma1",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_DMA1,
	},
};

static struct clk init_clocks[] = {
	{
		.name		= "lcd",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_LCD,
	}, {
		.name		= "gpio",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_GPIO,
	}, {
		.name		= "usb-host",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_UHOST,
	}, {
		.name		= "hsmmc",
		.id		= 0,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_HSMMC0,
	}, {
		.name		= "hsmmc",
		.id		= 1,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_HSMMC1,
	}, {
		.name		= "hsmmc",
		.id		= 2,
		.parent		= &clk_h,
		.enable		= s3c64xx_hclk_ctrl,
		.ctrlbit	= S3C_CLKCON_HCLK_HSMMC2,
	}, {
		.name		= "timers",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_PWM,
	}, {
		.name		= "uart",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART0,
	}, {
		.name		= "uart",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART1,
	}, {
		.name		= "uart",
		.id		= 2,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART2,
	}, {
		.name		= "uart",
		.id		= 3,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_UART3,
	}, {
		.name		= "rtc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c64xx_pclk_ctrl,
		.ctrlbit	= S3C_CLKCON_PCLK_RTC,
	}, {
		.name		= "watchdog",
		.id		= -1,
		.parent		= &clk_p,
		.ctrlbit	= S3C_CLKCON_PCLK_WDT,
	}, {
		.name		= "ac97",
		.id		= -1,
		.parent		= &clk_p,
		.ctrlbit	= S3C_CLKCON_PCLK_AC97,
	}
};


static struct clk clk_fout_apll = {
	.name		= "fout_apll",
	.id		= -1,
};

static struct clk *clk_src_apll_list[] = {
	[0] = &clk_fin_apll,
	[1] = &clk_fout_apll,
};

static struct clksrc_sources clk_src_apll = {
	.sources	= clk_src_apll_list,
	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
};

static struct clksrc_clk clk_mout_apll = {
	.clk	= {
		.name		= "mout_apll",
		.id		= -1,
	},
	.reg_src	= { .reg = S3C_CLK_SRC, .shift = 0, .size = 1  },
	.sources	= &clk_src_apll,
};

static struct clk *clk_src_epll_list[] = {
	[0] = &clk_fin_epll,
	[1] = &clk_fout_epll,
};

static struct clksrc_sources clk_src_epll = {
	.sources	= clk_src_epll_list,
	.nr_sources	= ARRAY_SIZE(clk_src_epll_list),
};

static struct clksrc_clk clk_mout_epll = {
	.clk	= {
		.name		= "mout_epll",
		.id		= -1,
	},
	.reg_src	= { .reg = S3C_CLK_SRC, .shift = 2, .size = 1  },
	.sources	= &clk_src_epll,
};

static struct clk *clk_src_mpll_list[] = {
	[0] = &clk_fin_mpll,
	[1] = &clk_fout_mpll,
};

static struct clksrc_sources clk_src_mpll = {
	.sources	= clk_src_mpll_list,
	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),
};

static struct clksrc_clk clk_mout_mpll = {
	.clk = {
		.name		= "mout_mpll",
		.id		= -1,
	},
	.reg_src	= { .reg = S3C_CLK_SRC, .shift = 1, .size = 1  },
	.sources	= &clk_src_mpll,
};

static unsigned int armclk_mask;

static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);
	u32 clkdiv;

	/* divisor mask starts at bit0, so no need to shift */
	clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;

	return rate / (clkdiv + 1);
}

static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
						unsigned long rate)
{
	unsigned long parent = clk_get_rate(clk->parent);
	u32 div;

	if (parent < rate)
		return parent;

	div = (parent / rate) - 1;
	if (div > armclk_mask)
		div = armclk_mask;

	return parent / (div + 1);
}

static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long parent = clk_get_rate(clk->parent);
	u32 div;
	u32 val;

	if (rate < parent / (armclk_mask + 1))
		return -EINVAL;

	rate = clk_round_rate(clk, rate);
	div = clk_get_rate(clk->parent) / rate;

	val = __raw_readl(S3C_CLK_DIV0);
	val &= ~armclk_mask;
	val |= (div - 1);
	__raw_writel(val, S3C_CLK_DIV0);

	return 0;

}

static struct clk clk_arm = {
	.name		= "armclk",
	.id		= -1,
	.parent		= &clk_mout_apll.clk,
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c64xx_clk_arm_get_rate,
		.set_rate	= s3c64xx_clk_arm_set_rate,
		.round_rate	= s3c64xx_clk_arm_round_rate,
	},
};

static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);

	printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);

	if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
		rate /= 2;

	return rate;
}

static struct clk_ops clk_dout_ops = {
	.get_rate	= s3c64xx_clk_doutmpll_get_rate,
};

static struct clk clk_dout_mpll = {
	.name		= "dout_mpll",
	.id		= -1,
	.parent		= &clk_mout_mpll.clk,
	.ops		= &clk_dout_ops,
};

static struct clk *clkset_spi_mmc_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	&clk_fin_epll,
	&clk_27m,
};

static struct clksrc_sources clkset_spi_mmc = {
	.sources	= clkset_spi_mmc_list,
	.nr_sources	= ARRAY_SIZE(clkset_spi_mmc_list),
};

static struct clk *clkset_irda_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	NULL,
	&clk_27m,
};

static struct clksrc_sources clkset_irda = {
	.sources	= clkset_irda_list,
	.nr_sources	= ARRAY_SIZE(clkset_irda_list),
};

static struct clk *clkset_uart_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	NULL,
	NULL
};

static struct clksrc_sources clkset_uart = {
	.sources	= clkset_uart_list,
	.nr_sources	= ARRAY_SIZE(clkset_uart_list),
};

static struct clk *clkset_uhost_list[] = {
	&clk_48m,
	&clk_mout_epll.clk,
	&clk_dout_mpll,
	&clk_fin_epll,
};

static struct clksrc_sources clkset_uhost = {
	.sources	= clkset_uhost_list,
	.nr_sources	= ARRAY_SIZE(clkset_uhost_list),
};

/* The peripheral clocks are all controlled via clocksource followed
 * by an optional divider and gate stage. We currently roll this into
 * one clock which hides the intermediate clock from the mux.
 *
 * Note, the JPEG clock can only be an even divider...
 *
 * The scaler and LCD clocks depend on the S3C64XX version, and also
 * have a common parent divisor so are not included here.
 */

/* clocks that feed other parts of the clock source tree */

static struct clk clk_iis_cd0 = {
	.name		= "iis_cdclk0",
	.id		= -1,
};

static struct clk clk_iis_cd1 = {
	.name		= "iis_cdclk1",
	.id		= -1,
};

static struct clk clk_iisv4_cd = {
	.name		= "iis_cdclk_v4",
	.id		= -1,
};

static struct clk clk_pcm_cd = {
	.name		= "pcm_cdclk",
	.id		= -1,
};

static struct clk *clkset_audio0_list[] = {
	[0] = &clk_mout_epll.clk,
	[1] = &clk_dout_mpll,
	[2] = &clk_fin_epll,
	[3] = &clk_iis_cd0,
	[4] = &clk_pcm_cd,
};

static struct clksrc_sources clkset_audio0 = {
	.sources	= clkset_audio0_list,
	.nr_sources	= ARRAY_SIZE(clkset_audio0_list),
};

static struct clk *clkset_audio1_list[] = {
	[0] = &clk_mout_epll.clk,
	[1] = &clk_dout_mpll,
	[2] = &clk_fin_epll,
	[3] = &clk_iis_cd1,
	[4] = &clk_pcm_cd,
};

static struct clksrc_sources clkset_audio1 = {
	.sources	= clkset_audio1_list,
	.nr_sources	= ARRAY_SIZE(clkset_audio1_list),
};

static struct clk *clkset_camif_list[] = {
	&clk_h2,
};

static struct clksrc_sources clkset_camif = {
	.sources	= clkset_camif_list,
	.nr_sources	= ARRAY_SIZE(clkset_camif_list),
};

static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "mmc_bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_MMC0,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "mmc_bus",
			.id		= 1,
			.ctrlbit        = S3C_CLKCON_SCLK_MMC1,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "mmc_bus",
			.id		= 2,
			.ctrlbit        = S3C_CLKCON_SCLK_MMC2,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
		.reg_div 	= { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "usb-bus-host",
			.id		= -1,
			.ctrlbit        = S3C_CLKCON_SCLK_UHOST,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src 	= { .reg = S3C_CLK_SRC, .shift = 5, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },
		.sources	= &clkset_uhost,
	}, {
		.clk	= {
			.name		= "uclk1",
			.id		= -1,
			.ctrlbit        = S3C_CLKCON_SCLK_UART,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
		.sources	= &clkset_uart,
	}, {
/* Where does UCLK0 come from? */
		.clk	= {
			.name		= "spi-bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_SPI0,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 14, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "spi-bus",
			.id		= 1,
			.ctrlbit        = S3C_CLKCON_SCLK_SPI1,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 16, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4  },
		.sources	= &clkset_spi_mmc,
	}, {
		.clk	= {
			.name		= "audio-bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 7, .size = 3  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4  },
		.sources	= &clkset_audio0,
	}, {
		.clk	= {
			.name		= "audio-bus",
			.id		= 1,
			.ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 10, .size = 3  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4  },
		.sources	= &clkset_audio1,
	}, {
		.clk	= {
			.name		= "irda-bus",
			.id		= 0,
			.ctrlbit        = S3C_CLKCON_SCLK_IRDA,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 24, .size = 2  },
		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4  },
		.sources	= &clkset_irda,
	}, {
		.clk	= {
			.name		= "camera",
			.id		= -1,
			.ctrlbit        = S3C_CLKCON_SCLK_CAM,
			.enable		= s3c64xx_sclk_ctrl,
		},
		.reg_div	= { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
		.reg_src	= { .reg = NULL, .shift = 0, .size = 0  },
		.sources	= &clkset_camif,
	},
};

/* Clock initialisation code */

static struct clksrc_clk *init_parents[] = {
	&clk_mout_apll,
	&clk_mout_epll,
	&clk_mout_mpll,
};

#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

void __init_or_cpufreq s3c6400_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk2;
	unsigned long pclk;
	unsigned long epll;
	unsigned long apll;
	unsigned long mpll;
	unsigned int ptr;
	u32 clkdiv0;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	clkdiv0 = __raw_readl(S3C_CLK_DIV0);
	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	/* For now assume the mux always selects the crystal */
	clk_ext_xtal_mux.parent = xtal_clk;

	epll = s3c6400_get_epll(xtal);
	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));

	fclk = mpll;

	printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
	       apll, mpll, epll);

	hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
	hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
	pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);

	printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
	       hclk2, hclk, pclk);

	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_apll.rate = apll;

	clk_h2.rate = hclk2;
	clk_h.rate = hclk;
	clk_p.rate = pclk;
	clk_f.rate = fclk;

	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
		s3c_set_clksrc(init_parents[ptr], true);

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}

static struct clk *clks1[] __initdata = {
	&clk_ext_xtal_mux,
	&clk_iis_cd0,
	&clk_iis_cd1,
	&clk_iisv4_cd,
	&clk_pcm_cd,
	&clk_mout_epll.clk,
	&clk_mout_mpll.clk,
	&clk_dout_mpll,
	&clk_arm,
};

static struct clk *clks[] __initdata = {
	&clk_ext,
	&clk_epll,
	&clk_27m,
	&clk_48m,
	&clk_h2,
};

/**
 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
 * @xtal: The rate for the clock crystal feeding the PLLs.
 * @armclk_divlimit: Divisor mask for ARMCLK.
 *
 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
 * as ARMCLK as well as the necessary parent clocks.
 *
 * This call does not setup the clocks, which is left to the
 * s3c6400_setup_clocks() call which may be needed by the cpufreq
 * or resume code to re-set the clocks if the bootloader has changed
 * them.
 */
void __init s3c64xx_register_clocks(unsigned long xtal, 
				    unsigned armclk_divlimit)
{
	struct clk *clkp;
	int ret;
	int ptr;

	armclk_mask = armclk_divlimit;

	s3c24xx_register_baseclocks(xtal);
	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	clkp = init_clocks_disable;
	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {

		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}

		(clkp->enable)(clkp, 0);
	}

	s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	s3c_pwmclk_init();
}
Commit	Line	Data
4b31d8b2 BD	1	/* linux/arch/arm/plat-s3c64xx/clock.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C64XX Base clock support
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/ioport.h>
62acb2f8 BD	19	#include <linux/clk.h>
62acb2f8 BD	20	#include <linux/err.h>
4b31d8b2 BD	21	#include <linux/io.h>
	22
	23	#include <mach/hardware.h>
	24	#include <mach/map.h>
	25
3501c9ae BD	26	#include <mach/regs-sys.h>
3501c9ae BD	27	#include <mach/regs-clock.h>
f7be9aba BD	28	#include <mach/pll.h>
f7be9aba BD	29
4b31d8b2 BD	30	#include <plat/cpu.h>
4b31d8b2 BD	31	#include <plat/devs.h>
62acb2f8	32	#include <plat/cpu-freq.h>
4b31d8b2	33	#include <plat/clock.h>
62acb2f8 BD	34	#include <plat/clock-clksrc.h>
	35
	36	/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
	37	* ext_xtal_mux for want of an actual name from the manual.
	38	*/
	39
	40	static struct clk clk_ext_xtal_mux = {
	41	.name = "ext_xtal",
	42	.id = -1,
	43	};
	44
	45	#define clk_fin_apll clk_ext_xtal_mux
	46	#define clk_fin_mpll clk_ext_xtal_mux
	47	#define clk_fin_epll clk_ext_xtal_mux
	48
	49	#define clk_fout_mpll clk_mpll
	50	#define clk_fout_epll clk_epll
4b31d8b2	51
a03f7daf WA	52	struct clk clk_h2 = {
	53	.name = "hclk2",
	54	.id = -1,
	55	.rate = 0,
	56	};
	57
4b31d8b2 BD	58	struct clk clk_27m = {
	59	.name = "clk_27m",
	60	.id = -1,
	61	.rate = 27000000,
	62	};
	63
3627379f BD	64	static int clk_48m_ctrl(struct clk *clk, int enable)
	65	{
	66	unsigned long flags;
	67	u32 val;
	68
	69	/* can't rely on clock lock, this register has other usages */
	70	local_irq_save(flags);
	71
	72	val = __raw_readl(S3C64XX_OTHERS);
	73	if (enable)
	74	val \|= S3C64XX_OTHERS_USBMASK;
	75	else
	76	val &= ~S3C64XX_OTHERS_USBMASK;
	77
	78	__raw_writel(val, S3C64XX_OTHERS);
	79	local_irq_restore(flags);
	80
	81	return 0;
	82	}
	83
4b31d8b2 BD	84	struct clk clk_48m = {
	85	.name = "clk_48m",
	86	.id = -1,
	87	.rate = 48000000,
3627379f	88	.enable = clk_48m_ctrl,
4b31d8b2 BD	89	};
	90
	91	static int inline s3c64xx_gate(void __iomem *reg,
	92	struct clk *clk,
	93	int enable)
	94	{
	95	unsigned int ctrlbit = clk->ctrlbit;
	96	u32 con;
	97
	98	con = __raw_readl(reg);
	99
	100	if (enable)
	101	con \|= ctrlbit;
	102	else
	103	con &= ~ctrlbit;
	104
	105	__raw_writel(con, reg);
	106	return 0;
	107	}
	108
	109	static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
	110	{
	111	return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
	112	}
	113
	114	static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
	115	{
	116	return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
	117	}
	118
cf18acf0	119	int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
4b31d8b2 BD	120	{
	121	return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
	122	}
	123
	124	static struct clk init_clocks_disable[] = {
	125	{
	126	.name = "nand",
	127	.id = -1,
	128	.parent = &clk_h,
	129	}, {
	130	.name = "adc",
	131	.id = -1,
	132	.parent = &clk_p,
	133	.enable = s3c64xx_pclk_ctrl,
	134	.ctrlbit = S3C_CLKCON_PCLK_TSADC,
	135	}, {
	136	.name = "i2c",
	137	.id = -1,
	138	.parent = &clk_p,
	139	.enable = s3c64xx_pclk_ctrl,
	140	.ctrlbit = S3C_CLKCON_PCLK_IIC,
	141	}, {
	142	.name = "iis",
	143	.id = 0,
	144	.parent = &clk_p,
	145	.enable = s3c64xx_pclk_ctrl,
	146	.ctrlbit = S3C_CLKCON_PCLK_IIS0,
	147	}, {
	148	.name = "iis",
	149	.id = 1,
	150	.parent = &clk_p,
	151	.enable = s3c64xx_pclk_ctrl,
	152	.ctrlbit = S3C_CLKCON_PCLK_IIS1,
	153	}, {
2e5070bc JB	154	#ifdef CONFIG_CPU_S3C6410
	155	.name = "iis",
	156	.id = -1, /* There's only one IISv4 port */
	157	.parent = &clk_p,
	158	.enable = s3c64xx_pclk_ctrl,
	159	.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
	160	}, {
	161	#endif
4b31d8b2 BD	162	.name = "spi",
	163	.id = 0,
	164	.parent = &clk_p,
	165	.enable = s3c64xx_pclk_ctrl,
	166	.ctrlbit = S3C_CLKCON_PCLK_SPI0,
	167	}, {
	168	.name = "spi",
	169	.id = 1,
	170	.parent = &clk_p,
	171	.enable = s3c64xx_pclk_ctrl,
	172	.ctrlbit = S3C_CLKCON_PCLK_SPI1,
87315a80 JB	173	}, {
	174	.name = "spi_48m",
	175	.id = 0,
	176	.parent = &clk_48m,
	177	.enable = s3c64xx_sclk_ctrl,
	178	.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
	179	}, {
	180	.name = "spi_48m",
	181	.id = 1,
	182	.parent = &clk_48m,
	183	.enable = s3c64xx_sclk_ctrl,
	184	.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
4b31d8b2 BD	185	}, {
	186	.name = "48m",
	187	.id = 0,
	188	.parent = &clk_48m,
	189	.enable = s3c64xx_sclk_ctrl,
	190	.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
	191	}, {
	192	.name = "48m",
	193	.id = 1,
	194	.parent = &clk_48m,
	195	.enable = s3c64xx_sclk_ctrl,
	196	.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
	197	}, {
	198	.name = "48m",
	199	.id = 2,
	200	.parent = &clk_48m,
	201	.enable = s3c64xx_sclk_ctrl,
	202	.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
8f1ecf1d MB	203	}, {
	204	.name = "dma0",
	205	.id = -1,
	206	.parent = &clk_h,
	207	.enable = s3c64xx_hclk_ctrl,
	208	.ctrlbit = S3C_CLKCON_HCLK_DMA0,
	209	}, {
	210	.name = "dma1",
	211	.id = -1,
	212	.parent = &clk_h,
	213	.enable = s3c64xx_hclk_ctrl,
	214	.ctrlbit = S3C_CLKCON_HCLK_DMA1,
4b31d8b2 BD	215	},
	216	};
	217
	218	static struct clk init_clocks[] = {
	219	{
	220	.name = "lcd",
	221	.id = -1,
	222	.parent = &clk_h,
	223	.enable = s3c64xx_hclk_ctrl,
	224	.ctrlbit = S3C_CLKCON_HCLK_LCD,
	225	}, {
	226	.name = "gpio",
	227	.id = -1,
	228	.parent = &clk_p,
	229	.enable = s3c64xx_pclk_ctrl,
	230	.ctrlbit = S3C_CLKCON_PCLK_GPIO,
	231	}, {
	232	.name = "usb-host",
	233	.id = -1,
	234	.parent = &clk_h,
	235	.enable = s3c64xx_hclk_ctrl,
386f4351	236	.ctrlbit = S3C_CLKCON_HCLK_UHOST,
4b31d8b2 BD	237	}, {
	238	.name = "hsmmc",
	239	.id = 0,
	240	.parent = &clk_h,
	241	.enable = s3c64xx_hclk_ctrl,
	242	.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
	243	}, {
	244	.name = "hsmmc",
	245	.id = 1,
	246	.parent = &clk_h,
	247	.enable = s3c64xx_hclk_ctrl,
	248	.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
	249	}, {
	250	.name = "hsmmc",
	251	.id = 2,
	252	.parent = &clk_h,
	253	.enable = s3c64xx_hclk_ctrl,
	254	.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
	255	}, {
	256	.name = "timers",
	257	.id = -1,
	258	.parent = &clk_p,
	259	.enable = s3c64xx_pclk_ctrl,
	260	.ctrlbit = S3C_CLKCON_PCLK_PWM,
	261	}, {
	262	.name = "uart",
	263	.id = 0,
	264	.parent = &clk_p,
	265	.enable = s3c64xx_pclk_ctrl,
	266	.ctrlbit = S3C_CLKCON_PCLK_UART0,
	267	}, {
	268	.name = "uart",
	269	.id = 1,
	270	.parent = &clk_p,
	271	.enable = s3c64xx_pclk_ctrl,
	272	.ctrlbit = S3C_CLKCON_PCLK_UART1,
	273	}, {
	274	.name = "uart",
	275	.id = 2,
	276	.parent = &clk_p,
	277	.enable = s3c64xx_pclk_ctrl,
	278	.ctrlbit = S3C_CLKCON_PCLK_UART2,
	279	}, {
	280	.name = "uart",
	281	.id = 3,
	282	.parent = &clk_p,
	283	.enable = s3c64xx_pclk_ctrl,
	284	.ctrlbit = S3C_CLKCON_PCLK_UART3,
	285	}, {
	286	.name = "rtc",
	287	.id = -1,
	288	.parent = &clk_p,
	289	.enable = s3c64xx_pclk_ctrl,
	290	.ctrlbit = S3C_CLKCON_PCLK_RTC,
	291	}, {
	292	.name = "watchdog",
	293	.id = -1,
	294	.parent = &clk_p,
	295	.ctrlbit = S3C_CLKCON_PCLK_WDT,
	296	}, {
	297	.name = "ac97",
	298	.id = -1,
	299	.parent = &clk_p,
	300	.ctrlbit = S3C_CLKCON_PCLK_AC97,
301	}
302	};
303
62acb2f8 BD	304
	305	static struct clk clk_fout_apll = {
	306	.name = "fout_apll",
	307	.id = -1,
	308	};
	309
	310	static struct clk *clk_src_apll_list[] = {
	311	[0] = &clk_fin_apll,
	312	[1] = &clk_fout_apll,
	313	};
	314
	315	static struct clksrc_sources clk_src_apll = {
	316	.sources = clk_src_apll_list,
	317	.nr_sources = ARRAY_SIZE(clk_src_apll_list),
	318	};
	319
	320	static struct clksrc_clk clk_mout_apll = {
	321	.clk = {
	322	.name = "mout_apll",
	323	.id = -1,
	324	},
	325	.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
	326	.sources = &clk_src_apll,
	327	};
	328
	329	static struct clk *clk_src_epll_list[] = {
	330	[0] = &clk_fin_epll,
	331	[1] = &clk_fout_epll,
	332	};
	333
	334	static struct clksrc_sources clk_src_epll = {
	335	.sources = clk_src_epll_list,
	336	.nr_sources = ARRAY_SIZE(clk_src_epll_list),
	337	};
	338
	339	static struct clksrc_clk clk_mout_epll = {
	340	.clk = {
	341	.name = "mout_epll",
	342	.id = -1,
	343	},
	344	.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
	345	.sources = &clk_src_epll,
	346	};
	347
	348	static struct clk *clk_src_mpll_list[] = {
	349	[0] = &clk_fin_mpll,
	350	[1] = &clk_fout_mpll,
	351	};
	352
	353	static struct clksrc_sources clk_src_mpll = {
	354	.sources = clk_src_mpll_list,
	355	.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
	356	};
	357
	358	static struct clksrc_clk clk_mout_mpll = {
	359	.clk = {
	360	.name = "mout_mpll",
	361	.id = -1,
	362	},
	363	.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
	364	.sources = &clk_src_mpll,
	365	};
	366
	367	static unsigned int armclk_mask;
368
369	static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
370	{
371	unsigned long rate = clk_get_rate(clk->parent);
372	u32 clkdiv;
373
374	/* divisor mask starts at bit0, so no need to shift */
375	clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
376
377	return rate / (clkdiv + 1);
378	}
379
380	static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
381	unsigned long rate)
382	{
383	unsigned long parent = clk_get_rate(clk->parent);
384	u32 div;
385
386	if (parent < rate)
387	return parent;
388
389	div = (parent / rate) - 1;
390	if (div > armclk_mask)
391	div = armclk_mask;
392
393	return parent / (div + 1);
394	}
395
396	static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
397	{
398	unsigned long parent = clk_get_rate(clk->parent);
399	u32 div;
400	u32 val;
401
402	if (rate < parent / (armclk_mask + 1))
403	return -EINVAL;
404
405	rate = clk_round_rate(clk, rate);
406	div = clk_get_rate(clk->parent) / rate;
407
408	val = __raw_readl(S3C_CLK_DIV0);
409	val &= ~armclk_mask;
410	val \|= (div - 1);
411	__raw_writel(val, S3C_CLK_DIV0);
412
413	return 0;
414
415	}
416
417	static struct clk clk_arm = {
418	.name = "armclk",
419	.id = -1,
420	.parent = &clk_mout_apll.clk,
421	.ops = &(struct clk_ops) {
422	.get_rate = s3c64xx_clk_arm_get_rate,
423	.set_rate = s3c64xx_clk_arm_set_rate,
424	.round_rate = s3c64xx_clk_arm_round_rate,
425	},
426	};
427
428	static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
429	{
430	unsigned long rate = clk_get_rate(clk->parent);
431
432	printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
433
434	if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
435	rate /= 2;
436
437	return rate;
438	}
439
440	static struct clk_ops clk_dout_ops = {
441	.get_rate = s3c64xx_clk_doutmpll_get_rate,
442	};
443
444	static struct clk clk_dout_mpll = {
445	.name = "dout_mpll",
446	.id = -1,
447	.parent = &clk_mout_mpll.clk,
448	.ops = &clk_dout_ops,
449	};
450
451	static struct clk *clkset_spi_mmc_list[] = {
452	&clk_mout_epll.clk,
453	&clk_dout_mpll,
454	&clk_fin_epll,
455	&clk_27m,
456	};
457
458	static struct clksrc_sources clkset_spi_mmc = {
459	.sources = clkset_spi_mmc_list,
460	.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
461	};
462
463	static struct clk *clkset_irda_list[] = {
464	&clk_mout_epll.clk,
465	&clk_dout_mpll,
466	NULL,
467	&clk_27m,
468	};
469
470	static struct clksrc_sources clkset_irda = {
471	.sources = clkset_irda_list,
472	.nr_sources = ARRAY_SIZE(clkset_irda_list),
473	};
474
475	static struct clk *clkset_uart_list[] = {
476	&clk_mout_epll.clk,
477	&clk_dout_mpll,
478	NULL,
479	NULL
480	};
481
482	static struct clksrc_sources clkset_uart = {
483	.sources = clkset_uart_list,
484	.nr_sources = ARRAY_SIZE(clkset_uart_list),
485	};
486
487	static struct clk *clkset_uhost_list[] = {
488	&clk_48m,
489	&clk_mout_epll.clk,
490	&clk_dout_mpll,
491	&clk_fin_epll,
492	};
493
494	static struct clksrc_sources clkset_uhost = {
495	.sources = clkset_uhost_list,
496	.nr_sources = ARRAY_SIZE(clkset_uhost_list),
497	};
498
499	/* The peripheral clocks are all controlled via clocksource followed
500	* by an optional divider and gate stage. We currently roll this into
501	* one clock which hides the intermediate clock from the mux.
502	*
503	* Note, the JPEG clock can only be an even divider...
504	*
505	* The scaler and LCD clocks depend on the S3C64XX version, and also
506	* have a common parent divisor so are not included here.
507	*/
508
509	/* clocks that feed other parts of the clock source tree */
510
511	static struct clk clk_iis_cd0 = {
512	.name = "iis_cdclk0",
513	.id = -1,
514	};
515
516	static struct clk clk_iis_cd1 = {
517	.name = "iis_cdclk1",
518	.id = -1,
519	};
520
bc8eb1e2 JB	521	static struct clk clk_iisv4_cd = {
	522	.name = "iis_cdclk_v4",
	523	.id = -1,
	524	};
	525
62acb2f8 BD	526	static struct clk clk_pcm_cd = {
	527	.name = "pcm_cdclk",
	528	.id = -1,
	529	};
	530
	531	static struct clk *clkset_audio0_list[] = {
	532	[0] = &clk_mout_epll.clk,
	533	[1] = &clk_dout_mpll,
	534	[2] = &clk_fin_epll,
	535	[3] = &clk_iis_cd0,
	536	[4] = &clk_pcm_cd,
	537	};
	538
	539	static struct clksrc_sources clkset_audio0 = {
	540	.sources = clkset_audio0_list,
	541	.nr_sources = ARRAY_SIZE(clkset_audio0_list),
	542	};
	543
	544	static struct clk *clkset_audio1_list[] = {
	545	[0] = &clk_mout_epll.clk,
	546	[1] = &clk_dout_mpll,
	547	[2] = &clk_fin_epll,
	548	[3] = &clk_iis_cd1,
	549	[4] = &clk_pcm_cd,
	550	};
	551
	552	static struct clksrc_sources clkset_audio1 = {
	553	.sources = clkset_audio1_list,
	554	.nr_sources = ARRAY_SIZE(clkset_audio1_list),
	555	};
	556
	557	static struct clk *clkset_camif_list[] = {
	558	&clk_h2,
	559	};
	560
	561	static struct clksrc_sources clkset_camif = {
	562	.sources = clkset_camif_list,
	563	.nr_sources = ARRAY_SIZE(clkset_camif_list),
	564	};
	565
	566	static struct clksrc_clk clksrcs[] = {
	567	{
	568	.clk = {
	569	.name = "mmc_bus",
	570	.id = 0,
	571	.ctrlbit = S3C_CLKCON_SCLK_MMC0,
	572	.enable = s3c64xx_sclk_ctrl,
	573	},
	574	.reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
	575	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
	576	.sources = &clkset_spi_mmc,
	577	}, {
	578	.clk = {
	579	.name = "mmc_bus",
	580	.id = 1,
	581	.ctrlbit = S3C_CLKCON_SCLK_MMC1,
	582	.enable = s3c64xx_sclk_ctrl,
	583	},
	584	.reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
	585	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
	586	.sources = &clkset_spi_mmc,
	587	}, {
	588	.clk = {
	589	.name = "mmc_bus",
590	.id = 2,
591	.ctrlbit = S3C_CLKCON_SCLK_MMC2,
592	.enable = s3c64xx_sclk_ctrl,
593	},
594	.reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
595	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
596	.sources = &clkset_spi_mmc,
597	}, {
598	.clk = {
599	.name = "usb-bus-host",
600	.id = -1,
601	.ctrlbit = S3C_CLKCON_SCLK_UHOST,
602	.enable = s3c64xx_sclk_ctrl,
603	},
604	.reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
605	.reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
606	.sources = &clkset_uhost,
607	}, {
608	.clk = {
609	.name = "uclk1",
610	.id = -1,
611	.ctrlbit = S3C_CLKCON_SCLK_UART,
612	.enable = s3c64xx_sclk_ctrl,
613	},
614	.reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
615	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
616	.sources = &clkset_uart,
617	}, {
618	/* Where does UCLK0 come from? */
619	.clk = {
620	.name = "spi-bus",
621	.id = 0,
622	.ctrlbit = S3C_CLKCON_SCLK_SPI0,
623	.enable = s3c64xx_sclk_ctrl,
624	},
625	.reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
626	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
627	.sources = &clkset_spi_mmc,
628	}, {
629	.clk = {
630	.name = "spi-bus",
631	.id = 1,
632	.ctrlbit = S3C_CLKCON_SCLK_SPI1,
633	.enable = s3c64xx_sclk_ctrl,
634	},
635	.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
636	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
637	.sources = &clkset_spi_mmc,
638	}, {
639	.clk = {
640	.name = "audio-bus",
641	.id = 0,
642	.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
643	.enable = s3c64xx_sclk_ctrl,
644	},
645	.reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
646	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
647	.sources = &clkset_audio0,
648	}, {
649	.clk = {
650	.name = "audio-bus",
651	.id = 1,
652	.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
653	.enable = s3c64xx_sclk_ctrl,
654	},
655	.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
656	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
657	.sources = &clkset_audio1,
658	}, {
659	.clk = {
660	.name = "irda-bus",
661	.id = 0,
662	.ctrlbit = S3C_CLKCON_SCLK_IRDA,
663	.enable = s3c64xx_sclk_ctrl,
664	},
665	.reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
666	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
667	.sources = &clkset_irda,
668	}, {
669	.clk = {
670	.name = "camera",
671	.id = -1,
672	.ctrlbit = S3C_CLKCON_SCLK_CAM,
673	.enable = s3c64xx_sclk_ctrl,
674	},
675	.reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
676	.reg_src = { .reg = NULL, .shift = 0, .size = 0 },
677	.sources = &clkset_camif,
678	},
679	};
680
681	/* Clock initialisation code */
682
683	static struct clksrc_clk *init_parents[] = {
684	&clk_mout_apll,
685	&clk_mout_epll,
686	&clk_mout_mpll,
687	};
688
689	#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
690
691	void __init_or_cpufreq s3c6400_setup_clocks(void)
692	{
693	struct clk *xtal_clk;
694	unsigned long xtal;
695	unsigned long fclk;
696	unsigned long hclk;
697	unsigned long hclk2;
698	unsigned long pclk;
699	unsigned long epll;
700	unsigned long apll;
701	unsigned long mpll;
702	unsigned int ptr;
703	u32 clkdiv0;
704
705	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
706
707	clkdiv0 = __raw_readl(S3C_CLK_DIV0);
708	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
709
710	xtal_clk = clk_get(NULL, "xtal");
711	BUG_ON(IS_ERR(xtal_clk));
712
713	xtal = clk_get_rate(xtal_clk);
714	clk_put(xtal_clk);
715
716	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
717
718	/* For now assume the mux always selects the crystal */
719	clk_ext_xtal_mux.parent = xtal_clk;
720
721	epll = s3c6400_get_epll(xtal);
722	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
723	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
724
725	fclk = mpll;
726
727	printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
728	apll, mpll, epll);
729
730	hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
731	hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
732	pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
733
734	printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
735	hclk2, hclk, pclk);
736
737	clk_fout_mpll.rate = mpll;
738	clk_fout_epll.rate = epll;
739	clk_fout_apll.rate = apll;
740
741	clk_h2.rate = hclk2;
742	clk_h.rate = hclk;
743	clk_p.rate = pclk;
744	clk_f.rate = fclk;
745
746	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
747	s3c_set_clksrc(init_parents[ptr], true);
748
749	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
750	s3c_set_clksrc(&clksrcs[ptr], true);
751	}
752
753	static struct clk *clks1[] __initdata = {
754	&clk_ext_xtal_mux,
755	&clk_iis_cd0,
756	&clk_iis_cd1,
bc8eb1e2	757	&clk_iisv4_cd,
62acb2f8 BD	758	&clk_pcm_cd,
	759	&clk_mout_epll.clk,
	760	&clk_mout_mpll.clk,
	761	&clk_dout_mpll,
	762	&clk_arm,
	763	};
	764
55bf9267 BD	765	static struct clk *clks[] __initdata = {
	766	&clk_ext,
	767	&clk_epll,
	768	&clk_27m,
	769	&clk_48m,
	770	&clk_h2,
	771	};
	772
62acb2f8	773	/**
55bf9267 BD	774	* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
	775	* @xtal: The rate for the clock crystal feeding the PLLs.
	776	* @armclk_divlimit: Divisor mask for ARMCLK.
62acb2f8	777	*
55bf9267 BD	778	* Register the clocks for the S3C6400 and S3C6410 SoC range, such
55bf9267 BD	779	* as ARMCLK as well as the necessary parent clocks.
62acb2f8 BD	780	*
	781	* This call does not setup the clocks, which is left to the
	782	* s3c6400_setup_clocks() call which may be needed by the cpufreq
	783	* or resume code to re-set the clocks if the bootloader has changed
	784	* them.
	785	*/
55bf9267 BD	786	void __init s3c64xx_register_clocks(unsigned long xtal,
55bf9267 BD	787	unsigned armclk_divlimit)
62acb2f8 BD	788	{
	789	struct clk *clkp;
	790	int ret;
	791	int ptr;
	792
	793	armclk_mask = armclk_divlimit;
	794
55bf9267	795	s3c24xx_register_baseclocks(xtal);
4b31d8b2	796	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
55bf9267	797
1d9f13c4	798	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
4b31d8b2 BD	799
	800	clkp = init_clocks_disable;
	801	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
	802
	803	ret = s3c24xx_register_clock(clkp);
	804	if (ret < 0) {
	805	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	806	clkp->name, ret);
	807	}
	808
	809	(clkp->enable)(clkp, 0);
	810	}
9d325f23	811
55bf9267 BD	812	s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
55bf9267 BD	813	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
9d325f23	814	s3c_pwmclk_init();
4b31d8b2	815	}