[deliverable/linux.git] / arch / arm / mach-s3c64xx / common.c

/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * Common Codes for S3C64XX machines
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/irqchip/arm-vic.h>
#include <clocksource/samsung_pwm.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include <mach/map.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>

#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/gpio-cfg.h>
#include <plat/irq-uart.h>
#include <plat/irq-vic-timer.h>
#include <plat/pwm-core.h>
#include <plat/regs-irqtype.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>

#include "common.h"

/* uart registration process */

static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
}

/* table of supported CPUs */

static const char name_s3c6400[] = "S3C6400";
static const char name_s3c6410[] = "S3C6410";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= S3C6400_CPU_ID,
		.idmask		= S3C64XX_CPU_MASK,
		.map_io		= s3c6400_map_io,
		.init_clocks	= s3c6400_init_clocks,
		.init_uarts	= s3c64xx_init_uarts,
		.init		= s3c6400_init,
		.name		= name_s3c6400,
	}, {
		.idcode		= S3C6410_CPU_ID,
		.idmask		= S3C64XX_CPU_MASK,
		.map_io		= s3c6410_map_io,
		.init_clocks	= s3c6410_init_clocks,
		.init_uarts	= s3c64xx_init_uarts,
		.init		= s3c6410_init,
		.name		= name_s3c6410,
	},
};

/* minimal IO mapping */

/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
#define UART_OFFS (S3C_PA_UART & 0xfffff)

static struct map_desc s3c_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(S3C64XX_PA_SYSCON),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_MEM,
		.pfn		= __phys_to_pfn(S3C64XX_PA_SROM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)(S3C_VA_UART + UART_OFFS),
		.pfn		= __phys_to_pfn(S3C_PA_UART),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)VA_VIC0,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC0),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)VA_VIC1,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC1),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(S3C_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_GPIO,
		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(S3C64XX_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
		.length		= SZ_1K,
		.type		= MT_DEVICE,
	},
};

static struct bus_type s3c64xx_subsys = {
	.name		= "s3c64xx-core",
	.dev_name	= "s3c64xx-core",
};

static struct device s3c64xx_dev = {
	.bus	= &s3c64xx_subsys,
};

static struct samsung_pwm_variant s3c64xx_pwm_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

/* read cpu identification code */

void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
{
	/* initialise the io descriptors we need for initialisation */
	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	iotable_init(mach_desc, size);

	/* detect cpu id */
	s3c64xx_init_cpu();

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));

	samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
}

static __init int s3c64xx_dev_init(void)
{
	subsys_system_register(&s3c64xx_subsys, NULL);
	return device_register(&s3c64xx_dev);
}
core_initcall(s3c64xx_dev_init);

/*
 * setup the sources the vic should advertise resume
 * for, even though it is not doing the wake
 * (set_irq_wake needs to be valid)
 */
#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_PENDN - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))

void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
	/*
	 * FIXME: there is no better place to put this at the moment
	 * (samsung_wdt_reset_init needs clocks)
	 */
	samsung_wdt_reset_init(S3C_VA_WATCHDOG);

	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);

	/* initialise the pair of VICs */
	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);

	/* add the timer sub-irqs */
	s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}

#define eint_offset(irq)	((irq) - IRQ_EINT(0))
#define eint_irq_to_bit(irq)	((u32)(1 << eint_offset(irq)))

static inline void s3c_irq_eint_mask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S3C64XX_EINT0MASK);
	mask |= (u32)data->chip_data;
	__raw_writel(mask, S3C64XX_EINT0MASK);
}

static void s3c_irq_eint_unmask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S3C64XX_EINT0MASK);
	mask &= ~((u32)data->chip_data);
	__raw_writel(mask, S3C64XX_EINT0MASK);
}

static inline void s3c_irq_eint_ack(struct irq_data *data)
{
	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
}

static void s3c_irq_eint_maskack(struct irq_data *data)
{
	/* compiler should in-line these */
	s3c_irq_eint_mask(data);
	s3c_irq_eint_ack(data);
}

static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
	int offs = eint_offset(data->irq);
	int pin, pin_val;
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;
	void __iomem *reg;

	if (offs > 27)
		return -EINVAL;

	if (offs <= 15)
		reg = S3C64XX_EINT0CON0;
	else
		reg = S3C64XX_EINT0CON1;

	switch (type) {
	case IRQ_TYPE_NONE:
		printk(KERN_WARNING "No edge setting!\n");
		break;

	case IRQ_TYPE_EDGE_RISING:
		newvalue = S3C2410_EXTINT_RISEEDGE;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S3C2410_EXTINT_FALLEDGE;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S3C2410_EXTINT_BOTHEDGE;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S3C2410_EXTINT_LOWLEV;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S3C2410_EXTINT_HILEV;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -1;
	}

	if (offs <= 15)
		shift = (offs / 2) * 4;
	else
		shift = ((offs - 16) / 2) * 4;
	mask = 0x7 << shift;

	ctrl = __raw_readl(reg);
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, reg);

	/* set the GPIO pin appropriately */

	if (offs < 16) {
		pin = S3C64XX_GPN(offs);
		pin_val = S3C_GPIO_SFN(2);
	} else if (offs < 23) {
		pin = S3C64XX_GPL(offs + 8 - 16);
		pin_val = S3C_GPIO_SFN(3);
	} else {
		pin = S3C64XX_GPM(offs - 23);
		pin_val = S3C_GPIO_SFN(3);
	}

	s3c_gpio_cfgpin(pin, pin_val);

	return 0;
}

static struct irq_chip s3c_irq_eint = {
	.name		= "s3c-eint",
	.irq_mask	= s3c_irq_eint_mask,
	.irq_unmask	= s3c_irq_eint_unmask,
	.irq_mask_ack	= s3c_irq_eint_maskack,
	.irq_ack	= s3c_irq_eint_ack,
	.irq_set_type	= s3c_irq_eint_set_type,
	.irq_set_wake	= s3c_irqext_wake,
};

/* s3c_irq_demux_eint
 *
 * This function demuxes the IRQ from the group0 external interrupts,
 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 * the specific handlers s3c_irq_demux_eintX_Y.
 */
static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
{
	u32 status = __raw_readl(S3C64XX_EINT0PEND);
	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
	unsigned int irq;

	status &= ~mask;
	status >>= start;
	status &= (1 << (end - start + 1)) - 1;

	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
		if (status & 1)
			generic_handle_irq(irq);

		status >>= 1;
	}
}

static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(0, 3);
}

static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(4, 11);
}

static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(12, 19);
}

static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(20, 27);
}

static int __init s3c64xx_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
		irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
		irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);

	return 0;
}
arch_initcall(s3c64xx_init_irq_eint);

void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
{
	if (mode != REBOOT_SOFT)
		samsung_wdt_reset();

	/* if all else fails, or mode was for soft, jump to 0 */
	soft_restart(0);
}

void __init s3c64xx_init_late(void)
{
	s3c64xx_pm_late_initcall();
}
Commit	Line	Data
b024043b KK	1	/*
	2	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
80789e79 BD	4	*
	5	* Copyright 2008 Openmoko, Inc.
	6	* Copyright 2008 Simtec Electronics
b024043b KK	7	* Ben Dooks <ben@simtec.co.uk>
b024043b KK	8	* http://armlinux.simtec.co.uk/
80789e79	9	*
b024043b	10	* Common Codes for S3C64XX machines
80789e79 BD	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
	17	#include <linux/kernel.h>
b024043b KK	18	#include <linux/init.h>
b024043b KK	19	#include <linux/module.h>
80789e79	20	#include <linux/interrupt.h>
b024043b	21	#include <linux/ioport.h>
b024043b KK	22	#include <linux/serial_core.h>
b024043b KK	23	#include <linux/platform_device.h>
7b6d864b	24	#include <linux/reboot.h>
80789e79	25	#include <linux/io.h>
b024043b KK	26	#include <linux/dma-mapping.h>
	27	#include <linux/irq.h>
	28	#include <linux/gpio.h>
9e47b8bf	29	#include <linux/irqchip/arm-vic.h>
1c161fd0	30	#include <clocksource/samsung_pwm.h>
80789e79	31
b024043b KK	32	#include <asm/mach/arch.h>
b024043b KK	33	#include <asm/mach/map.h>
9f97da78	34	#include <asm/system_misc.h>
80789e79	35
b024043b KK	36	#include <mach/map.h>
b024043b KK	37	#include <mach/hardware.h>
3501c9ae	38	#include <mach/regs-gpio.h>
80789e79	39
80789e79	40	#include <plat/cpu.h>
b024043b KK	41	#include <plat/clock.h>
b024043b KK	42	#include <plat/devs.h>
bd117bd1	43	#include <plat/pm.h>
b024043b KK	44	#include <plat/gpio-cfg.h>
	45	#include <plat/irq-uart.h>
	46	#include <plat/irq-vic-timer.h>
1c161fd0	47	#include <plat/pwm-core.h>
b024043b KK	48	#include <plat/regs-irqtype.h>
b024043b KK	49	#include <plat/regs-serial.h>
ff84ded2	50	#include <plat/watchdog-reset.h>
b024043b KK	51
	52	#include "common.h"
	53
	54	/* uart registration process */
	55
b7c9705c	56	static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
b024043b KK	57	{
	58	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
	59	}
	60
	61	/* table of supported CPUs */
	62
	63	static const char name_s3c6400[] = "S3C6400";
	64	static const char name_s3c6410[] = "S3C6410";
	65
	66	static struct cpu_table cpu_ids[] __initdata = {
	67	{
	68	.idcode = S3C6400_CPU_ID,
	69	.idmask = S3C64XX_CPU_MASK,
	70	.map_io = s3c6400_map_io,
	71	.init_clocks = s3c6400_init_clocks,
	72	.init_uarts = s3c64xx_init_uarts,
	73	.init = s3c6400_init,
	74	.name = name_s3c6400,
	75	}, {
	76	.idcode = S3C6410_CPU_ID,
	77	.idmask = S3C64XX_CPU_MASK,
	78	.map_io = s3c6410_map_io,
	79	.init_clocks = s3c6410_init_clocks,
	80	.init_uarts = s3c64xx_init_uarts,
	81	.init = s3c6410_init,
	82	.name = name_s3c6410,
	83	},
	84	};
	85
	86	/* minimal IO mapping */
	87
	88	/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
	89	#define UART_OFFS (S3C_PA_UART & 0xfffff)
	90
	91	static struct map_desc s3c_iodesc[] __initdata = {
	92	{
	93	.virtual = (unsigned long)S3C_VA_SYS,
	94	.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
	95	.length = SZ_4K,
	96	.type = MT_DEVICE,
	97	}, {
	98	.virtual = (unsigned long)S3C_VA_MEM,
	99	.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
	100	.length = SZ_4K,
	101	.type = MT_DEVICE,
	102	}, {
	103	.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
	104	.pfn = __phys_to_pfn(S3C_PA_UART),
	105	.length = SZ_4K,
	106	.type = MT_DEVICE,
	107	}, {
	108	.virtual = (unsigned long)VA_VIC0,
	109	.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
	110	.length = SZ_16K,
	111	.type = MT_DEVICE,
	112	}, {
	113	.virtual = (unsigned long)VA_VIC1,
	114	.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
	115	.length = SZ_16K,
	116	.type = MT_DEVICE,
	117	}, {
	118	.virtual = (unsigned long)S3C_VA_TIMER,
	119	.pfn = __phys_to_pfn(S3C_PA_TIMER),
	120	.length = SZ_16K,
121	.type = MT_DEVICE,
122	}, {
123	.virtual = (unsigned long)S3C64XX_VA_GPIO,
124	.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
125	.length = SZ_4K,
126	.type = MT_DEVICE,
127	}, {
128	.virtual = (unsigned long)S3C64XX_VA_MODEM,
129	.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
130	.length = SZ_4K,
131	.type = MT_DEVICE,
132	}, {
133	.virtual = (unsigned long)S3C_VA_WATCHDOG,
134	.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
135	.length = SZ_4K,
136	.type = MT_DEVICE,
137	}, {
138	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
139	.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
140	.length = SZ_1K,
141	.type = MT_DEVICE,
142	},
143	};
144
7affca35 LT	145	static struct bus_type s3c64xx_subsys = {
	146	.name = "s3c64xx-core",
	147	.dev_name = "s3c64xx-core",
b024043b KK	148	};
b024043b KK	149
7affca35 LT	150	static struct device s3c64xx_dev = {
7affca35 LT	151	.bus = &s3c64xx_subsys,
b024043b KK	152	};
b024043b KK	153
1c161fd0 TF	154	static struct samsung_pwm_variant s3c64xx_pwm_variant = {
	155	.bits = 32,
	156	.div_base = 0,
	157	.has_tint_cstat = true,
	158	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	159	};
	160
b024043b KK	161	/* read cpu identification code */
	162
	163	void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
	164	{
	165	/* initialise the io descriptors we need for initialisation */
	166	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	167	iotable_init(mach_desc, size);
b024043b KK	168
	169	/* detect cpu id */
	170	s3c64xx_init_cpu();
	171
	172	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
1c161fd0 TF	173
1c161fd0 TF	174	samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
b024043b KK	175	}
b024043b KK	176
7affca35	177	static __init int s3c64xx_dev_init(void)
b024043b	178	{
7affca35 LT	179	subsys_system_register(&s3c64xx_subsys, NULL);
7affca35 LT	180	return device_register(&s3c64xx_dev);
b024043b	181	}
7affca35	182	core_initcall(s3c64xx_dev_init);
b024043b KK	183
	184	/*
	185	* setup the sources the vic should advertise resume
	186	* for, even though it is not doing the wake
	187	* (set_irq_wake needs to be valid)
	188	*/
	189	#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
	190	#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) \| \
	191	1 << (IRQ_PENDN - IRQ_VIC1_BASE) \| \
	192	1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) \| \
	193	1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) \| \
	194	1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
	195
	196	void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
	197	{
88f59738 TF	198	/*
	199	* FIXME: there is no better place to put this at the moment
	200	* (samsung_wdt_reset_init needs clocks)
	201	*/
	202	samsung_wdt_reset_init(S3C_VA_WATCHDOG);
	203
b024043b KK	204	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
	205
	206	/* initialise the pair of VICs */
	207	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
	208	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
	209
	210	/* add the timer sub-irqs */
	211	s3c_init_vic_timer_irq(5, IRQ_TIMER0);
	212	}
80789e79	213
80789e79	214	#define eint_offset(irq) ((irq) - IRQ_EINT(0))
3c916975	215	#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
80789e79	216
c35cd6ec	217	static inline void s3c_irq_eint_mask(struct irq_data *data)
80789e79 BD	218	{
	219	u32 mask;
	220
	221	mask = __raw_readl(S3C64XX_EINT0MASK);
3c916975	222	mask \|= (u32)data->chip_data;
80789e79 BD	223	__raw_writel(mask, S3C64XX_EINT0MASK);
	224	}
	225
c35cd6ec	226	static void s3c_irq_eint_unmask(struct irq_data *data)
80789e79 BD	227	{
	228	u32 mask;
	229
	230	mask = __raw_readl(S3C64XX_EINT0MASK);
3c916975	231	mask &= ~((u32)data->chip_data);
80789e79 BD	232	__raw_writel(mask, S3C64XX_EINT0MASK);
	233	}
	234
c35cd6ec	235	static inline void s3c_irq_eint_ack(struct irq_data *data)
80789e79	236	{
3c916975	237	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
80789e79 BD	238	}
80789e79 BD	239
c35cd6ec	240	static void s3c_irq_eint_maskack(struct irq_data *data)
80789e79 BD	241	{
80789e79 BD	242	/* compiler should in-line these */
c35cd6ec MB	243	s3c_irq_eint_mask(data);
c35cd6ec MB	244	s3c_irq_eint_ack(data);
80789e79 BD	245	}
80789e79 BD	246
c35cd6ec	247	static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
80789e79	248	{
c35cd6ec	249	int offs = eint_offset(data->irq);
6a88e983	250	int pin, pin_val;
80789e79 BD	251	int shift;
	252	u32 ctrl, mask;
	253	u32 newvalue = 0;
	254	void __iomem *reg;
	255
	256	if (offs > 27)
	257	return -EINVAL;
	258
a9c5d23a	259	if (offs <= 15)
80789e79 BD	260	reg = S3C64XX_EINT0CON0;
	261	else
	262	reg = S3C64XX_EINT0CON1;
	263
	264	switch (type) {
	265	case IRQ_TYPE_NONE:
	266	printk(KERN_WARNING "No edge setting!\n");
	267	break;
	268
	269	case IRQ_TYPE_EDGE_RISING:
	270	newvalue = S3C2410_EXTINT_RISEEDGE;
	271	break;
	272
	273	case IRQ_TYPE_EDGE_FALLING:
	274	newvalue = S3C2410_EXTINT_FALLEDGE;
	275	break;
	276
	277	case IRQ_TYPE_EDGE_BOTH:
	278	newvalue = S3C2410_EXTINT_BOTHEDGE;
	279	break;
	280
	281	case IRQ_TYPE_LEVEL_LOW:
	282	newvalue = S3C2410_EXTINT_LOWLEV;
	283	break;
	284
	285	case IRQ_TYPE_LEVEL_HIGH:
	286	newvalue = S3C2410_EXTINT_HILEV;
	287	break;
	288
	289	default:
	290	printk(KERN_ERR "No such irq type %d", type);
	291	return -1;
	292	}
	293
6a88e983 MC	294	if (offs <= 15)
	295	shift = (offs / 2) * 4;
	296	else
	297	shift = ((offs - 16) / 2) * 4;
80789e79 BD	298	mask = 0x7 << shift;
	299
	300	ctrl = __raw_readl(reg);
	301	ctrl &= ~mask;
	302	ctrl \|= newvalue << shift;
	303	__raw_writel(ctrl, reg);
	304
28fd2d39 BD	305	/* set the GPIO pin appropriately */
28fd2d39 BD	306
6a88e983	307	if (offs < 16) {
28fd2d39	308	pin = S3C64XX_GPN(offs);
6a88e983 MC	309	pin_val = S3C_GPIO_SFN(2);
	310	} else if (offs < 23) {
	311	pin = S3C64XX_GPL(offs + 8 - 16);
	312	pin_val = S3C_GPIO_SFN(3);
	313	} else {
28fd2d39	314	pin = S3C64XX_GPM(offs - 23);
6a88e983 MC	315	pin_val = S3C_GPIO_SFN(3);
6a88e983 MC	316	}
28fd2d39	317
6a88e983	318	s3c_gpio_cfgpin(pin, pin_val);
28fd2d39	319
80789e79 BD	320	return 0;
	321	}
	322
	323	static struct irq_chip s3c_irq_eint = {
	324	.name = "s3c-eint",
c35cd6ec MB	325	.irq_mask = s3c_irq_eint_mask,
	326	.irq_unmask = s3c_irq_eint_unmask,
	327	.irq_mask_ack = s3c_irq_eint_maskack,
	328	.irq_ack = s3c_irq_eint_ack,
	329	.irq_set_type = s3c_irq_eint_set_type,
f5aeffb7	330	.irq_set_wake = s3c_irqext_wake,
80789e79 BD	331	};
	332
	333	/* s3c_irq_demux_eint
	334	*
	335	* This function demuxes the IRQ from the group0 external interrupts,
	336	* from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
	337	* the specific handlers s3c_irq_demux_eintX_Y.
	338	*/
	339	static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
	340	{
	341	u32 status = __raw_readl(S3C64XX_EINT0PEND);
	342	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
	343	unsigned int irq;
	344
	345	status &= ~mask;
	346	status >>= start;
	347	status &= (1 << (end - start + 1)) - 1;
	348
	349	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
	350	if (status & 1)
	351	generic_handle_irq(irq);
	352
	353	status >>= 1;
	354	}
	355	}
	356
	357	static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
	358	{
	359	s3c_irq_demux_eint(0, 3);
	360	}
	361
	362	static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
	363	{
	364	s3c_irq_demux_eint(4, 11);
	365	}
	366
	367	static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
	368	{
	369	s3c_irq_demux_eint(12, 19);
	370	}
	371
	372	static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
	373	{
	374	s3c_irq_demux_eint(20, 27);
	375	}
	376
8bd8dbdf	377	static int __init s3c64xx_init_irq_eint(void)
80789e79 BD	378	{
	379	int irq;
	380
	381	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
f38c02f3	382	irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
9323f261	383	irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
80789e79 BD	384	set_irq_flags(irq, IRQF_VALID);
	385	}
	386
6845664a TG	387	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
	388	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
	389	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
	390	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
80789e79 BD	391
	392	return 0;
	393	}
80789e79	394	arch_initcall(s3c64xx_init_irq_eint);
ff84ded2	395
7b6d864b	396	void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
ff84ded2	397	{
7b6d864b	398	if (mode != REBOOT_SOFT)
88f59738	399	samsung_wdt_reset();
ff84ded2 KK	400
	401	/* if all else fails, or mode was for soft, jump to 0 */
	402	soft_restart(0);
	403	}
cc8f252b SG	404
	405	void __init s3c64xx_init_late(void)
	406	{
	407	s3c64xx_pm_late_initcall();
	408	}