[deliverable/linux.git] / arch / arm / mach-s3c64xx / common.c

/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * Common Codes for S3C64XX machines
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/irqchip/arm-vic.h>
#include <clocksource/samsung_pwm.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include <mach/map.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>

#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/gpio-cfg.h>
#include <plat/irq-uart.h>
#include <plat/pwm-core.h>
#include <plat/regs-irqtype.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>

#include "common.h"

/* uart registration process */

static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
}

/* table of supported CPUs */

static const char name_s3c6400[] = "S3C6400";
static const char name_s3c6410[] = "S3C6410";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= S3C6400_CPU_ID,
		.idmask		= S3C64XX_CPU_MASK,
		.map_io		= s3c6400_map_io,
		.init_clocks	= s3c6400_init_clocks,
		.init_uarts	= s3c64xx_init_uarts,
		.init		= s3c6400_init,
		.name		= name_s3c6400,
	}, {
		.idcode		= S3C6410_CPU_ID,
		.idmask		= S3C64XX_CPU_MASK,
		.map_io		= s3c6410_map_io,
		.init_clocks	= s3c6410_init_clocks,
		.init_uarts	= s3c64xx_init_uarts,
		.init		= s3c6410_init,
		.name		= name_s3c6410,
	},
};

/* minimal IO mapping */

/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
#define UART_OFFS (S3C_PA_UART & 0xfffff)

static struct map_desc s3c_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(S3C64XX_PA_SYSCON),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_MEM,
		.pfn		= __phys_to_pfn(S3C64XX_PA_SROM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)(S3C_VA_UART + UART_OFFS),
		.pfn		= __phys_to_pfn(S3C_PA_UART),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)VA_VIC0,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC0),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)VA_VIC1,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC1),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(S3C_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_GPIO,
		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(S3C64XX_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
		.length		= SZ_1K,
		.type		= MT_DEVICE,
	},
};

static struct bus_type s3c64xx_subsys = {
	.name		= "s3c64xx-core",
	.dev_name	= "s3c64xx-core",
};

static struct device s3c64xx_dev = {
	.bus	= &s3c64xx_subsys,
};

static struct samsung_pwm_variant s3c64xx_pwm_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

void __init samsung_set_timer_source(unsigned int event, unsigned int source)
{
	s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
	s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}

void __init samsung_timer_init(void)
{
	unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
		IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
		IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
	};

	samsung_pwm_clocksource_init(S3C_VA_TIMER,
					timer_irqs, &s3c64xx_pwm_variant);
}

/* read cpu identification code */

void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
{
	/* initialise the io descriptors we need for initialisation */
	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	iotable_init(mach_desc, size);

	/* detect cpu id */
	s3c64xx_init_cpu();

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));

	samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
}

static __init int s3c64xx_dev_init(void)
{
	subsys_system_register(&s3c64xx_subsys, NULL);
	return device_register(&s3c64xx_dev);
}
core_initcall(s3c64xx_dev_init);

/*
 * setup the sources the vic should advertise resume
 * for, even though it is not doing the wake
 * (set_irq_wake needs to be valid)
 */
#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_PENDN - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))

void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
	/*
	 * FIXME: there is no better place to put this at the moment
	 * (samsung_wdt_reset_init needs clocks)
	 */
	samsung_wdt_reset_init(S3C_VA_WATCHDOG);

	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);

	/* initialise the pair of VICs */
	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
}

#define eint_offset(irq)	((irq) - IRQ_EINT(0))
#define eint_irq_to_bit(irq)	((u32)(1 << eint_offset(irq)))

static inline void s3c_irq_eint_mask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S3C64XX_EINT0MASK);
	mask |= (u32)data->chip_data;
	__raw_writel(mask, S3C64XX_EINT0MASK);
}

static void s3c_irq_eint_unmask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S3C64XX_EINT0MASK);
	mask &= ~((u32)data->chip_data);
	__raw_writel(mask, S3C64XX_EINT0MASK);
}

static inline void s3c_irq_eint_ack(struct irq_data *data)
{
	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
}

static void s3c_irq_eint_maskack(struct irq_data *data)
{
	/* compiler should in-line these */
	s3c_irq_eint_mask(data);
	s3c_irq_eint_ack(data);
}

static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
	int offs = eint_offset(data->irq);
	int pin, pin_val;
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;
	void __iomem *reg;

	if (offs > 27)
		return -EINVAL;

	if (offs <= 15)
		reg = S3C64XX_EINT0CON0;
	else
		reg = S3C64XX_EINT0CON1;

	switch (type) {
	case IRQ_TYPE_NONE:
		printk(KERN_WARNING "No edge setting!\n");
		break;

	case IRQ_TYPE_EDGE_RISING:
		newvalue = S3C2410_EXTINT_RISEEDGE;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S3C2410_EXTINT_FALLEDGE;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S3C2410_EXTINT_BOTHEDGE;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S3C2410_EXTINT_LOWLEV;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S3C2410_EXTINT_HILEV;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -1;
	}

	if (offs <= 15)
		shift = (offs / 2) * 4;
	else
		shift = ((offs - 16) / 2) * 4;
	mask = 0x7 << shift;

	ctrl = __raw_readl(reg);
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, reg);

	/* set the GPIO pin appropriately */

	if (offs < 16) {
		pin = S3C64XX_GPN(offs);
		pin_val = S3C_GPIO_SFN(2);
	} else if (offs < 23) {
		pin = S3C64XX_GPL(offs + 8 - 16);
		pin_val = S3C_GPIO_SFN(3);
	} else {
		pin = S3C64XX_GPM(offs - 23);
		pin_val = S3C_GPIO_SFN(3);
	}

	s3c_gpio_cfgpin(pin, pin_val);

	return 0;
}

static struct irq_chip s3c_irq_eint = {
	.name		= "s3c-eint",
	.irq_mask	= s3c_irq_eint_mask,
	.irq_unmask	= s3c_irq_eint_unmask,
	.irq_mask_ack	= s3c_irq_eint_maskack,
	.irq_ack	= s3c_irq_eint_ack,
	.irq_set_type	= s3c_irq_eint_set_type,
	.irq_set_wake	= s3c_irqext_wake,
};

/* s3c_irq_demux_eint
 *
 * This function demuxes the IRQ from the group0 external interrupts,
 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 * the specific handlers s3c_irq_demux_eintX_Y.
 */
static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
{
	u32 status = __raw_readl(S3C64XX_EINT0PEND);
	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
	unsigned int irq;

	status &= ~mask;
	status >>= start;
	status &= (1 << (end - start + 1)) - 1;

	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
		if (status & 1)
			generic_handle_irq(irq);

		status >>= 1;
	}
}

static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(0, 3);
}

static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(4, 11);
}

static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(12, 19);
}

static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(20, 27);
}

static int __init s3c64xx_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
		irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
		irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);

	return 0;
}
arch_initcall(s3c64xx_init_irq_eint);

void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
{
	if (mode != REBOOT_SOFT)
		samsung_wdt_reset();

	/* if all else fails, or mode was for soft, jump to 0 */
	soft_restart(0);
}

void __init s3c64xx_init_late(void)
{
	s3c64xx_pm_late_initcall();
}
Commit	Line	Data
b024043b KK	1	/*
	2	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
80789e79 BD	4	*
	5	* Copyright 2008 Openmoko, Inc.
	6	* Copyright 2008 Simtec Electronics
b024043b KK	7	* Ben Dooks <ben@simtec.co.uk>
b024043b KK	8	* http://armlinux.simtec.co.uk/
80789e79	9	*
b024043b	10	* Common Codes for S3C64XX machines
80789e79 BD	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
	17	#include <linux/kernel.h>
b024043b KK	18	#include <linux/init.h>
b024043b KK	19	#include <linux/module.h>
80789e79	20	#include <linux/interrupt.h>
b024043b	21	#include <linux/ioport.h>
b024043b KK	22	#include <linux/serial_core.h>
b024043b KK	23	#include <linux/platform_device.h>
7b6d864b	24	#include <linux/reboot.h>
80789e79	25	#include <linux/io.h>
b024043b KK	26	#include <linux/dma-mapping.h>
	27	#include <linux/irq.h>
	28	#include <linux/gpio.h>
9e47b8bf	29	#include <linux/irqchip/arm-vic.h>
1c161fd0	30	#include <clocksource/samsung_pwm.h>
80789e79	31
b024043b KK	32	#include <asm/mach/arch.h>
b024043b KK	33	#include <asm/mach/map.h>
9f97da78	34	#include <asm/system_misc.h>
80789e79	35
b024043b KK	36	#include <mach/map.h>
b024043b KK	37	#include <mach/hardware.h>
3501c9ae	38	#include <mach/regs-gpio.h>
80789e79	39
80789e79	40	#include <plat/cpu.h>
b024043b KK	41	#include <plat/clock.h>
b024043b KK	42	#include <plat/devs.h>
bd117bd1	43	#include <plat/pm.h>
b024043b KK	44	#include <plat/gpio-cfg.h>
b024043b KK	45	#include <plat/irq-uart.h>
1c161fd0	46	#include <plat/pwm-core.h>
b024043b KK	47	#include <plat/regs-irqtype.h>
b024043b KK	48	#include <plat/regs-serial.h>
ff84ded2	49	#include <plat/watchdog-reset.h>
b024043b KK	50
	51	#include "common.h"
	52
	53	/* uart registration process */
	54
b7c9705c	55	static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
b024043b KK	56	{
	57	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
	58	}
	59
	60	/* table of supported CPUs */
	61
	62	static const char name_s3c6400[] = "S3C6400";
	63	static const char name_s3c6410[] = "S3C6410";
	64
	65	static struct cpu_table cpu_ids[] __initdata = {
	66	{
	67	.idcode = S3C6400_CPU_ID,
	68	.idmask = S3C64XX_CPU_MASK,
	69	.map_io = s3c6400_map_io,
	70	.init_clocks = s3c6400_init_clocks,
	71	.init_uarts = s3c64xx_init_uarts,
	72	.init = s3c6400_init,
	73	.name = name_s3c6400,
	74	}, {
	75	.idcode = S3C6410_CPU_ID,
	76	.idmask = S3C64XX_CPU_MASK,
	77	.map_io = s3c6410_map_io,
	78	.init_clocks = s3c6410_init_clocks,
	79	.init_uarts = s3c64xx_init_uarts,
	80	.init = s3c6410_init,
	81	.name = name_s3c6410,
	82	},
	83	};
	84
	85	/* minimal IO mapping */
	86
	87	/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
	88	#define UART_OFFS (S3C_PA_UART & 0xfffff)
	89
	90	static struct map_desc s3c_iodesc[] __initdata = {
	91	{
	92	.virtual = (unsigned long)S3C_VA_SYS,
	93	.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
	94	.length = SZ_4K,
	95	.type = MT_DEVICE,
	96	}, {
	97	.virtual = (unsigned long)S3C_VA_MEM,
	98	.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
	99	.length = SZ_4K,
	100	.type = MT_DEVICE,
	101	}, {
	102	.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
	103	.pfn = __phys_to_pfn(S3C_PA_UART),
	104	.length = SZ_4K,
	105	.type = MT_DEVICE,
	106	}, {
	107	.virtual = (unsigned long)VA_VIC0,
	108	.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
	109	.length = SZ_16K,
	110	.type = MT_DEVICE,
	111	}, {
	112	.virtual = (unsigned long)VA_VIC1,
	113	.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
	114	.length = SZ_16K,
	115	.type = MT_DEVICE,
	116	}, {
	117	.virtual = (unsigned long)S3C_VA_TIMER,
	118	.pfn = __phys_to_pfn(S3C_PA_TIMER),
	119	.length = SZ_16K,
120	.type = MT_DEVICE,
121	}, {
122	.virtual = (unsigned long)S3C64XX_VA_GPIO,
123	.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
124	.length = SZ_4K,
125	.type = MT_DEVICE,
126	}, {
127	.virtual = (unsigned long)S3C64XX_VA_MODEM,
128	.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
129	.length = SZ_4K,
130	.type = MT_DEVICE,
131	}, {
132	.virtual = (unsigned long)S3C_VA_WATCHDOG,
133	.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
134	.length = SZ_4K,
135	.type = MT_DEVICE,
136	}, {
137	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
138	.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
139	.length = SZ_1K,
140	.type = MT_DEVICE,
141	},
142	};
143
7affca35 LT	144	static struct bus_type s3c64xx_subsys = {
	145	.name = "s3c64xx-core",
	146	.dev_name = "s3c64xx-core",
b024043b KK	147	};
b024043b KK	148
7affca35 LT	149	static struct device s3c64xx_dev = {
7affca35 LT	150	.bus = &s3c64xx_subsys,
b024043b KK	151	};
b024043b KK	152
1c161fd0 TF	153	static struct samsung_pwm_variant s3c64xx_pwm_variant = {
	154	.bits = 32,
	155	.div_base = 0,
	156	.has_tint_cstat = true,
	157	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	158	};
	159
4280506a TF	160	void __init samsung_set_timer_source(unsigned int event, unsigned int source)
	161	{
	162	s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
	163	s3c64xx_pwm_variant.output_mask &= ~(BIT(event) \| BIT(source));
	164	}
	165
	166	void __init samsung_timer_init(void)
	167	{
	168	unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
	169	IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
	170	IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
	171	};
	172
	173	samsung_pwm_clocksource_init(S3C_VA_TIMER,
	174	timer_irqs, &s3c64xx_pwm_variant);
	175	}
	176
b024043b KK	177	/* read cpu identification code */
	178
	179	void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
	180	{
	181	/* initialise the io descriptors we need for initialisation */
	182	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	183	iotable_init(mach_desc, size);
b024043b KK	184
	185	/* detect cpu id */
	186	s3c64xx_init_cpu();
	187
	188	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
1c161fd0 TF	189
1c161fd0 TF	190	samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
b024043b KK	191	}
b024043b KK	192
7affca35	193	static __init int s3c64xx_dev_init(void)
b024043b	194	{
7affca35 LT	195	subsys_system_register(&s3c64xx_subsys, NULL);
7affca35 LT	196	return device_register(&s3c64xx_dev);
b024043b	197	}
7affca35	198	core_initcall(s3c64xx_dev_init);
b024043b KK	199
	200	/*
	201	* setup the sources the vic should advertise resume
	202	* for, even though it is not doing the wake
	203	* (set_irq_wake needs to be valid)
	204	*/
	205	#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
	206	#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) \| \
	207	1 << (IRQ_PENDN - IRQ_VIC1_BASE) \| \
	208	1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) \| \
	209	1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) \| \
	210	1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
	211
	212	void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
	213	{
88f59738 TF	214	/*
	215	* FIXME: there is no better place to put this at the moment
	216	* (samsung_wdt_reset_init needs clocks)
	217	*/
	218	samsung_wdt_reset_init(S3C_VA_WATCHDOG);
	219
b024043b KK	220	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
	221
	222	/* initialise the pair of VICs */
	223	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
	224	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
b024043b	225	}
80789e79	226
80789e79	227	#define eint_offset(irq) ((irq) - IRQ_EINT(0))
3c916975	228	#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
80789e79	229
c35cd6ec	230	static inline void s3c_irq_eint_mask(struct irq_data *data)
80789e79 BD	231	{
	232	u32 mask;
	233
	234	mask = __raw_readl(S3C64XX_EINT0MASK);
3c916975	235	mask \|= (u32)data->chip_data;
80789e79 BD	236	__raw_writel(mask, S3C64XX_EINT0MASK);
	237	}
	238
c35cd6ec	239	static void s3c_irq_eint_unmask(struct irq_data *data)
80789e79 BD	240	{
	241	u32 mask;
	242
	243	mask = __raw_readl(S3C64XX_EINT0MASK);
3c916975	244	mask &= ~((u32)data->chip_data);
80789e79 BD	245	__raw_writel(mask, S3C64XX_EINT0MASK);
	246	}
	247
c35cd6ec	248	static inline void s3c_irq_eint_ack(struct irq_data *data)
80789e79	249	{
3c916975	250	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
80789e79 BD	251	}
80789e79 BD	252
c35cd6ec	253	static void s3c_irq_eint_maskack(struct irq_data *data)
80789e79 BD	254	{
80789e79 BD	255	/* compiler should in-line these */
c35cd6ec MB	256	s3c_irq_eint_mask(data);
c35cd6ec MB	257	s3c_irq_eint_ack(data);
80789e79 BD	258	}
80789e79 BD	259
c35cd6ec	260	static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
80789e79	261	{
c35cd6ec	262	int offs = eint_offset(data->irq);
6a88e983	263	int pin, pin_val;
80789e79 BD	264	int shift;
	265	u32 ctrl, mask;
	266	u32 newvalue = 0;
	267	void __iomem *reg;
	268
	269	if (offs > 27)
	270	return -EINVAL;
	271
a9c5d23a	272	if (offs <= 15)
80789e79 BD	273	reg = S3C64XX_EINT0CON0;
	274	else
	275	reg = S3C64XX_EINT0CON1;
	276
	277	switch (type) {
	278	case IRQ_TYPE_NONE:
	279	printk(KERN_WARNING "No edge setting!\n");
	280	break;
	281
	282	case IRQ_TYPE_EDGE_RISING:
	283	newvalue = S3C2410_EXTINT_RISEEDGE;
	284	break;
	285
	286	case IRQ_TYPE_EDGE_FALLING:
	287	newvalue = S3C2410_EXTINT_FALLEDGE;
	288	break;
	289
	290	case IRQ_TYPE_EDGE_BOTH:
	291	newvalue = S3C2410_EXTINT_BOTHEDGE;
	292	break;
	293
	294	case IRQ_TYPE_LEVEL_LOW:
	295	newvalue = S3C2410_EXTINT_LOWLEV;
	296	break;
	297
	298	case IRQ_TYPE_LEVEL_HIGH:
	299	newvalue = S3C2410_EXTINT_HILEV;
	300	break;
	301
	302	default:
	303	printk(KERN_ERR "No such irq type %d", type);
	304	return -1;
	305	}
	306
6a88e983 MC	307	if (offs <= 15)
	308	shift = (offs / 2) * 4;
	309	else
	310	shift = ((offs - 16) / 2) * 4;
80789e79 BD	311	mask = 0x7 << shift;
	312
	313	ctrl = __raw_readl(reg);
	314	ctrl &= ~mask;
	315	ctrl \|= newvalue << shift;
	316	__raw_writel(ctrl, reg);
	317
28fd2d39 BD	318	/* set the GPIO pin appropriately */
28fd2d39 BD	319
6a88e983	320	if (offs < 16) {
28fd2d39	321	pin = S3C64XX_GPN(offs);
6a88e983 MC	322	pin_val = S3C_GPIO_SFN(2);
	323	} else if (offs < 23) {
	324	pin = S3C64XX_GPL(offs + 8 - 16);
	325	pin_val = S3C_GPIO_SFN(3);
	326	} else {
28fd2d39	327	pin = S3C64XX_GPM(offs - 23);
6a88e983 MC	328	pin_val = S3C_GPIO_SFN(3);
6a88e983 MC	329	}
28fd2d39	330
6a88e983	331	s3c_gpio_cfgpin(pin, pin_val);
28fd2d39	332
80789e79 BD	333	return 0;
	334	}
	335
	336	static struct irq_chip s3c_irq_eint = {
	337	.name = "s3c-eint",
c35cd6ec MB	338	.irq_mask = s3c_irq_eint_mask,
	339	.irq_unmask = s3c_irq_eint_unmask,
	340	.irq_mask_ack = s3c_irq_eint_maskack,
	341	.irq_ack = s3c_irq_eint_ack,
	342	.irq_set_type = s3c_irq_eint_set_type,
f5aeffb7	343	.irq_set_wake = s3c_irqext_wake,
80789e79 BD	344	};
	345
	346	/* s3c_irq_demux_eint
	347	*
	348	* This function demuxes the IRQ from the group0 external interrupts,
	349	* from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
	350	* the specific handlers s3c_irq_demux_eintX_Y.
	351	*/
	352	static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
	353	{
	354	u32 status = __raw_readl(S3C64XX_EINT0PEND);
	355	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
	356	unsigned int irq;
	357
	358	status &= ~mask;
	359	status >>= start;
	360	status &= (1 << (end - start + 1)) - 1;
	361
	362	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
	363	if (status & 1)
	364	generic_handle_irq(irq);
	365
	366	status >>= 1;
	367	}
	368	}
	369
	370	static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
	371	{
	372	s3c_irq_demux_eint(0, 3);
	373	}
	374
	375	static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
	376	{
	377	s3c_irq_demux_eint(4, 11);
	378	}
	379
	380	static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
	381	{
	382	s3c_irq_demux_eint(12, 19);
	383	}
	384
	385	static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
	386	{
	387	s3c_irq_demux_eint(20, 27);
	388	}
	389
8bd8dbdf	390	static int __init s3c64xx_init_irq_eint(void)
80789e79 BD	391	{
	392	int irq;
	393
	394	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
f38c02f3	395	irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
9323f261	396	irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
80789e79 BD	397	set_irq_flags(irq, IRQF_VALID);
	398	}
	399
6845664a TG	400	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
	401	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
	402	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
	403	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
80789e79 BD	404
	405	return 0;
	406	}
80789e79	407	arch_initcall(s3c64xx_init_irq_eint);
ff84ded2	408
7b6d864b	409	void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
ff84ded2	410	{
7b6d864b	411	if (mode != REBOOT_SOFT)
88f59738	412	samsung_wdt_reset();
ff84ded2 KK	413
	414	/* if all else fails, or mode was for soft, jump to 0 */
	415	soft_restart(0);
	416	}
cc8f252b SG	417
	418	void __init s3c64xx_init_late(void)
	419	{
	420	s3c64xx_pm_late_initcall();
	421	}