[deliverable/linux.git] / arch / arm / mach-s3c64xx / common.c

/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * Common Codes for S3C64XX machines
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/irq.h>
#include <linux/gpio.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/hardware/vic.h>

#include <mach/map.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>

#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/gpio-cfg.h>
#include <plat/irq-uart.h>
#include <plat/irq-vic-timer.h>
#include <plat/regs-irqtype.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>

#include "common.h"

/* uart registration process */

void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
}

/* table of supported CPUs */

static const char name_s3c6400[] = "S3C6400";
static const char name_s3c6410[] = "S3C6410";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= S3C6400_CPU_ID,
		.idmask		= S3C64XX_CPU_MASK,
		.map_io		= s3c6400_map_io,
		.init_clocks	= s3c6400_init_clocks,
		.init_uarts	= s3c64xx_init_uarts,
		.init		= s3c6400_init,
		.name		= name_s3c6400,
	}, {
		.idcode		= S3C6410_CPU_ID,
		.idmask		= S3C64XX_CPU_MASK,
		.map_io		= s3c6410_map_io,
		.init_clocks	= s3c6410_init_clocks,
		.init_uarts	= s3c64xx_init_uarts,
		.init		= s3c6410_init,
		.name		= name_s3c6410,
	},
};

/* minimal IO mapping */

/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
#define UART_OFFS (S3C_PA_UART & 0xfffff)

static struct map_desc s3c_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(S3C64XX_PA_SYSCON),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_MEM,
		.pfn		= __phys_to_pfn(S3C64XX_PA_SROM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)(S3C_VA_UART + UART_OFFS),
		.pfn		= __phys_to_pfn(S3C_PA_UART),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)VA_VIC0,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC0),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)VA_VIC1,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC1),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(S3C_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_GPIO,
		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(S3C64XX_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
		.length		= SZ_1K,
		.type		= MT_DEVICE,
	},
};

static struct bus_type s3c64xx_subsys = {
	.name		= "s3c64xx-core",
	.dev_name	= "s3c64xx-core",
};

static struct device s3c64xx_dev = {
	.bus	= &s3c64xx_subsys,
};

/* read cpu identification code */

void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
{
	/* initialise the io descriptors we need for initialisation */
	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	iotable_init(mach_desc, size);
	init_consistent_dma_size(SZ_8M);

	/* detect cpu id */
	s3c64xx_init_cpu();

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}

static __init int s3c64xx_dev_init(void)
{
	subsys_system_register(&s3c64xx_subsys, NULL);
	return device_register(&s3c64xx_dev);
}
core_initcall(s3c64xx_dev_init);

/*
 * setup the sources the vic should advertise resume
 * for, even though it is not doing the wake
 * (set_irq_wake needs to be valid)
 */
#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_PENDN - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |	\
			 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))

void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);

	/* initialise the pair of VICs */
	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);

	/* add the timer sub-irqs */
	s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}

#define eint_offset(irq)	((irq) - IRQ_EINT(0))
#define eint_irq_to_bit(irq)	((u32)(1 << eint_offset(irq)))

static inline void s3c_irq_eint_mask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S3C64XX_EINT0MASK);
	mask |= (u32)data->chip_data;
	__raw_writel(mask, S3C64XX_EINT0MASK);
}

static void s3c_irq_eint_unmask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S3C64XX_EINT0MASK);
	mask &= ~((u32)data->chip_data);
	__raw_writel(mask, S3C64XX_EINT0MASK);
}

static inline void s3c_irq_eint_ack(struct irq_data *data)
{
	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
}

static void s3c_irq_eint_maskack(struct irq_data *data)
{
	/* compiler should in-line these */
	s3c_irq_eint_mask(data);
	s3c_irq_eint_ack(data);
}

static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
	int offs = eint_offset(data->irq);
	int pin, pin_val;
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;
	void __iomem *reg;

	if (offs > 27)
		return -EINVAL;

	if (offs <= 15)
		reg = S3C64XX_EINT0CON0;
	else
		reg = S3C64XX_EINT0CON1;

	switch (type) {
	case IRQ_TYPE_NONE:
		printk(KERN_WARNING "No edge setting!\n");
		break;

	case IRQ_TYPE_EDGE_RISING:
		newvalue = S3C2410_EXTINT_RISEEDGE;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S3C2410_EXTINT_FALLEDGE;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S3C2410_EXTINT_BOTHEDGE;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S3C2410_EXTINT_LOWLEV;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S3C2410_EXTINT_HILEV;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -1;
	}

	if (offs <= 15)
		shift = (offs / 2) * 4;
	else
		shift = ((offs - 16) / 2) * 4;
	mask = 0x7 << shift;

	ctrl = __raw_readl(reg);
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, reg);

	/* set the GPIO pin appropriately */

	if (offs < 16) {
		pin = S3C64XX_GPN(offs);
		pin_val = S3C_GPIO_SFN(2);
	} else if (offs < 23) {
		pin = S3C64XX_GPL(offs + 8 - 16);
		pin_val = S3C_GPIO_SFN(3);
	} else {
		pin = S3C64XX_GPM(offs - 23);
		pin_val = S3C_GPIO_SFN(3);
	}

	s3c_gpio_cfgpin(pin, pin_val);

	return 0;
}

static struct irq_chip s3c_irq_eint = {
	.name		= "s3c-eint",
	.irq_mask	= s3c_irq_eint_mask,
	.irq_unmask	= s3c_irq_eint_unmask,
	.irq_mask_ack	= s3c_irq_eint_maskack,
	.irq_ack	= s3c_irq_eint_ack,
	.irq_set_type	= s3c_irq_eint_set_type,
	.irq_set_wake	= s3c_irqext_wake,
};

/* s3c_irq_demux_eint
 *
 * This function demuxes the IRQ from the group0 external interrupts,
 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 * the specific handlers s3c_irq_demux_eintX_Y.
 */
static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
{
	u32 status = __raw_readl(S3C64XX_EINT0PEND);
	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
	unsigned int irq;

	status &= ~mask;
	status >>= start;
	status &= (1 << (end - start + 1)) - 1;

	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
		if (status & 1)
			generic_handle_irq(irq);

		status >>= 1;
	}
}

static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(0, 3);
}

static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(4, 11);
}

static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(12, 19);
}

static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
{
	s3c_irq_demux_eint(20, 27);
}

static int __init s3c64xx_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
		irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
		irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);

	return 0;
}
arch_initcall(s3c64xx_init_irq_eint);

void s3c64xx_restart(char mode, const char *cmd)
{
	if (mode != 's')
		arch_wdt_reset();

	/* if all else fails, or mode was for soft, jump to 0 */
	soft_restart(0);
}
Commit	Line	Data
b024043b KK	1	/*
	2	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
80789e79 BD	4	*
	5	* Copyright 2008 Openmoko, Inc.
	6	* Copyright 2008 Simtec Electronics
b024043b KK	7	* Ben Dooks <ben@simtec.co.uk>
b024043b KK	8	* http://armlinux.simtec.co.uk/
80789e79	9	*
b024043b	10	* Common Codes for S3C64XX machines
80789e79 BD	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
	17	#include <linux/kernel.h>
b024043b KK	18	#include <linux/init.h>
b024043b KK	19	#include <linux/module.h>
80789e79	20	#include <linux/interrupt.h>
b024043b	21	#include <linux/ioport.h>
b024043b KK	22	#include <linux/serial_core.h>
b024043b KK	23	#include <linux/platform_device.h>
80789e79	24	#include <linux/io.h>
b024043b KK	25	#include <linux/dma-mapping.h>
	26	#include <linux/irq.h>
	27	#include <linux/gpio.h>
80789e79	28
b024043b KK	29	#include <asm/mach/arch.h>
b024043b KK	30	#include <asm/mach/map.h>
80789e79 BD	31	#include <asm/hardware/vic.h>
80789e79 BD	32
b024043b KK	33	#include <mach/map.h>
b024043b KK	34	#include <mach/hardware.h>
3501c9ae	35	#include <mach/regs-gpio.h>
80789e79	36
80789e79	37	#include <plat/cpu.h>
b024043b KK	38	#include <plat/clock.h>
b024043b KK	39	#include <plat/devs.h>
bd117bd1	40	#include <plat/pm.h>
b024043b KK	41	#include <plat/gpio-cfg.h>
	42	#include <plat/irq-uart.h>
	43	#include <plat/irq-vic-timer.h>
	44	#include <plat/regs-irqtype.h>
	45	#include <plat/regs-serial.h>
ff84ded2	46	#include <plat/watchdog-reset.h>
b024043b KK	47
	48	#include "common.h"
	49
	50	/* uart registration process */
	51
	52	void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
	53	{
	54	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
	55	}
	56
	57	/* table of supported CPUs */
	58
	59	static const char name_s3c6400[] = "S3C6400";
	60	static const char name_s3c6410[] = "S3C6410";
	61
	62	static struct cpu_table cpu_ids[] __initdata = {
	63	{
	64	.idcode = S3C6400_CPU_ID,
	65	.idmask = S3C64XX_CPU_MASK,
	66	.map_io = s3c6400_map_io,
	67	.init_clocks = s3c6400_init_clocks,
	68	.init_uarts = s3c64xx_init_uarts,
	69	.init = s3c6400_init,
	70	.name = name_s3c6400,
	71	}, {
	72	.idcode = S3C6410_CPU_ID,
	73	.idmask = S3C64XX_CPU_MASK,
	74	.map_io = s3c6410_map_io,
	75	.init_clocks = s3c6410_init_clocks,
	76	.init_uarts = s3c64xx_init_uarts,
	77	.init = s3c6410_init,
	78	.name = name_s3c6410,
	79	},
	80	};
	81
	82	/* minimal IO mapping */
	83
	84	/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
	85	#define UART_OFFS (S3C_PA_UART & 0xfffff)
	86
	87	static struct map_desc s3c_iodesc[] __initdata = {
	88	{
	89	.virtual = (unsigned long)S3C_VA_SYS,
	90	.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
	91	.length = SZ_4K,
	92	.type = MT_DEVICE,
	93	}, {
	94	.virtual = (unsigned long)S3C_VA_MEM,
	95	.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
	96	.length = SZ_4K,
	97	.type = MT_DEVICE,
	98	}, {
	99	.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
	100	.pfn = __phys_to_pfn(S3C_PA_UART),
	101	.length = SZ_4K,
	102	.type = MT_DEVICE,
	103	}, {
	104	.virtual = (unsigned long)VA_VIC0,
	105	.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
	106	.length = SZ_16K,
	107	.type = MT_DEVICE,
	108	}, {
	109	.virtual = (unsigned long)VA_VIC1,
	110	.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
111	.length = SZ_16K,
112	.type = MT_DEVICE,
113	}, {
114	.virtual = (unsigned long)S3C_VA_TIMER,
115	.pfn = __phys_to_pfn(S3C_PA_TIMER),
116	.length = SZ_16K,
117	.type = MT_DEVICE,
118	}, {
119	.virtual = (unsigned long)S3C64XX_VA_GPIO,
120	.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
121	.length = SZ_4K,
122	.type = MT_DEVICE,
123	}, {
124	.virtual = (unsigned long)S3C64XX_VA_MODEM,
125	.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
126	.length = SZ_4K,
127	.type = MT_DEVICE,
128	}, {
129	.virtual = (unsigned long)S3C_VA_WATCHDOG,
130	.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
131	.length = SZ_4K,
132	.type = MT_DEVICE,
133	}, {
134	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
135	.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
136	.length = SZ_1K,
137	.type = MT_DEVICE,
138	},
139	};
140
7affca35 LT	141	static struct bus_type s3c64xx_subsys = {
	142	.name = "s3c64xx-core",
	143	.dev_name = "s3c64xx-core",
b024043b KK	144	};
b024043b KK	145
7affca35 LT	146	static struct device s3c64xx_dev = {
7affca35 LT	147	.bus = &s3c64xx_subsys,
b024043b KK	148	};
	149
	150	/* read cpu identification code */
	151
	152	void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
	153	{
	154	/* initialise the io descriptors we need for initialisation */
	155	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	156	iotable_init(mach_desc, size);
	157	init_consistent_dma_size(SZ_8M);
	158
	159	/* detect cpu id */
	160	s3c64xx_init_cpu();
	161
	162	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
	163	}
	164
7affca35	165	static __init int s3c64xx_dev_init(void)
b024043b	166	{
7affca35 LT	167	subsys_system_register(&s3c64xx_subsys, NULL);
7affca35 LT	168	return device_register(&s3c64xx_dev);
b024043b	169	}
7affca35	170	core_initcall(s3c64xx_dev_init);
b024043b KK	171
	172	/*
	173	* setup the sources the vic should advertise resume
	174	* for, even though it is not doing the wake
	175	* (set_irq_wake needs to be valid)
	176	*/
	177	#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
	178	#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) \| \
	179	1 << (IRQ_PENDN - IRQ_VIC1_BASE) \| \
	180	1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) \| \
	181	1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) \| \
	182	1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
	183
	184	void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
	185	{
	186	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
	187
	188	/* initialise the pair of VICs */
	189	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
	190	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
	191
	192	/* add the timer sub-irqs */
	193	s3c_init_vic_timer_irq(5, IRQ_TIMER0);
	194	}
80789e79	195
80789e79	196	#define eint_offset(irq) ((irq) - IRQ_EINT(0))
3c916975	197	#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
80789e79	198
c35cd6ec	199	static inline void s3c_irq_eint_mask(struct irq_data *data)
80789e79 BD	200	{
	201	u32 mask;
	202
	203	mask = __raw_readl(S3C64XX_EINT0MASK);
3c916975	204	mask \|= (u32)data->chip_data;
80789e79 BD	205	__raw_writel(mask, S3C64XX_EINT0MASK);
	206	}
	207
c35cd6ec	208	static void s3c_irq_eint_unmask(struct irq_data *data)
80789e79 BD	209	{
	210	u32 mask;
	211
	212	mask = __raw_readl(S3C64XX_EINT0MASK);
3c916975	213	mask &= ~((u32)data->chip_data);
80789e79 BD	214	__raw_writel(mask, S3C64XX_EINT0MASK);
	215	}
	216
c35cd6ec	217	static inline void s3c_irq_eint_ack(struct irq_data *data)
80789e79	218	{
3c916975	219	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
80789e79 BD	220	}
80789e79 BD	221
c35cd6ec	222	static void s3c_irq_eint_maskack(struct irq_data *data)
80789e79 BD	223	{
80789e79 BD	224	/* compiler should in-line these */
c35cd6ec MB	225	s3c_irq_eint_mask(data);
c35cd6ec MB	226	s3c_irq_eint_ack(data);
80789e79 BD	227	}
80789e79 BD	228
c35cd6ec	229	static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
80789e79	230	{
c35cd6ec	231	int offs = eint_offset(data->irq);
6a88e983	232	int pin, pin_val;
80789e79 BD	233	int shift;
	234	u32 ctrl, mask;
	235	u32 newvalue = 0;
	236	void __iomem *reg;
	237
	238	if (offs > 27)
	239	return -EINVAL;
	240
a9c5d23a	241	if (offs <= 15)
80789e79 BD	242	reg = S3C64XX_EINT0CON0;
	243	else
	244	reg = S3C64XX_EINT0CON1;
	245
	246	switch (type) {
	247	case IRQ_TYPE_NONE:
	248	printk(KERN_WARNING "No edge setting!\n");
	249	break;
	250
	251	case IRQ_TYPE_EDGE_RISING:
	252	newvalue = S3C2410_EXTINT_RISEEDGE;
	253	break;
	254
	255	case IRQ_TYPE_EDGE_FALLING:
	256	newvalue = S3C2410_EXTINT_FALLEDGE;
	257	break;
	258
	259	case IRQ_TYPE_EDGE_BOTH:
	260	newvalue = S3C2410_EXTINT_BOTHEDGE;
	261	break;
	262
	263	case IRQ_TYPE_LEVEL_LOW:
	264	newvalue = S3C2410_EXTINT_LOWLEV;
	265	break;
	266
	267	case IRQ_TYPE_LEVEL_HIGH:
	268	newvalue = S3C2410_EXTINT_HILEV;
	269	break;
	270
	271	default:
	272	printk(KERN_ERR "No such irq type %d", type);
	273	return -1;
	274	}
	275
6a88e983 MC	276	if (offs <= 15)
	277	shift = (offs / 2) * 4;
	278	else
	279	shift = ((offs - 16) / 2) * 4;
80789e79 BD	280	mask = 0x7 << shift;
	281
	282	ctrl = __raw_readl(reg);
	283	ctrl &= ~mask;
	284	ctrl \|= newvalue << shift;
	285	__raw_writel(ctrl, reg);
	286
28fd2d39 BD	287	/* set the GPIO pin appropriately */
28fd2d39 BD	288
6a88e983	289	if (offs < 16) {
28fd2d39	290	pin = S3C64XX_GPN(offs);
6a88e983 MC	291	pin_val = S3C_GPIO_SFN(2);
	292	} else if (offs < 23) {
	293	pin = S3C64XX_GPL(offs + 8 - 16);
	294	pin_val = S3C_GPIO_SFN(3);
	295	} else {
28fd2d39	296	pin = S3C64XX_GPM(offs - 23);
6a88e983 MC	297	pin_val = S3C_GPIO_SFN(3);
6a88e983 MC	298	}
28fd2d39	299
6a88e983	300	s3c_gpio_cfgpin(pin, pin_val);
28fd2d39	301
80789e79 BD	302	return 0;
	303	}
	304
	305	static struct irq_chip s3c_irq_eint = {
	306	.name = "s3c-eint",
c35cd6ec MB	307	.irq_mask = s3c_irq_eint_mask,
	308	.irq_unmask = s3c_irq_eint_unmask,
	309	.irq_mask_ack = s3c_irq_eint_maskack,
	310	.irq_ack = s3c_irq_eint_ack,
	311	.irq_set_type = s3c_irq_eint_set_type,
f5aeffb7	312	.irq_set_wake = s3c_irqext_wake,
80789e79 BD	313	};
	314
	315	/* s3c_irq_demux_eint
	316	*
	317	* This function demuxes the IRQ from the group0 external interrupts,
	318	* from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
	319	* the specific handlers s3c_irq_demux_eintX_Y.
	320	*/
	321	static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
	322	{
	323	u32 status = __raw_readl(S3C64XX_EINT0PEND);
	324	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
	325	unsigned int irq;
	326
	327	status &= ~mask;
	328	status >>= start;
	329	status &= (1 << (end - start + 1)) - 1;
	330
	331	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
	332	if (status & 1)
	333	generic_handle_irq(irq);
	334
	335	status >>= 1;
	336	}
	337	}
	338
	339	static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
	340	{
	341	s3c_irq_demux_eint(0, 3);
	342	}
	343
	344	static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
	345	{
	346	s3c_irq_demux_eint(4, 11);
	347	}
	348
	349	static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
	350	{
	351	s3c_irq_demux_eint(12, 19);
	352	}
	353
	354	static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
	355	{
	356	s3c_irq_demux_eint(20, 27);
	357	}
	358
8bd8dbdf	359	static int __init s3c64xx_init_irq_eint(void)
80789e79 BD	360	{
	361	int irq;
	362
	363	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
f38c02f3	364	irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
9323f261	365	irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
80789e79 BD	366	set_irq_flags(irq, IRQF_VALID);
	367	}
	368
6845664a TG	369	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
	370	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
	371	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
	372	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
80789e79 BD	373
	374	return 0;
	375	}
80789e79	376	arch_initcall(s3c64xx_init_irq_eint);
ff84ded2 KK	377
	378	void s3c64xx_restart(char mode, const char *cmd)
	379	{
	380	if (mode != 's')
	381	arch_wdt_reset();
	382
	383	/* if all else fails, or mode was for soft, jump to 0 */
	384	soft_restart(0);
	385	}