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1 | /* arch/arm/plat-s3c64xx/irq-pm.c |
2 | * | |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * S3C64XX - Interrupt handling Power Management | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
bb072c3c | 16 | #include <linux/syscore_ops.h> |
966bcc14 BD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/serial_core.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | ||
22 | #include <mach/map.h> | |
23 | ||
24 | #include <plat/regs-serial.h> | |
25 | #include <plat/regs-timer.h> | |
3501c9ae | 26 | #include <mach/regs-gpio.h> |
966bcc14 BD |
27 | #include <plat/cpu.h> |
28 | #include <plat/pm.h> | |
29 | ||
30 | /* We handled all the IRQ types in this code, to save having to make several | |
31 | * small files to handle each different type separately. Having the EINT_GRP | |
32 | * code here shouldn't be as much bloat as the IRQ table space needed when | |
33 | * they are enabled. The added benefit is we ensure that these registers are | |
34 | * in the same state as we suspended. | |
35 | */ | |
36 | ||
37 | static struct sleep_save irq_save[] = { | |
38 | SAVE_ITEM(S3C64XX_PRIORITY), | |
39 | SAVE_ITEM(S3C64XX_EINT0CON0), | |
40 | SAVE_ITEM(S3C64XX_EINT0CON1), | |
41 | SAVE_ITEM(S3C64XX_EINT0FLTCON0), | |
42 | SAVE_ITEM(S3C64XX_EINT0FLTCON1), | |
43 | SAVE_ITEM(S3C64XX_EINT0FLTCON2), | |
44 | SAVE_ITEM(S3C64XX_EINT0FLTCON3), | |
45 | SAVE_ITEM(S3C64XX_EINT0MASK), | |
46 | SAVE_ITEM(S3C64XX_TINT_CSTAT), | |
47 | }; | |
48 | ||
49 | static struct irq_grp_save { | |
50 | u32 fltcon; | |
51 | u32 con; | |
52 | u32 mask; | |
53 | } eint_grp_save[5]; | |
54 | ||
55 | static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; | |
56 | ||
bb072c3c | 57 | static int s3c64xx_irq_pm_suspend(void) |
966bcc14 BD |
58 | { |
59 | struct irq_grp_save *grp = eint_grp_save; | |
60 | int i; | |
61 | ||
62 | S3C_PMDBG("%s: suspending IRQs\n", __func__); | |
63 | ||
64 | s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | |
65 | ||
66 | for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) | |
67 | irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); | |
68 | ||
69 | for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { | |
70 | grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4)); | |
71 | grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); | |
72 | grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4)); | |
73 | } | |
74 | ||
75 | return 0; | |
76 | } | |
77 | ||
bb072c3c | 78 | static void s3c64xx_irq_pm_resume(void) |
966bcc14 BD |
79 | { |
80 | struct irq_grp_save *grp = eint_grp_save; | |
81 | int i; | |
82 | ||
83 | S3C_PMDBG("%s: resuming IRQs\n", __func__); | |
84 | ||
85 | s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | |
86 | ||
87 | for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) | |
88 | __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); | |
89 | ||
90 | for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { | |
91 | __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4)); | |
92 | __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4)); | |
93 | __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4)); | |
94 | } | |
95 | ||
96 | S3C_PMDBG("%s: IRQ configuration restored\n", __func__); | |
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97 | } |
98 | ||
5086c6c8 | 99 | static struct syscore_ops s3c64xx_irq_syscore_ops = { |
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100 | .suspend = s3c64xx_irq_pm_suspend, |
101 | .resume = s3c64xx_irq_pm_resume, | |
102 | }; | |
103 | ||
bb072c3c | 104 | static __init int s3c64xx_syscore_init(void) |
966bcc14 | 105 | { |
bb072c3c | 106 | register_syscore_ops(&s3c64xx_irq_syscore_ops); |
966bcc14 | 107 | |
bb072c3c RW |
108 | return 0; |
109 | } | |
966bcc14 | 110 | |
bb072c3c | 111 | core_initcall(s3c64xx_syscore_init); |