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ARM: S3C64XX: Fix build of Cragganmore after SPI changes
[deliverable/linux.git] / arch / arm / mach-s3c64xx / mach-crag6410.c
CommitLineData
e1a3c74f
MB		 1/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * Copyright 2011 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/serial_core.h>
17#include <linux/platform_device.h>
18#include <linux/fb.h>
19#include <linux/io.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
66211f98 22#include <linux/leds.h>
e1a3c74f
MB		 23#include <linux/delay.h>
24#include <linux/regulator/machine.h>
ae24c263 25#include <linux/regulator/fixed.h>
e1a3c74f
MB		 26#include <linux/pwm_backlight.h>
27#include <linux/dm9000.h>
28#include <linux/gpio_keys.h>
29#include <linux/basic_mmio_gpio.h>
30#include <linux/spi/spi.h>
31
32#include <linux/i2c/pca953x.h>
33
34#include <video/platform_lcd.h>
35
36#include <linux/mfd/wm831x/core.h>
37#include <linux/mfd/wm831x/pdata.h>
ae24c263 38#include <linux/mfd/wm831x/irq.h>
e1a3c74f
MB		 39#include <linux/mfd/wm831x/gpio.h>
40
8504a3cb
MB		 41#include <sound/wm1250-ev1.h>
42
774b51f8 43#include <asm/hardware/vic.h>
e1a3c74f
MB		 44#include <asm/mach/arch.h>
45#include <asm/mach-types.h>
46
47#include <mach/hardware.h>
48#include <mach/map.h>
49
e1a3c74f
MB		 50#include <mach/regs-sys.h>
51#include <mach/regs-gpio.h>
52#include <mach/regs-modem.h>
d0f0b43f 53#include <mach/crag6410.h>
e1a3c74f 54
e1a3c74f
MB		 55#include <mach/regs-gpio-memport.h>
56
57#include <plat/regs-serial.h>
58#include <plat/regs-fb-v4.h>
59#include <plat/fb.h>
60#include <plat/sdhci.h>
61#include <plat/gpio-cfg.h>
62#include <plat/s3c64xx-spi.h>
63
64#include <plat/keypad.h>
65#include <plat/clock.h>
66#include <plat/devs.h>
67#include <plat/cpu.h>
68#include <plat/adc.h>
69#include <plat/iic.h>
70#include <plat/pm.h>
71
b024043b
KK		 72#include "common.h"
73
e1a3c74f
MB		 74/* serial port setup */
75
76#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
77#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
78#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
79
80static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
81 [0] = {
ae24c263
MB		 82 .hwport = 0,
83 .flags = 0,
84 .ucon = UCON,
85 .ulcon = ULCON,
86 .ufcon = UFCON,
e1a3c74f
MB		 87 },
88 [1] = {
ae24c263
MB		 89 .hwport = 1,
90 .flags = 0,
91 .ucon = UCON,
92 .ulcon = ULCON,
93 .ufcon = UFCON,
e1a3c74f
MB		 94 },
95 [2] = {
ae24c263
MB		 96 .hwport = 2,
97 .flags = 0,
98 .ucon = UCON,
99 .ulcon = ULCON,
100 .ufcon = UFCON,
e1a3c74f
MB		 101 },
102 [3] = {
ae24c263
MB		 103 .hwport = 3,
104 .flags = 0,
105 .ucon = UCON,
106 .ulcon = ULCON,
107 .ufcon = UFCON,
e1a3c74f
MB		 108 },
109};
110
111static struct platform_pwm_backlight_data crag6410_backlight_data = {
112 .pwm_id = 0,
113 .max_brightness = 1000,
114 .dft_brightness = 600,
115 .pwm_period_ns = 100000, /* about 1kHz */
116};
117
118static struct platform_device crag6410_backlight_device = {
119 .name = "pwm-backlight",
120 .id = -1,
121 .dev = {
122 .parent = &s3c_device_timer[0].dev,
123 .platform_data = &crag6410_backlight_data,
124 },
125};
126
127static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
128{
129 pr_debug("%s: setting power %d\n", __func__, power);
130
131 if (power) {
132 gpio_set_value(S3C64XX_GPB(0), 1);
133 msleep(1);
134 s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
135 } else {
136 gpio_direction_output(S3C64XX_GPF(14), 0);
137 gpio_set_value(S3C64XX_GPB(0), 0);
138 }
139}
140
141static struct platform_device crag6410_lcd_powerdev = {
142 .name = "platform-lcd",
143 .id = -1,
144 .dev.parent = &s3c_device_fb.dev,
145 .dev.platform_data = &(struct plat_lcd_data) {
146 .set_power = crag6410_lcd_power_set,
147 },
148};
149
150/* 640x480 URT */
151static struct s3c_fb_pd_win crag6410_fb_win0 = {
152 /* this is to ensure we use win0 */
153 .win_mode = {
154 .left_margin = 150,
155 .right_margin = 80,
156 .upper_margin = 40,
157 .lower_margin = 5,
158 .hsync_len = 40,
159 .vsync_len = 5,
160 .xres = 640,
161 .yres = 480,
162 },
163 .max_bpp = 32,
164 .default_bpp = 16,
165 .virtual_y = 480 * 2,
166 .virtual_x = 640,
167};
168
169/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
170static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
171 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
172 .win[0] = &crag6410_fb_win0,
173 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
174 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
175};
176
177/* 2x6 keypad */
178
179static uint32_t crag6410_keymap[] __initdata = {
180 /* KEY(row, col, keycode) */
181 KEY(0, 0, KEY_VOLUMEUP),
182 KEY(0, 1, KEY_HOME),
183 KEY(0, 2, KEY_VOLUMEDOWN),
184 KEY(0, 3, KEY_HELP),
185 KEY(0, 4, KEY_MENU),
186 KEY(0, 5, KEY_MEDIA),
187 KEY(1, 0, 232),
188 KEY(1, 1, KEY_DOWN),
189 KEY(1, 2, KEY_LEFT),
190 KEY(1, 3, KEY_UP),
191 KEY(1, 4, KEY_RIGHT),
192 KEY(1, 5, KEY_CAMERA),
193};
194
195static struct matrix_keymap_data crag6410_keymap_data __initdata = {
196 .keymap = crag6410_keymap,
197 .keymap_size = ARRAY_SIZE(crag6410_keymap),
198};
199
200static struct samsung_keypad_platdata crag6410_keypad_data __initdata = {
201 .keymap_data = &crag6410_keymap_data,
202 .rows = 2,
203 .cols = 6,
204};
205
206static struct gpio_keys_button crag6410_gpio_keys[] = {
207 [0] = {
208 .code = KEY_SUSPEND,
209 .gpio = S3C64XX_GPL(10), /* EINT 18 */
ae24c263 210 .type = EV_KEY,
e1a3c74f
MB		 211 .wakeup = 1,
212 .active_low = 1,
213 },
ae24c263
MB		 214 [1] = {
215 .code = SW_FRONT_PROXIMITY,
216 .gpio = S3C64XX_GPN(11), /* EINT 11 */
217 .type = EV_SW,
218 },
e1a3c74f
MB		 219};
220
221static struct gpio_keys_platform_data crag6410_gpio_keydata = {
222 .buttons = crag6410_gpio_keys,
223 .nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
224};
225
226static struct platform_device crag6410_gpio_keydev = {
227 .name = "gpio-keys",
228 .id = 0,
229 .dev.platform_data = &crag6410_gpio_keydata,
230};
231
232static struct resource crag6410_dm9k_resource[] = {
233 [0] = {
234 .start = S3C64XX_PA_XM0CSN5,
235 .end = S3C64XX_PA_XM0CSN5 + 1,
236 .flags = IORESOURCE_MEM,
237 },
238 [1] = {
239 .start = S3C64XX_PA_XM0CSN5 + (1 << 8),
240 .end = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1,
241 .flags = IORESOURCE_MEM,
242 },
243 [2] = {
244 .start = S3C_EINT(17),
245 .end = S3C_EINT(17),
246 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
247 },
248};
249
250static struct dm9000_plat_data mini6410_dm9k_pdata = {
251 .flags = DM9000_PLATF_16BITONLY,
252};
253
254static struct platform_device crag6410_dm9k_device = {
255 .name = "dm9000",
256 .id = -1,
257 .num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
258 .resource = crag6410_dm9k_resource,
259 .dev.platform_data = &mini6410_dm9k_pdata,
260};
261
262static struct resource crag6410_mmgpio_resource[] = {
263 [0] = {
91b60b1d 264 .name = "dat",
e1a3c74f
MB		 265 .start = S3C64XX_PA_XM0CSN4 + 1,
266 .end = S3C64XX_PA_XM0CSN4 + 1,
267 .flags = IORESOURCE_MEM,
268 },
269};
270
271static struct platform_device crag6410_mmgpio = {
272 .name = "basic-mmio-gpio",
273 .id = -1,
274 .resource = crag6410_mmgpio_resource,
275 .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
276 .dev.platform_data = &(struct bgpio_pdata) {
91b60b1d 277 .base = MMGPIO_GPIO_BASE,
e1a3c74f
MB		 278 },
279};
280
ae24c263
MB		 281static struct platform_device speyside_device = {
282 .name = "speyside",
283 .id = -1,
284};
285
8c051ab4
MB		 286static struct platform_device lowland_device = {
287 .name = "lowland",
288 .id = -1,
289};
290
6414261f
MB		 291static struct platform_device tobermory_device = {
292 .name = "tobermory",
ae24c263
MB		 293 .id = -1,
294};
295
c5c32c96
MB		 296static struct platform_device littlemill_device = {
297 .name = "littlemill",
298 .id = -1,
299};
300
ae24c263
MB		 301static struct regulator_consumer_supply wallvdd_consumers[] = {
302 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
303 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
4ed12b50
MB		 304 REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
305 REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
ae24c263
MB		 306};
307
308static struct regulator_init_data wallvdd_data = {
309 .constraints = {
310 .always_on = 1,
311 },
312 .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
313 .consumer_supplies = wallvdd_consumers,
314};
315
316static struct fixed_voltage_config wallvdd_pdata = {
317 .supply_name = "WALLVDD",
318 .microvolts = 5000000,
319 .init_data = &wallvdd_data,
320 .gpio = -EINVAL,
321};
322
323static struct platform_device wallvdd_device = {
324 .name = "reg-fixed-voltage",
325 .id = -1,
326 .dev = {
327 .platform_data = &wallvdd_pdata,
328 },
329};
330
e1a3c74f
MB		 331static struct platform_device *crag6410_devices[] __initdata = {
332 &s3c_device_hsmmc0,
e1a3c74f
MB		 333 &s3c_device_hsmmc2,
334 &s3c_device_i2c0,
335 &s3c_device_i2c1,
336 &s3c_device_fb,
337 &s3c_device_ohci,
338 &s3c_device_usb_hsotg,
e1a3c74f
MB		 339 &s3c_device_timer[0],
340 &s3c64xx_device_iis0,
341 &s3c64xx_device_iis1,
342 &samsung_asoc_dma,
343 &samsung_device_keypad,
344 &crag6410_gpio_keydev,
345 &crag6410_dm9k_device,
346 &s3c64xx_device_spi0,
347 &crag6410_mmgpio,
348 &crag6410_lcd_powerdev,
349 &crag6410_backlight_device,
ae24c263 350 &speyside_device,
6414261f 351 &tobermory_device,
c5c32c96 352 &littlemill_device,
8c051ab4 353 &lowland_device,
ae24c263 354 &wallvdd_device,
e1a3c74f
MB		 355};
356
357static struct pca953x_platform_data crag6410_pca_data = {
358 .gpio_base = PCA935X_GPIO_BASE,
6e11e0bd 359 .irq_base = -1,
e1a3c74f
MB		 360};
361
986afc98
MB		 362/* VDDARM is controlled by DVS1 connected to GPK(0) */
363static struct wm831x_buckv_pdata vddarm_pdata = {
364 .dvs_control_src = 1,
365 .dvs_gpio = S3C64XX_GPK(0),
366};
367
e1a3c74f
MB		 368static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
369 REGULATOR_SUPPLY("vddarm", NULL),
370};
371
372static struct regulator_init_data vddarm __initdata = {
373 .constraints = {
374 .name = "VDDARM",
375 .min_uV = 1000000,
376 .max_uV = 1300000,
377 .always_on = 1,
378 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
379 },
380 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
381 .consumer_supplies = vddarm_consumers,
35127296 382 .supply_regulator = "WALLVDD",
986afc98 383 .driver_data = &vddarm_pdata,
e1a3c74f
MB		 384};
385
39cb263e
MB		 386static struct regulator_consumer_supply vddint_consumers[] __initdata = {
387 REGULATOR_SUPPLY("vddint", NULL),
388};
389
e1a3c74f
MB		 390static struct regulator_init_data vddint __initdata = {
391 .constraints = {
392 .name = "VDDINT",
393 .min_uV = 1000000,
394 .max_uV = 1200000,
395 .always_on = 1,
396 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
397 },
39cb263e
MB		 398 .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
399 .consumer_supplies = vddint_consumers,
400 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 401};
402
403static struct regulator_init_data vddmem __initdata = {
404 .constraints = {
405 .name = "VDDMEM",
406 .always_on = 1,
407 },
408};
409
410static struct regulator_init_data vddsys __initdata = {
411 .constraints = {
412 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
413 .always_on = 1,
414 },
415};
416
417static struct regulator_consumer_supply vddmmc_consumers[] __initdata = {
418 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
419 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
420 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
421};
422
423static struct regulator_init_data vddmmc __initdata = {
424 .constraints = {
425 .name = "VDDMMC,UH",
426 .always_on = 1,
427 },
428 .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
429 .consumer_supplies = vddmmc_consumers,
35127296 430 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 431};
432
433static struct regulator_init_data vddotgi __initdata = {
434 .constraints = {
435 .name = "VDDOTGi",
436 .always_on = 1,
437 },
35127296 438 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 439};
440
441static struct regulator_init_data vddotg __initdata = {
442 .constraints = {
443 .name = "VDDOTG",
444 .always_on = 1,
445 },
35127296 446 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 447};
448
449static struct regulator_init_data vddhi __initdata = {
450 .constraints = {
451 .name = "VDDHI",
452 .always_on = 1,
453 },
35127296 454 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 455};
456
457static struct regulator_init_data vddadc __initdata = {
458 .constraints = {
459 .name = "VDDADC,VDDDAC",
460 .always_on = 1,
461 },
35127296 462 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 463};
464
465static struct regulator_init_data vddmem0 __initdata = {
466 .constraints = {
467 .name = "VDDMEM0",
468 .always_on = 1,
469 },
35127296 470 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 471};
472
473static struct regulator_init_data vddpll __initdata = {
474 .constraints = {
475 .name = "VDDPLL",
476 .always_on = 1,
477 },
35127296 478 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 479};
480
481static struct regulator_init_data vddlcd __initdata = {
482 .constraints = {
483 .name = "VDDLCD",
484 .always_on = 1,
485 },
35127296 486 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 487};
488
489static struct regulator_init_data vddalive __initdata = {
490 .constraints = {
491 .name = "VDDALIVE",
492 .always_on = 1,
493 },
35127296 494 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 495};
496
89e1c3d0
MB		 497static struct wm831x_backup_pdata banff_backup_pdata __initdata = {
498 .charger_enable = 1,
499 .vlim = 2500, /* mV */
500 .ilim = 200, /* uA */
501};
502
e1a3c74f
MB		 503static struct wm831x_status_pdata banff_red_led __initdata = {
504 .name = "banff:red:",
505 .default_src = WM831X_STATUS_MANUAL,
506};
507
508static struct wm831x_status_pdata banff_green_led __initdata = {
509 .name = "banff:green:",
510 .default_src = WM831X_STATUS_MANUAL,
511};
512
513static struct wm831x_touch_pdata touch_pdata __initdata = {
514 .data_irq = S3C_EINT(26),
ae24c263 515 .pd_irq = S3C_EINT(27),
e1a3c74f
MB		 516};
517
e1a3c74f 518static struct wm831x_pdata crag_pmic_pdata __initdata = {
ae24c263 519 .wm831x_num = 1,
e1a3c74f 520 .irq_base = BANFF_PMIC_IRQ_BASE,
aaed44e1 521 .gpio_base = BANFF_PMIC_GPIO_BASE,
dcf3580a 522 .soft_shutdown = true,
e1a3c74f 523
89e1c3d0
MB		 524 .backup = &banff_backup_pdata,
525
ae24c263 526 .gpio_defaults = {
986afc98
MB		 527 /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
528 [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
ae24c263
MB		 529 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
530 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
531 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
532 [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
533 },
534
e1a3c74f
MB		 535 .dcdc = {
536 &vddarm, /* DCDC1 */
537 &vddint, /* DCDC2 */
538 &vddmem, /* DCDC3 */
539 },
540
541 .ldo = {
542 &vddsys, /* LDO1 */
543 &vddmmc, /* LDO2 */
544 NULL, /* LDO3 */
545 &vddotgi, /* LDO4 */
546 &vddotg, /* LDO5 */
547 &vddhi, /* LDO6 */
548 &vddadc, /* LDO7 */
549 &vddmem0, /* LDO8 */
550 &vddpll, /* LDO9 */
551 &vddlcd, /* LDO10 */
552 &vddalive, /* LDO11 */
553 },
554
555 .status = {
556 &banff_green_led,
557 &banff_red_led,
558 },
559
560 .touch = &touch_pdata,
561};
562
563static struct i2c_board_info i2c_devs0[] __initdata = {
564 { I2C_BOARD_INFO("24c08", 0x50), },
565 { I2C_BOARD_INFO("tca6408", 0x20),
566 .platform_data = &crag6410_pca_data,
567 },
568 { I2C_BOARD_INFO("wm8312", 0x34),
569 .platform_data = &crag_pmic_pdata,
570 .irq = S3C_EINT(23),
571 },
572};
573
574static struct s3c2410_platform_i2c i2c0_pdata = {
575 .frequency = 400000,
576};
577
ae24c263
MB		 578static struct regulator_init_data pvdd_1v2 __initdata = {
579 .constraints = {
580 .name = "PVDD_1V2",
581 .always_on = 1,
582 },
583};
584
585static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
d5160ecf 586 REGULATOR_SUPPLY("LDOVDD", "1-001a"),
ae24c263
MB		 587 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
588 REGULATOR_SUPPLY("DBVDD", "1-001a"),
4ed12b50
MB		 589 REGULATOR_SUPPLY("DBVDD1", "1-001a"),
590 REGULATOR_SUPPLY("DBVDD2", "1-001a"),
591 REGULATOR_SUPPLY("DBVDD3", "1-001a"),
ae24c263
MB		 592 REGULATOR_SUPPLY("CPVDD", "1-001a"),
593 REGULATOR_SUPPLY("AVDD2", "1-001a"),
594 REGULATOR_SUPPLY("DCVDD", "1-001a"),
595 REGULATOR_SUPPLY("AVDD", "1-001a"),
596};
597
598static struct regulator_init_data pvdd_1v8 __initdata = {
599 .constraints = {
600 .name = "PVDD_1V8",
601 .always_on = 1,
602 },
603
604 .consumer_supplies = pvdd_1v8_consumers,
605 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
606};
607
608static struct regulator_consumer_supply pvdd_3v3_consumers[] __initdata = {
609 REGULATOR_SUPPLY("MICVDD", "1-001a"),
610 REGULATOR_SUPPLY("AVDD1", "1-001a"),
611};
612
613static struct regulator_init_data pvdd_3v3 __initdata = {
614 .constraints = {
615 .name = "PVDD_3V3",
616 .always_on = 1,
617 },
618
619 .consumer_supplies = pvdd_3v3_consumers,
620 .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
621};
622
623static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
624 .wm831x_num = 2,
625 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
626 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
dcf3580a 627 .soft_shutdown = true,
ae24c263
MB		 628
629 .gpio_defaults = {
630 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
631 [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
632 [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
633 [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
634 },
635
636 .dcdc = {
637 &pvdd_1v2, /* DCDC1 */
638 &pvdd_1v8, /* DCDC2 */
639 &pvdd_3v3, /* DCDC3 */
640 },
641
642 .disable_touch = true,
643};
644
8504a3cb
MB		 645static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
646 .gpios = {
647 [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
648 [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
649 [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
650 [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
651 [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
652 },
653};
654
e1a3c74f
MB		 655static struct i2c_board_info i2c_devs1[] __initdata = {
656 { I2C_BOARD_INFO("wm8311", 0x34),
ae24c263
MB		 657 .irq = S3C_EINT(0),
658 .platform_data = &glenfarclas_pmic_pdata },
659
d0f0b43f
MB		 660 { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
661 { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
662 { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
663
8504a3cb
MB		 664 { I2C_BOARD_INFO("wm1250-ev1", 0x27),
665 .platform_data = &wm1250_ev1_pdata },
e1a3c74f
MB		 666};
667
8351c7aa
MB		 668static struct s3c2410_platform_i2c i2c1_pdata = {
669 .frequency = 400000,
670 .bus_num = 1,
e1a3c74f
MB		 671};
672
673static void __init crag6410_map_io(void)
674{
675 s3c64xx_init_io(NULL, 0);
676 s3c24xx_init_clocks(12000000);
677 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
678
679 /* LCD type and Bypass set by bootloader */
680}
681
682static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
683 .max_width = 4,
684 .cd_type = S3C_SDHCI_CD_PERMANENT,
685};
686
e1a3c74f
MB		 687static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
688{
689 /* Set all the necessary GPG pins to special-function 2 */
690 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
691
692 /* force card-detected for prototype 0 */
693 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
694}
695
696static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
697 .max_width = 4,
698 .cd_type = S3C_SDHCI_CD_INTERNAL,
699 .cfg_gpio = crag6410_cfg_sdhci0,
700};
701
66211f98
MB		 702static const struct gpio_led gpio_leds[] = {
703 {
704 .name = "d13:green:",
705 .gpio = MMGPIO_GPIO_BASE + 0,
706 .default_state = LEDS_GPIO_DEFSTATE_ON,
707 },
708 {
709 .name = "d14:green:",
710 .gpio = MMGPIO_GPIO_BASE + 1,
711 .default_state = LEDS_GPIO_DEFSTATE_ON,
712 },
713 {
714 .name = "d15:green:",
715 .gpio = MMGPIO_GPIO_BASE + 2,
716 .default_state = LEDS_GPIO_DEFSTATE_ON,
717 },
718 {
719 .name = "d16:green:",
720 .gpio = MMGPIO_GPIO_BASE + 3,
721 .default_state = LEDS_GPIO_DEFSTATE_ON,
722 },
723 {
724 .name = "d17:green:",
725 .gpio = MMGPIO_GPIO_BASE + 4,
726 .default_state = LEDS_GPIO_DEFSTATE_ON,
727 },
728 {
729 .name = "d18:green:",
730 .gpio = MMGPIO_GPIO_BASE + 5,
731 .default_state = LEDS_GPIO_DEFSTATE_ON,
732 },
733 {
734 .name = "d19:green:",
735 .gpio = MMGPIO_GPIO_BASE + 6,
736 .default_state = LEDS_GPIO_DEFSTATE_ON,
737 },
738 {
739 .name = "d20:green:",
740 .gpio = MMGPIO_GPIO_BASE + 7,
741 .default_state = LEDS_GPIO_DEFSTATE_ON,
742 },
743};
744
745static const struct gpio_led_platform_data gpio_leds_pdata = {
746 .leds = gpio_leds,
747 .num_leds = ARRAY_SIZE(gpio_leds),
748};
749
e1a3c74f
MB		 750static void __init crag6410_machine_init(void)
751{
752 /* Open drain IRQs need pullups */
753 s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
754 s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
755
756 gpio_request(S3C64XX_GPB(0), "LCD power");
757 gpio_direction_output(S3C64XX_GPB(0), 0);
758
759 gpio_request(S3C64XX_GPF(14), "LCD PWM");
760 gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
761
762 gpio_request(S3C64XX_GPB(1), "SD power");
763 gpio_direction_output(S3C64XX_GPB(1), 0);
764
765 gpio_request(S3C64XX_GPF(10), "nRESETSEL");
766 gpio_direction_output(S3C64XX_GPF(10), 1);
767
768 s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
e1a3c74f
MB		 769 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
770
771 s3c_i2c0_set_platdata(&i2c0_pdata);
8351c7aa 772 s3c_i2c1_set_platdata(&i2c1_pdata);
e1a3c74f
MB		 773 s3c_fb_set_platdata(&crag6410_lcd_pdata);
774
775 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
776 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
777
778 samsung_keypad_set_platdata(&crag6410_keypad_data);
6e2f2b4a 779 s3c64xx_spi0_set_platdata(NULL, 0, 1);
e1a3c74f
MB		 780
781 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
782
66211f98
MB		 783 gpio_led_register_device(-1, &gpio_leds_pdata);
784
ae24c263
MB		 785 regulator_has_full_constraints();
786
c656c306 787 s3c64xx_pm_init();
e1a3c74f
MB		 788}
789
790MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
791 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
170a5908 792 .atag_offset = 0x100,
e1a3c74f 793 .init_irq = s3c6410_init_irq,
774b51f8 794 .handle_irq = vic_handle_irq,
e1a3c74f
MB		 795 .map_io = crag6410_map_io,
796 .init_machine = crag6410_machine_init,
797 .timer = &s3c24xx_timer,
ff84ded2 798 .restart = s3c64xx_restart,
e1a3c74f 799MACHINE_END
Linux kernel - Deliverables
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