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ARM: S3C64XX: make regs-gpio-memport.h local
[deliverable/linux.git] / arch / arm / mach-s3c64xx / mach-crag6410.c
CommitLineData
e1a3c74f
MB		 1/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * Copyright 2011 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/serial_core.h>
17#include <linux/platform_device.h>
18#include <linux/fb.h>
19#include <linux/io.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
66211f98 22#include <linux/leds.h>
e1a3c74f 23#include <linux/delay.h>
fb7f60f3 24#include <linux/mmc/host.h>
e1a3c74f 25#include <linux/regulator/machine.h>
ae24c263 26#include <linux/regulator/fixed.h>
e1a3c74f
MB		 27#include <linux/pwm_backlight.h>
28#include <linux/dm9000.h>
29#include <linux/gpio_keys.h>
30#include <linux/basic_mmio_gpio.h>
31#include <linux/spi/spi.h>
32
33#include <linux/i2c/pca953x.h>
126625e1 34#include <linux/platform_data/s3c-hsotg.h>
e1a3c74f
MB		 35
36#include <video/platform_lcd.h>
37
38#include <linux/mfd/wm831x/core.h>
39#include <linux/mfd/wm831x/pdata.h>
ae24c263 40#include <linux/mfd/wm831x/irq.h>
e1a3c74f
MB		 41#include <linux/mfd/wm831x/gpio.h>
42
8504a3cb
MB		 43#include <sound/wm1250-ev1.h>
44
774b51f8 45#include <asm/hardware/vic.h>
e1a3c74f
MB		 46#include <asm/mach/arch.h>
47#include <asm/mach-types.h>
48
5a213a55 49#include <video/samsung_fimd.h>
e1a3c74f
MB		 50#include <mach/hardware.h>
51#include <mach/map.h>
52
e1a3c74f
MB		 53#include <mach/regs-sys.h>
54#include <mach/regs-gpio.h>
55#include <mach/regs-modem.h>
56
e1a3c74f 57#include <plat/regs-serial.h>
e1a3c74f
MB		 58#include <plat/fb.h>
59#include <plat/sdhci.h>
60#include <plat/gpio-cfg.h>
436d42c6 61#include <linux/platform_data/spi-s3c64xx.h>
e1a3c74f
MB		 62
63#include <plat/keypad.h>
64#include <plat/clock.h>
65#include <plat/devs.h>
66#include <plat/cpu.h>
67#include <plat/adc.h>
436d42c6 68#include <linux/platform_data/i2c-s3c2410.h>
e1a3c74f
MB		 69#include <plat/pm.h>
70
b024043b 71#include "common.h"
e6235928 72#include "crag6410.h"
8bb86ead 73#include "regs-gpio-memport.h"
b024043b 74
e1a3c74f
MB		 75/* serial port setup */
76
77#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
78#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
79#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
80
81static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
82 [0] = {
ae24c263
MB		 83 .hwport = 0,
84 .flags = 0,
85 .ucon = UCON,
86 .ulcon = ULCON,
87 .ufcon = UFCON,
e1a3c74f
MB		 88 },
89 [1] = {
ae24c263
MB		 90 .hwport = 1,
91 .flags = 0,
92 .ucon = UCON,
93 .ulcon = ULCON,
94 .ufcon = UFCON,
e1a3c74f
MB		 95 },
96 [2] = {
ae24c263
MB		 97 .hwport = 2,
98 .flags = 0,
99 .ucon = UCON,
100 .ulcon = ULCON,
101 .ufcon = UFCON,
e1a3c74f
MB		 102 },
103 [3] = {
ae24c263
MB		 104 .hwport = 3,
105 .flags = 0,
106 .ucon = UCON,
107 .ulcon = ULCON,
108 .ufcon = UFCON,
e1a3c74f
MB		 109 },
110};
111
112static struct platform_pwm_backlight_data crag6410_backlight_data = {
113 .pwm_id = 0,
114 .max_brightness = 1000,
115 .dft_brightness = 600,
116 .pwm_period_ns = 100000, /* about 1kHz */
117};
118
119static struct platform_device crag6410_backlight_device = {
120 .name = "pwm-backlight",
121 .id = -1,
122 .dev = {
123 .parent = &s3c_device_timer[0].dev,
124 .platform_data = &crag6410_backlight_data,
125 },
126};
127
128static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
129{
130 pr_debug("%s: setting power %d\n", __func__, power);
131
132 if (power) {
133 gpio_set_value(S3C64XX_GPB(0), 1);
134 msleep(1);
135 s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
136 } else {
137 gpio_direction_output(S3C64XX_GPF(14), 0);
138 gpio_set_value(S3C64XX_GPB(0), 0);
139 }
140}
141
142static struct platform_device crag6410_lcd_powerdev = {
143 .name = "platform-lcd",
144 .id = -1,
145 .dev.parent = &s3c_device_fb.dev,
146 .dev.platform_data = &(struct plat_lcd_data) {
147 .set_power = crag6410_lcd_power_set,
148 },
149};
150
151/* 640x480 URT */
152static struct s3c_fb_pd_win crag6410_fb_win0 = {
e1a3c74f
MB		 153 .max_bpp = 32,
154 .default_bpp = 16,
79d3c41a
TA		 155 .xres = 640,
156 .yres = 480,
e1a3c74f
MB		 157 .virtual_y = 480 * 2,
158 .virtual_x = 640,
159};
160
79d3c41a
TA		 161static struct fb_videomode crag6410_lcd_timing = {
162 .left_margin = 150,
163 .right_margin = 80,
164 .upper_margin = 40,
165 .lower_margin = 5,
166 .hsync_len = 40,
167 .vsync_len = 5,
168 .xres = 640,
169 .yres = 480,
170};
171
e1a3c74f 172/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
70660e5d 173static struct s3c_fb_platdata crag6410_lcd_pdata __devinitdata = {
e1a3c74f 174 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
79d3c41a 175 .vtiming = &crag6410_lcd_timing,
e1a3c74f
MB		 176 .win[0] = &crag6410_fb_win0,
177 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
178 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
179};
180
181/* 2x6 keypad */
182
70660e5d 183static uint32_t crag6410_keymap[] __devinitdata = {
e1a3c74f
MB		 184 /* KEY(row, col, keycode) */
185 KEY(0, 0, KEY_VOLUMEUP),
186 KEY(0, 1, KEY_HOME),
187 KEY(0, 2, KEY_VOLUMEDOWN),
188 KEY(0, 3, KEY_HELP),
189 KEY(0, 4, KEY_MENU),
190 KEY(0, 5, KEY_MEDIA),
191 KEY(1, 0, 232),
192 KEY(1, 1, KEY_DOWN),
193 KEY(1, 2, KEY_LEFT),
194 KEY(1, 3, KEY_UP),
195 KEY(1, 4, KEY_RIGHT),
196 KEY(1, 5, KEY_CAMERA),
197};
198
70660e5d 199static struct matrix_keymap_data crag6410_keymap_data __devinitdata = {
e1a3c74f
MB		 200 .keymap = crag6410_keymap,
201 .keymap_size = ARRAY_SIZE(crag6410_keymap),
202};
203
70660e5d 204static struct samsung_keypad_platdata crag6410_keypad_data __devinitdata = {
e1a3c74f
MB		 205 .keymap_data = &crag6410_keymap_data,
206 .rows = 2,
207 .cols = 6,
208};
209
210static struct gpio_keys_button crag6410_gpio_keys[] = {
211 [0] = {
212 .code = KEY_SUSPEND,
213 .gpio = S3C64XX_GPL(10), /* EINT 18 */
ae24c263 214 .type = EV_KEY,
e1a3c74f
MB		 215 .wakeup = 1,
216 .active_low = 1,
217 },
ae24c263
MB		 218 [1] = {
219 .code = SW_FRONT_PROXIMITY,
220 .gpio = S3C64XX_GPN(11), /* EINT 11 */
221 .type = EV_SW,
222 },
e1a3c74f
MB		 223};
224
225static struct gpio_keys_platform_data crag6410_gpio_keydata = {
226 .buttons = crag6410_gpio_keys,
227 .nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
228};
229
230static struct platform_device crag6410_gpio_keydev = {
231 .name = "gpio-keys",
232 .id = 0,
233 .dev.platform_data = &crag6410_gpio_keydata,
234};
235
236static struct resource crag6410_dm9k_resource[] = {
8ebf148a
TB		 237 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2),
238 [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2),
239 [2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \
240 | IORESOURCE_IRQ_HIGHLEVEL),
e1a3c74f
MB		 241};
242
243static struct dm9000_plat_data mini6410_dm9k_pdata = {
244 .flags = DM9000_PLATF_16BITONLY,
245};
246
247static struct platform_device crag6410_dm9k_device = {
248 .name = "dm9000",
249 .id = -1,
250 .num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
251 .resource = crag6410_dm9k_resource,
252 .dev.platform_data = &mini6410_dm9k_pdata,
253};
254
255static struct resource crag6410_mmgpio_resource[] = {
8ebf148a 256 [0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"),
e1a3c74f
MB		 257};
258
259static struct platform_device crag6410_mmgpio = {
260 .name = "basic-mmio-gpio",
261 .id = -1,
262 .resource = crag6410_mmgpio_resource,
263 .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
264 .dev.platform_data = &(struct bgpio_pdata) {
91b60b1d 265 .base = MMGPIO_GPIO_BASE,
e1a3c74f
MB		 266 },
267};
268
ae24c263
MB		 269static struct platform_device speyside_device = {
270 .name = "speyside",
271 .id = -1,
272};
273
8c051ab4
MB		 274static struct platform_device lowland_device = {
275 .name = "lowland",
276 .id = -1,
277};
278
6414261f
MB		 279static struct platform_device tobermory_device = {
280 .name = "tobermory",
ae24c263
MB		 281 .id = -1,
282};
283
c5c32c96
MB		 284static struct platform_device littlemill_device = {
285 .name = "littlemill",
286 .id = -1,
287};
288
3322914e 289static struct platform_device bells_wm2200_device = {
25752b78
MB		 290 .name = "bells",
291 .id = 0,
292};
293
3322914e 294static struct platform_device bells_wm5102_device = {
25752b78
MB		 295 .name = "bells",
296 .id = 1,
297};
298
3322914e
MB		 299static struct platform_device bells_wm5110_device = {
300 .name = "bells",
301 .id = 2,
302};
303
ae24c263 304static struct regulator_consumer_supply wallvdd_consumers[] = {
554f01fb 305 REGULATOR_SUPPLY("SPKVDD", "1-001a"),
ae24c263
MB		 306 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
307 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
4ed12b50
MB		 308 REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
309 REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
402f624b 310
479535ed
MB		 311 REGULATOR_SUPPLY("SPKVDDL", "spi0.1"),
312 REGULATOR_SUPPLY("SPKVDDR", "spi0.1"),
313 REGULATOR_SUPPLY("SPKVDDL", "wm5102-codec"),
314 REGULATOR_SUPPLY("SPKVDDR", "wm5102-codec"),
315 REGULATOR_SUPPLY("SPKVDDL", "wm5110-codec"),
316 REGULATOR_SUPPLY("SPKVDDR", "wm5110-codec"),
317
402f624b
MB		 318 REGULATOR_SUPPLY("DC1VDD", "0-0034"),
319 REGULATOR_SUPPLY("DC2VDD", "0-0034"),
320 REGULATOR_SUPPLY("DC3VDD", "0-0034"),
321 REGULATOR_SUPPLY("LDO1VDD", "0-0034"),
322 REGULATOR_SUPPLY("LDO2VDD", "0-0034"),
323 REGULATOR_SUPPLY("LDO4VDD", "0-0034"),
324 REGULATOR_SUPPLY("LDO5VDD", "0-0034"),
325 REGULATOR_SUPPLY("LDO6VDD", "0-0034"),
326 REGULATOR_SUPPLY("LDO7VDD", "0-0034"),
327 REGULATOR_SUPPLY("LDO8VDD", "0-0034"),
328 REGULATOR_SUPPLY("LDO9VDD", "0-0034"),
329 REGULATOR_SUPPLY("LDO10VDD", "0-0034"),
330 REGULATOR_SUPPLY("LDO11VDD", "0-0034"),
331
332 REGULATOR_SUPPLY("DC1VDD", "1-0034"),
333 REGULATOR_SUPPLY("DC2VDD", "1-0034"),
334 REGULATOR_SUPPLY("DC3VDD", "1-0034"),
f4fe3881
MB		 335 REGULATOR_SUPPLY("LDO1VDD", "1-0034"),
336 REGULATOR_SUPPLY("LDO2VDD", "1-0034"),
337 REGULATOR_SUPPLY("LDO4VDD", "1-0034"),
338 REGULATOR_SUPPLY("LDO5VDD", "1-0034"),
339 REGULATOR_SUPPLY("LDO6VDD", "1-0034"),
340 REGULATOR_SUPPLY("LDO7VDD", "1-0034"),
341 REGULATOR_SUPPLY("LDO8VDD", "1-0034"),
342 REGULATOR_SUPPLY("LDO9VDD", "1-0034"),
343 REGULATOR_SUPPLY("LDO10VDD", "1-0034"),
344 REGULATOR_SUPPLY("LDO11VDD", "1-0034"),
ae24c263
MB		 345};
346
347static struct regulator_init_data wallvdd_data = {
348 .constraints = {
349 .always_on = 1,
350 },
351 .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
352 .consumer_supplies = wallvdd_consumers,
353};
354
355static struct fixed_voltage_config wallvdd_pdata = {
356 .supply_name = "WALLVDD",
357 .microvolts = 5000000,
358 .init_data = &wallvdd_data,
359 .gpio = -EINVAL,
360};
361
362static struct platform_device wallvdd_device = {
363 .name = "reg-fixed-voltage",
364 .id = -1,
365 .dev = {
366 .platform_data = &wallvdd_pdata,
367 },
368};
369
e1a3c74f
MB		 370static struct platform_device *crag6410_devices[] __initdata = {
371 &s3c_device_hsmmc0,
e1a3c74f
MB		 372 &s3c_device_hsmmc2,
373 &s3c_device_i2c0,
374 &s3c_device_i2c1,
375 &s3c_device_fb,
376 &s3c_device_ohci,
377 &s3c_device_usb_hsotg,
e1a3c74f
MB		 378 &s3c_device_timer[0],
379 &s3c64xx_device_iis0,
380 &s3c64xx_device_iis1,
e1a3c74f
MB		 381 &samsung_device_keypad,
382 &crag6410_gpio_keydev,
383 &crag6410_dm9k_device,
384 &s3c64xx_device_spi0,
385 &crag6410_mmgpio,
386 &crag6410_lcd_powerdev,
387 &crag6410_backlight_device,
ae24c263 388 &speyside_device,
6414261f 389 &tobermory_device,
c5c32c96 390 &littlemill_device,
8c051ab4 391 &lowland_device,
3322914e 392 &bells_wm2200_device,
25752b78
MB		 393 &bells_wm5102_device,
394 &bells_wm5110_device,
ae24c263 395 &wallvdd_device,
e1a3c74f
MB		 396};
397
398static struct pca953x_platform_data crag6410_pca_data = {
399 .gpio_base = PCA935X_GPIO_BASE,
6e11e0bd 400 .irq_base = -1,
e1a3c74f
MB		 401};
402
986afc98
MB		 403/* VDDARM is controlled by DVS1 connected to GPK(0) */
404static struct wm831x_buckv_pdata vddarm_pdata = {
405 .dvs_control_src = 1,
406 .dvs_gpio = S3C64XX_GPK(0),
407};
408
70660e5d 409static struct regulator_consumer_supply vddarm_consumers[] __devinitdata = {
e1a3c74f
MB		 410 REGULATOR_SUPPLY("vddarm", NULL),
411};
412
70660e5d 413static struct regulator_init_data vddarm __devinitdata = {
e1a3c74f
MB		 414 .constraints = {
415 .name = "VDDARM",
416 .min_uV = 1000000,
417 .max_uV = 1300000,
418 .always_on = 1,
419 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
420 },
421 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
422 .consumer_supplies = vddarm_consumers,
35127296 423 .supply_regulator = "WALLVDD",
986afc98 424 .driver_data = &vddarm_pdata,
e1a3c74f
MB		 425};
426
70660e5d 427static struct regulator_consumer_supply vddint_consumers[] __devinitdata = {
39cb263e
MB		 428 REGULATOR_SUPPLY("vddint", NULL),
429};
430
70660e5d 431static struct regulator_init_data vddint __devinitdata = {
e1a3c74f
MB		 432 .constraints = {
433 .name = "VDDINT",
434 .min_uV = 1000000,
435 .max_uV = 1200000,
436 .always_on = 1,
437 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
438 },
39cb263e
MB		 439 .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
440 .consumer_supplies = vddint_consumers,
441 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 442};
443
70660e5d 444static struct regulator_init_data vddmem __devinitdata = {
e1a3c74f
MB		 445 .constraints = {
446 .name = "VDDMEM",
447 .always_on = 1,
448 },
449};
450
70660e5d 451static struct regulator_init_data vddsys __devinitdata = {
e1a3c74f
MB		 452 .constraints = {
453 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
454 .always_on = 1,
455 },
456};
457
70660e5d 458static struct regulator_consumer_supply vddmmc_consumers[] __devinitdata = {
e1a3c74f
MB		 459 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
460 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
461 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
462};
463
70660e5d 464static struct regulator_init_data vddmmc __devinitdata = {
e1a3c74f
MB		 465 .constraints = {
466 .name = "VDDMMC,UH",
467 .always_on = 1,
468 },
469 .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
470 .consumer_supplies = vddmmc_consumers,
35127296 471 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 472};
473
70660e5d 474static struct regulator_init_data vddotgi __devinitdata = {
e1a3c74f
MB		 475 .constraints = {
476 .name = "VDDOTGi",
477 .always_on = 1,
478 },
35127296 479 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 480};
481
70660e5d 482static struct regulator_init_data vddotg __devinitdata = {
e1a3c74f
MB		 483 .constraints = {
484 .name = "VDDOTG",
485 .always_on = 1,
486 },
35127296 487 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 488};
489
70660e5d 490static struct regulator_init_data vddhi __devinitdata = {
e1a3c74f
MB		 491 .constraints = {
492 .name = "VDDHI",
493 .always_on = 1,
494 },
35127296 495 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 496};
497
70660e5d 498static struct regulator_init_data vddadc __devinitdata = {
e1a3c74f
MB		 499 .constraints = {
500 .name = "VDDADC,VDDDAC",
501 .always_on = 1,
502 },
35127296 503 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 504};
505
70660e5d 506static struct regulator_init_data vddmem0 __devinitdata = {
e1a3c74f
MB		 507 .constraints = {
508 .name = "VDDMEM0",
509 .always_on = 1,
510 },
35127296 511 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 512};
513
70660e5d 514static struct regulator_init_data vddpll __devinitdata = {
e1a3c74f
MB		 515 .constraints = {
516 .name = "VDDPLL",
517 .always_on = 1,
518 },
35127296 519 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 520};
521
70660e5d 522static struct regulator_init_data vddlcd __devinitdata = {
e1a3c74f
MB		 523 .constraints = {
524 .name = "VDDLCD",
525 .always_on = 1,
526 },
35127296 527 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 528};
529
70660e5d 530static struct regulator_init_data vddalive __devinitdata = {
e1a3c74f
MB		 531 .constraints = {
532 .name = "VDDALIVE",
533 .always_on = 1,
534 },
35127296 535 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 536};
537
70660e5d 538static struct wm831x_backup_pdata banff_backup_pdata __devinitdata = {
89e1c3d0
MB		 539 .charger_enable = 1,
540 .vlim = 2500, /* mV */
541 .ilim = 200, /* uA */
542};
543
70660e5d 544static struct wm831x_status_pdata banff_red_led __devinitdata = {
e1a3c74f
MB		 545 .name = "banff:red:",
546 .default_src = WM831X_STATUS_MANUAL,
547};
548
70660e5d 549static struct wm831x_status_pdata banff_green_led __devinitdata = {
e1a3c74f
MB		 550 .name = "banff:green:",
551 .default_src = WM831X_STATUS_MANUAL,
552};
553
70660e5d 554static struct wm831x_touch_pdata touch_pdata __devinitdata = {
e1a3c74f 555 .data_irq = S3C_EINT(26),
ae24c263 556 .pd_irq = S3C_EINT(27),
e1a3c74f
MB		 557};
558
70660e5d 559static struct wm831x_pdata crag_pmic_pdata __devinitdata = {
ae24c263 560 .wm831x_num = 1,
aaed44e1 561 .gpio_base = BANFF_PMIC_GPIO_BASE,
dcf3580a 562 .soft_shutdown = true,
e1a3c74f 563
89e1c3d0
MB		 564 .backup = &banff_backup_pdata,
565
ae24c263 566 .gpio_defaults = {
986afc98
MB		 567 /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
568 [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
ae24c263
MB		 569 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
570 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
571 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
572 [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
573 },
574
e1a3c74f
MB		 575 .dcdc = {
576 &vddarm, /* DCDC1 */
577 &vddint, /* DCDC2 */
578 &vddmem, /* DCDC3 */
579 },
580
581 .ldo = {
582 &vddsys, /* LDO1 */
583 &vddmmc, /* LDO2 */
584 NULL, /* LDO3 */
585 &vddotgi, /* LDO4 */
586 &vddotg, /* LDO5 */
587 &vddhi, /* LDO6 */
588 &vddadc, /* LDO7 */
589 &vddmem0, /* LDO8 */
590 &vddpll, /* LDO9 */
591 &vddlcd, /* LDO10 */
592 &vddalive, /* LDO11 */
593 },
594
595 .status = {
596 &banff_green_led,
597 &banff_red_led,
598 },
599
600 .touch = &touch_pdata,
601};
602
70660e5d 603static struct i2c_board_info i2c_devs0[] __devinitdata = {
e1a3c74f
MB		 604 { I2C_BOARD_INFO("24c08", 0x50), },
605 { I2C_BOARD_INFO("tca6408", 0x20),
606 .platform_data = &crag6410_pca_data,
607 },
608 { I2C_BOARD_INFO("wm8312", 0x34),
609 .platform_data = &crag_pmic_pdata,
610 .irq = S3C_EINT(23),
611 },
612};
613
614static struct s3c2410_platform_i2c i2c0_pdata = {
615 .frequency = 400000,
616};
617
70660e5d 618static struct regulator_consumer_supply pvdd_1v2_consumers[] __devinitdata = {
cda2349a
MB		 619 REGULATOR_SUPPLY("DCVDD", "spi0.0"),
620 REGULATOR_SUPPLY("AVDD", "spi0.0"),
479535ed 621 REGULATOR_SUPPLY("AVDD", "spi0.1"),
cda2349a
MB		 622};
623
70660e5d 624static struct regulator_init_data pvdd_1v2 __devinitdata = {
ae24c263
MB		 625 .constraints = {
626 .name = "PVDD_1V2",
cda2349a 627 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
ae24c263 628 },
cda2349a
MB		 629
630 .consumer_supplies = pvdd_1v2_consumers,
631 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
ae24c263
MB		 632};
633
70660e5d 634static struct regulator_consumer_supply pvdd_1v8_consumers[] __devinitdata = {
d5160ecf 635 REGULATOR_SUPPLY("LDOVDD", "1-001a"),
ae24c263
MB		 636 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
637 REGULATOR_SUPPLY("DBVDD", "1-001a"),
4ed12b50
MB		 638 REGULATOR_SUPPLY("DBVDD1", "1-001a"),
639 REGULATOR_SUPPLY("DBVDD2", "1-001a"),
640 REGULATOR_SUPPLY("DBVDD3", "1-001a"),
ae24c263
MB		 641 REGULATOR_SUPPLY("CPVDD", "1-001a"),
642 REGULATOR_SUPPLY("AVDD2", "1-001a"),
643 REGULATOR_SUPPLY("DCVDD", "1-001a"),
644 REGULATOR_SUPPLY("AVDD", "1-001a"),
cda2349a 645 REGULATOR_SUPPLY("DBVDD", "spi0.0"),
e6a194b7
MB		 646
647 REGULATOR_SUPPLY("DBVDD", "1-003a"),
648 REGULATOR_SUPPLY("LDOVDD", "1-003a"),
649 REGULATOR_SUPPLY("CPVDD", "1-003a"),
650 REGULATOR_SUPPLY("AVDD", "1-003a"),
479535ed
MB		 651 REGULATOR_SUPPLY("DBVDD1", "spi0.1"),
652 REGULATOR_SUPPLY("DBVDD2", "spi0.1"),
653 REGULATOR_SUPPLY("DBVDD3", "spi0.1"),
654 REGULATOR_SUPPLY("LDOVDD", "spi0.1"),
655 REGULATOR_SUPPLY("CPVDD", "spi0.1"),
656
657 REGULATOR_SUPPLY("DBVDD2", "wm5102-codec"),
658 REGULATOR_SUPPLY("DBVDD3", "wm5102-codec"),
659 REGULATOR_SUPPLY("CPVDD", "wm5102-codec"),
660
661 REGULATOR_SUPPLY("DBVDD2", "wm5110-codec"),
662 REGULATOR_SUPPLY("DBVDD3", "wm5110-codec"),
663 REGULATOR_SUPPLY("CPVDD", "wm5110-codec"),
ae24c263
MB		 664};
665
70660e5d 666static struct regulator_init_data pvdd_1v8 __devinitdata = {
ae24c263
MB		 667 .constraints = {
668 .name = "PVDD_1V8",
669 .always_on = 1,
670 },
671
672 .consumer_supplies = pvdd_1v8_consumers,
673 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
674};
675
70660e5d 676static struct regulator_consumer_supply pvdd_3v3_consumers[] __devinitdata = {
ae24c263
MB		 677 REGULATOR_SUPPLY("MICVDD", "1-001a"),
678 REGULATOR_SUPPLY("AVDD1", "1-001a"),
679};
680
70660e5d 681static struct regulator_init_data pvdd_3v3 __devinitdata = {
ae24c263
MB		 682 .constraints = {
683 .name = "PVDD_3V3",
684 .always_on = 1,
685 },
686
687 .consumer_supplies = pvdd_3v3_consumers,
688 .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
689};
690
70660e5d 691static struct wm831x_pdata glenfarclas_pmic_pdata __devinitdata = {
ae24c263
MB		 692 .wm831x_num = 2,
693 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
694 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
dcf3580a 695 .soft_shutdown = true,
ae24c263
MB		 696
697 .gpio_defaults = {
698 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
699 [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
700 [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
701 [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
702 },
703
704 .dcdc = {
705 &pvdd_1v2, /* DCDC1 */
706 &pvdd_1v8, /* DCDC2 */
707 &pvdd_3v3, /* DCDC3 */
708 },
709
710 .disable_touch = true,
711};
712
8504a3cb
MB		 713static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
714 .gpios = {
715 [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
716 [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
717 [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
718 [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
719 [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
720 },
721};
722
70660e5d 723static struct i2c_board_info i2c_devs1[] __devinitdata = {
e1a3c74f 724 { I2C_BOARD_INFO("wm8311", 0x34),
ae24c263
MB		 725 .irq = S3C_EINT(0),
726 .platform_data = &glenfarclas_pmic_pdata },
727
091cff0a 728 { I2C_BOARD_INFO("wlf-gf-module", 0x20) },
ea070cd2 729 { I2C_BOARD_INFO("wlf-gf-module", 0x22) },
d0f0b43f
MB		 730 { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
731 { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
732 { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
733
8504a3cb
MB		 734 { I2C_BOARD_INFO("wm1250-ev1", 0x27),
735 .platform_data = &wm1250_ev1_pdata },
e1a3c74f
MB		 736};
737
8351c7aa
MB		 738static struct s3c2410_platform_i2c i2c1_pdata = {
739 .frequency = 400000,
740 .bus_num = 1,
e1a3c74f
MB		 741};
742
743static void __init crag6410_map_io(void)
744{
745 s3c64xx_init_io(NULL, 0);
746 s3c24xx_init_clocks(12000000);
747 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
748
749 /* LCD type and Bypass set by bootloader */
750}
751
752static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
753 .max_width = 4,
754 .cd_type = S3C_SDHCI_CD_PERMANENT,
a9294cdc 755 .host_caps = MMC_CAP_POWER_OFF_CARD,
e1a3c74f
MB		 756};
757
e1a3c74f
MB		 758static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
759{
760 /* Set all the necessary GPG pins to special-function 2 */
761 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
762
763 /* force card-detected for prototype 0 */
764 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
765}
766
767static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
768 .max_width = 4,
769 .cd_type = S3C_SDHCI_CD_INTERNAL,
770 .cfg_gpio = crag6410_cfg_sdhci0,
fb7f60f3 771 .host_caps = MMC_CAP_POWER_OFF_CARD,
e1a3c74f
MB		 772};
773
66211f98
MB		 774static const struct gpio_led gpio_leds[] = {
775 {
776 .name = "d13:green:",
777 .gpio = MMGPIO_GPIO_BASE + 0,
778 .default_state = LEDS_GPIO_DEFSTATE_ON,
779 },
780 {
781 .name = "d14:green:",
782 .gpio = MMGPIO_GPIO_BASE + 1,
783 .default_state = LEDS_GPIO_DEFSTATE_ON,
784 },
785 {
786 .name = "d15:green:",
787 .gpio = MMGPIO_GPIO_BASE + 2,
788 .default_state = LEDS_GPIO_DEFSTATE_ON,
789 },
790 {
791 .name = "d16:green:",
792 .gpio = MMGPIO_GPIO_BASE + 3,
793 .default_state = LEDS_GPIO_DEFSTATE_ON,
794 },
795 {
796 .name = "d17:green:",
797 .gpio = MMGPIO_GPIO_BASE + 4,
798 .default_state = LEDS_GPIO_DEFSTATE_ON,
799 },
800 {
801 .name = "d18:green:",
802 .gpio = MMGPIO_GPIO_BASE + 5,
803 .default_state = LEDS_GPIO_DEFSTATE_ON,
804 },
805 {
806 .name = "d19:green:",
807 .gpio = MMGPIO_GPIO_BASE + 6,
808 .default_state = LEDS_GPIO_DEFSTATE_ON,
809 },
810 {
811 .name = "d20:green:",
812 .gpio = MMGPIO_GPIO_BASE + 7,
813 .default_state = LEDS_GPIO_DEFSTATE_ON,
814 },
815};
816
817static const struct gpio_led_platform_data gpio_leds_pdata = {
818 .leds = gpio_leds,
819 .num_leds = ARRAY_SIZE(gpio_leds),
e1a3c74f
MB		 820};
821
99f6e1f5
JS		 822static struct s3c_hsotg_plat crag6410_hsotg_pdata;
823
e1a3c74f
MB		 824static void __init crag6410_machine_init(void)
825{
826 /* Open drain IRQs need pullups */
827 s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
828 s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
829
830 gpio_request(S3C64XX_GPB(0), "LCD power");
831 gpio_direction_output(S3C64XX_GPB(0), 0);
832
833 gpio_request(S3C64XX_GPF(14), "LCD PWM");
834 gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
835
836 gpio_request(S3C64XX_GPB(1), "SD power");
837 gpio_direction_output(S3C64XX_GPB(1), 0);
838
839 gpio_request(S3C64XX_GPF(10), "nRESETSEL");
840 gpio_direction_output(S3C64XX_GPF(10), 1);
841
842 s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
e1a3c74f
MB		 843 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
844
845 s3c_i2c0_set_platdata(&i2c0_pdata);
8351c7aa 846 s3c_i2c1_set_platdata(&i2c1_pdata);
e1a3c74f 847 s3c_fb_set_platdata(&crag6410_lcd_pdata);
99f6e1f5 848 s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
e1a3c74f
MB		 849
850 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
851 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
852
853 samsung_keypad_set_platdata(&crag6410_keypad_data);
479535ed 854 s3c64xx_spi0_set_platdata(NULL, 0, 2);
e1a3c74f
MB		 855
856 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
857
66211f98
MB		 858 gpio_led_register_device(-1, &gpio_leds_pdata);
859
ae24c263
MB		 860 regulator_has_full_constraints();
861
c656c306 862 s3c64xx_pm_init();
e1a3c74f
MB		 863}
864
865MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
866 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
170a5908 867 .atag_offset = 0x100,
e1a3c74f 868 .init_irq = s3c6410_init_irq,
774b51f8 869 .handle_irq = vic_handle_irq,
e1a3c74f
MB		 870 .map_io = crag6410_map_io,
871 .init_machine = crag6410_machine_init,
cc8f252b 872 .init_late = s3c64xx_init_late,
e1a3c74f 873 .timer = &s3c24xx_timer,
ff84ded2 874 .restart = s3c64xx_restart,
e1a3c74f 875MACHINE_END
Linux kernel - Deliverables
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