[deliverable/linux.git] / arch / arm / mach-s3c64xx / mach-mini6410.c

/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
 *
 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/dm9000.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/serial_core.h>
#include <linux/types.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/map.h>
#include <mach/regs-gpio.h>

#include <plat/adc.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <plat/regs-serial.h>
#include <linux/platform_data/touchscreen-s3c2410.h>

#include <video/platform_lcd.h>
#include <video/samsung_fimd.h>

#include "common.h"
#include "regs-modem.h"
#include "regs-srom.h"

#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)

static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
	[0] = {
		.hwport	= 0,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[1] = {
		.hwport	= 1,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[2] = {
		.hwport	= 2,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[3] = {
		.hwport	= 3,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
};

/* DM9000AEP 10/100 ethernet controller */

static struct resource mini6410_dm9k_resource[] = {
	[0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
	[1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
	[2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
					| IORESOURCE_IRQ_HIGHLEVEL),
};

static struct dm9000_plat_data mini6410_dm9k_pdata = {
	.flags		= (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
};

static struct platform_device mini6410_device_eth = {
	.name		= "dm9000",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(mini6410_dm9k_resource),
	.resource	= mini6410_dm9k_resource,
	.dev		= {
		.platform_data	= &mini6410_dm9k_pdata,
	},
};

static struct mtd_partition mini6410_nand_part[] = {
	[0] = {
		.name	= "uboot",
		.size	= SZ_1M,
		.offset	= 0,
	},
	[1] = {
		.name	= "kernel",
		.size	= SZ_2M,
		.offset	= SZ_1M,
	},
	[2] = {
		.name	= "rootfs",
		.size	= MTDPART_SIZ_FULL,
		.offset	= SZ_1M + SZ_2M,
	},
};

static struct s3c2410_nand_set mini6410_nand_sets[] = {
	[0] = {
		.name		= "nand",
		.nr_chips	= 1,
		.nr_partitions	= ARRAY_SIZE(mini6410_nand_part),
		.partitions	= mini6410_nand_part,
	},
};

static struct s3c2410_platform_nand mini6410_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(mini6410_nand_sets),
	.sets		= mini6410_nand_sets,
};

static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
	.max_bpp	= 32,
	.default_bpp	= 16,
	.xres		= 480,
	.yres		= 272,
};

static struct fb_videomode mini6410_lcd_type0_timing = {
	/* 4.3" 480x272 */
	.left_margin	= 3,
	.right_margin	= 2,
	.upper_margin	= 1,
	.lower_margin	= 1,
	.hsync_len	= 40,
	.vsync_len	= 1,
	.xres		= 480,
	.yres		= 272,
};

static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
	.max_bpp	= 32,
	.default_bpp	= 16,
	.xres		= 800,
	.yres		= 480,
};

static struct fb_videomode mini6410_lcd_type1_timing = {
	/* 7.0" 800x480 */
	.left_margin	= 8,
	.right_margin	= 13,
	.upper_margin	= 7,
	.lower_margin	= 5,
	.hsync_len	= 3,
	.vsync_len	= 1,
	.xres		= 800,
	.yres		= 480,
};

static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
	{
		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
		.vtiming	= &mini6410_lcd_type0_timing,
		.win[0]		= &mini6410_lcd_type0_fb_win,
		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	}, {
		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
		.vtiming	= &mini6410_lcd_type1_timing,
		.win[0]		= &mini6410_lcd_type1_fb_win,
		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	},
	{ },
};

static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
				   unsigned int power)
{
	if (power)
		gpio_direction_output(S3C64XX_GPE(0), 1);
	else
		gpio_direction_output(S3C64XX_GPE(0), 0);
}

static struct plat_lcd_data mini6410_lcd_power_data = {
	.set_power	= mini6410_lcd_power_set,
};

static struct platform_device mini6410_lcd_powerdev = {
	.name			= "platform-lcd",
	.dev.parent		= &s3c_device_fb.dev,
	.dev.platform_data	= &mini6410_lcd_power_data,
};

static struct platform_device *mini6410_devices[] __initdata = {
	&mini6410_device_eth,
	&s3c_device_hsmmc0,
	&s3c_device_hsmmc1,
	&s3c_device_ohci,
	&s3c_device_nand,
	&s3c_device_fb,
	&mini6410_lcd_powerdev,
	&s3c_device_adc,
	&s3c_device_ts,
};

static void __init mini6410_map_io(void)
{
	u32 tmp;

	s3c64xx_init_io(NULL, 0);
	s3c24xx_init_clocks(12000000);
	s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));

	/* set the LCD type */
	tmp = __raw_readl(S3C64XX_SPCON);
	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
	__raw_writel(tmp, S3C64XX_SPCON);

	/* remove the LCD bypass */
	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	tmp &= ~MIFPCON_LCD_BYPASS;
	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}

/*
 * mini6410_features string
 *
 * 0-9 LCD configuration
 *
 */
static char mini6410_features_str[12] __initdata = "0";

static int __init mini6410_features_setup(char *str)
{
	if (str)
		strlcpy(mini6410_features_str, str,
			sizeof(mini6410_features_str));
	return 1;
}

__setup("mini6410=", mini6410_features_setup);

#define FEATURE_SCREEN (1 << 0)

struct mini6410_features_t {
	int done;
	int lcd_index;
};

static void mini6410_parse_features(
		struct mini6410_features_t *features,
		const char *features_str)
{
	const char *fp = features_str;

	features->done = 0;
	features->lcd_index = 0;

	while (*fp) {
		char f = *fp++;

		switch (f) {
		case '0'...'9':	/* tft screen */
			if (features->done & FEATURE_SCREEN) {
				printk(KERN_INFO "MINI6410: '%c' ignored, "
					"screen type already set\n", f);
			} else {
				int li = f - '0';
				if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
					printk(KERN_INFO "MINI6410: '%c' out "
						"of range LCD mode\n", f);
				else {
					features->lcd_index = li;
				}
			}
			features->done |= FEATURE_SCREEN;
			break;
		}
	}
}

static void __init mini6410_machine_init(void)
{
	u32 cs1;
	struct mini6410_features_t features = { 0 };

	printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
			mini6410_features_str);

	/* Parse the feature string */
	mini6410_parse_features(&features, mini6410_features_str);

	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
		mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
		mini6410_lcd_pdata[features.lcd_index].win[0]->yres);

	s3c_nand_set_platdata(&mini6410_nand_info);
	s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
	s3c24xx_ts_set_platdata(NULL);

	/* configure nCS1 width to 16 bits */

	cs1 = __raw_readl(S3C64XX_SROM_BW) &
		~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
			S3C64XX_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S3C64XX_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */

	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
		(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
		(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
		(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
		(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
		(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
		(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);

	gpio_request(S3C64XX_GPF(15), "LCD power");
	gpio_request(S3C64XX_GPE(0), "LCD power");

	platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
}

MACHINE_START(MINI6410, "MINI6410")
	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
	.atag_offset	= 0x100,
	.init_irq	= s3c6410_init_irq,
	.map_io		= mini6410_map_io,
	.init_machine	= mini6410_machine_init,
	.init_late	= s3c64xx_init_late,
	.init_time	= s3c24xx_timer_init,
	.restart	= s3c64xx_restart,
MACHINE_END
Commit	Line	Data
e9debd98 DA	1	/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
	2	*
	3	* Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
	4	* Copyright 2008 Openmoko, Inc.
	5	* Copyright 2008 Simtec Electronics
	6	* Ben Dooks <ben@simtec.co.uk>
	7	* http://armlinux.simtec.co.uk/
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/interrupt.h>
2abca87c	17	#include <linux/fb.h>
e9debd98 DA	18	#include <linux/gpio.h>
	19	#include <linux/kernel.h>
	20	#include <linux/list.h>
	21	#include <linux/dm9000.h>
1c5d76ef DA	22	#include <linux/mtd/mtd.h>
1c5d76ef DA	23	#include <linux/mtd/partitions.h>
e9debd98 DA	24	#include <linux/serial_core.h>
	25	#include <linux/types.h>
	26
	27	#include <asm/mach-types.h>
	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30
	31	#include <mach/map.h>
	32	#include <mach/regs-gpio.h>
e9debd98	33
fe894f97	34	#include <plat/adc.h>
e9debd98 DA	35	#include <plat/cpu.h>
e9debd98 DA	36	#include <plat/devs.h>
2abca87c	37	#include <plat/fb.h>
436d42c6	38	#include <linux/platform_data/mtd-nand-s3c2410.h>
e9debd98	39	#include <plat/regs-serial.h>
436d42c6	40	#include <linux/platform_data/touchscreen-s3c2410.h>
fe894f97	41
bbd7ac63	42	#include <video/platform_lcd.h>
5a213a55	43	#include <video/samsung_fimd.h>
e9debd98	44
b024043b	45	#include "common.h"
a81c1970	46	#include "regs-modem.h"
8eba8ea2	47	#include "regs-srom.h"
b024043b	48
8b8c87de	49	#define UCON S3C2410_UCON_DEFAULT
e9debd98 DA	50	#define ULCON (S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB)
	51	#define UFCON (S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE)
	52
	53	static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
	54	[0] = {
	55	.hwport = 0,
	56	.flags = 0,
	57	.ucon = UCON,
	58	.ulcon = ULCON,
	59	.ufcon = UFCON,
	60	},
	61	[1] = {
	62	.hwport = 1,
	63	.flags = 0,
	64	.ucon = UCON,
	65	.ulcon = ULCON,
	66	.ufcon = UFCON,
	67	},
	68	[2] = {
	69	.hwport = 2,
	70	.flags = 0,
	71	.ucon = UCON,
	72	.ulcon = ULCON,
	73	.ufcon = UFCON,
	74	},
	75	[3] = {
	76	.hwport = 3,
	77	.flags = 0,
	78	.ucon = UCON,
	79	.ulcon = ULCON,
	80	.ufcon = UFCON,
	81	},
	82	};
	83
	84	/* DM9000AEP 10/100 ethernet controller */
	85
	86	static struct resource mini6410_dm9k_resource[] = {
bc4521d3 TB	87	[0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
	88	[1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
	89	[2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
	90	\| IORESOURCE_IRQ_HIGHLEVEL),
e9debd98 DA	91	};
	92
	93	static struct dm9000_plat_data mini6410_dm9k_pdata = {
	94	.flags = (DM9000_PLATF_16BITONLY \| DM9000_PLATF_NO_EEPROM),
	95	};
	96
	97	static struct platform_device mini6410_device_eth = {
	98	.name = "dm9000",
	99	.id = -1,
	100	.num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
	101	.resource = mini6410_dm9k_resource,
	102	.dev = {
	103	.platform_data = &mini6410_dm9k_pdata,
	104	},
	105	};
	106
1c5d76ef DA	107	static struct mtd_partition mini6410_nand_part[] = {
	108	[0] = {
	109	.name = "uboot",
	110	.size = SZ_1M,
	111	.offset = 0,
	112	},
	113	[1] = {
	114	.name = "kernel",
	115	.size = SZ_2M,
	116	.offset = SZ_1M,
	117	},
	118	[2] = {
	119	.name = "rootfs",
	120	.size = MTDPART_SIZ_FULL,
	121	.offset = SZ_1M + SZ_2M,
	122	},
	123	};
	124
	125	static struct s3c2410_nand_set mini6410_nand_sets[] = {
	126	[0] = {
	127	.name = "nand",
	128	.nr_chips = 1,
	129	.nr_partitions = ARRAY_SIZE(mini6410_nand_part),
	130	.partitions = mini6410_nand_part,
	131	},
	132	};
	133
	134	static struct s3c2410_platform_nand mini6410_nand_info = {
	135	.tacls = 25,
	136	.twrph0 = 55,
	137	.twrph1 = 40,
	138	.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
	139	.sets = mini6410_nand_sets,
	140	};
	141
884924be	142	static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
884924be TA	143	.max_bpp = 32,
884924be TA	144	.default_bpp = 16,
79d3c41a TA	145	.xres = 480,
	146	.yres = 272,
	147	};
	148
	149	static struct fb_videomode mini6410_lcd_type0_timing = {
	150	/* 4.3" 480x272 */
	151	.left_margin = 3,
	152	.right_margin = 2,
	153	.upper_margin = 1,
	154	.lower_margin = 1,
	155	.hsync_len = 40,
	156	.vsync_len = 1,
	157	.xres = 480,
	158	.yres = 272,
2abca87c DA	159	};
2abca87c DA	160
884924be	161	static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
884924be TA	162	.max_bpp = 32,
884924be TA	163	.default_bpp = 16,
79d3c41a TA	164	.xres = 800,
	165	.yres = 480,
	166	};
	167
	168	static struct fb_videomode mini6410_lcd_type1_timing = {
	169	/* 7.0" 800x480 */
	170	.left_margin = 8,
	171	.right_margin = 13,
	172	.upper_margin = 7,
	173	.lower_margin = 5,
	174	.hsync_len = 3,
	175	.vsync_len = 1,
	176	.xres = 800,
	177	.yres = 480,
884924be TA	178	};
	179
	180	static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
2abca87c	181	{
884924be	182	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
79d3c41a	183	.vtiming = &mini6410_lcd_type0_timing,
884924be TA	184	.win[0] = &mini6410_lcd_type0_fb_win,
	185	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	186	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
2abca87c	187	}, {
884924be	188	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
79d3c41a	189	.vtiming = &mini6410_lcd_type1_timing,
884924be TA	190	.win[0] = &mini6410_lcd_type1_fb_win,
	191	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	192	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
2abca87c	193	},
884924be	194	{ },
2abca87c DA	195	};
2abca87c DA	196
bbd7ac63 DA	197	static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
	198	unsigned int power)
	199	{
	200	if (power)
	201	gpio_direction_output(S3C64XX_GPE(0), 1);
	202	else
	203	gpio_direction_output(S3C64XX_GPE(0), 0);
	204	}
	205
	206	static struct plat_lcd_data mini6410_lcd_power_data = {
	207	.set_power = mini6410_lcd_power_set,
	208	};
	209
	210	static struct platform_device mini6410_lcd_powerdev = {
	211	.name = "platform-lcd",
	212	.dev.parent = &s3c_device_fb.dev,
	213	.dev.platform_data = &mini6410_lcd_power_data,
	214	};
	215
e9debd98 DA	216	static struct platform_device *mini6410_devices[] __initdata = {
	217	&mini6410_device_eth,
	218	&s3c_device_hsmmc0,
	219	&s3c_device_hsmmc1,
	220	&s3c_device_ohci,
1c5d76ef	221	&s3c_device_nand,
2abca87c	222	&s3c_device_fb,
bbd7ac63	223	&mini6410_lcd_powerdev,
fe894f97 DA	224	&s3c_device_adc,
fe894f97 DA	225	&s3c_device_ts,
e9debd98 DA	226	};
	227
	228	static void __init mini6410_map_io(void)
	229	{
2abca87c DA	230	u32 tmp;
2abca87c DA	231
e9debd98 DA	232	s3c64xx_init_io(NULL, 0);
	233	s3c24xx_init_clocks(12000000);
	234	s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
2abca87c DA	235
	236	/* set the LCD type */
	237	tmp = __raw_readl(S3C64XX_SPCON);
	238	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	239	tmp \|= S3C64XX_SPCON_LCD_SEL_RGB;
	240	__raw_writel(tmp, S3C64XX_SPCON);
	241
	242	/* remove the LCD bypass */
	243	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	244	tmp &= ~MIFPCON_LCD_BYPASS;
	245	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
	246	}
	247
	248	/*
	249	* mini6410_features string
	250	*
	251	* 0-9 LCD configuration
	252	*
	253	*/
	254	static char mini6410_features_str[12] __initdata = "0";
	255
	256	static int __init mini6410_features_setup(char *str)
	257	{
	258	if (str)
	259	strlcpy(mini6410_features_str, str,
	260	sizeof(mini6410_features_str));
	261	return 1;
	262	}
	263
	264	__setup("mini6410=", mini6410_features_setup);
	265
	266	#define FEATURE_SCREEN (1 << 0)
	267
	268	struct mini6410_features_t {
	269	int done;
	270	int lcd_index;
	271	};
	272
	273	static void mini6410_parse_features(
	274	struct mini6410_features_t *features,
	275	const char *features_str)
	276	{
	277	const char *fp = features_str;
	278
	279	features->done = 0;
	280	features->lcd_index = 0;
	281
	282	while (*fp) {
	283	char f = *fp++;
	284
	285	switch (f) {
	286	case '0'...'9': /* tft screen */
	287	if (features->done & FEATURE_SCREEN) {
	288	printk(KERN_INFO "MINI6410: '%c' ignored, "
	289	"screen type already set\n", f);
	290	} else {
	291	int li = f - '0';
884924be	292	if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
2abca87c DA	293	printk(KERN_INFO "MINI6410: '%c' out "
	294	"of range LCD mode\n", f);
	295	else {
	296	features->lcd_index = li;
	297	}
	298	}
	299	features->done \|= FEATURE_SCREEN;
	300	break;
	301	}
	302	}
e9debd98 DA	303	}
	304
	305	static void __init mini6410_machine_init(void)
	306	{
	307	u32 cs1;
2abca87c DA	308	struct mini6410_features_t features = { 0 };
	309
	310	printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
	311	mini6410_features_str);
	312
	313	/* Parse the feature string */
	314	mini6410_parse_features(&features, mini6410_features_str);
	315
2abca87c	316	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
79d3c41a TA	317	mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
79d3c41a TA	318	mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
e9debd98	319
1c5d76ef	320	s3c_nand_set_platdata(&mini6410_nand_info);
884924be	321	s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
0804765a	322	s3c24xx_ts_set_platdata(NULL);
1c5d76ef	323
e9debd98 DA	324	/* configure nCS1 width to 16 bits */
	325
	326	cs1 = __raw_readl(S3C64XX_SROM_BW) &
	327	~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	328	cs1 \|= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) \|
	329	(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) \|
	330	(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
	331	S3C64XX_SROM_BW__NCS1__SHIFT;
	332	__raw_writel(cs1, S3C64XX_SROM_BW);
	333
	334	/* set timing for nCS1 suitable for ethernet chip */
	335
	336	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) \|
	337	(6 << S3C64XX_SROM_BCX__TACP__SHIFT) \|
	338	(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) \|
	339	(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) \|
	340	(13 << S3C64XX_SROM_BCX__TACC__SHIFT) \|
	341	(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) \|
	342	(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
	343
2abca87c DA	344	gpio_request(S3C64XX_GPF(15), "LCD power");
	345	gpio_request(S3C64XX_GPE(0), "LCD power");
	346
e9debd98 DA	347	platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
	348	}
	349
	350	MACHINE_START(MINI6410, "MINI6410")
	351	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
170a5908	352	.atag_offset = 0x100,
e9debd98 DA	353	.init_irq = s3c6410_init_irq,
	354	.map_io = mini6410_map_io,
	355	.init_machine = mini6410_machine_init,
cc8f252b	356	.init_late = s3c64xx_init_late,
6bb27d73	357	.init_time = s3c24xx_timer_init,
ff84ded2	358	.restart = s3c64xx_restart,
e9debd98	359	MACHINE_END