[deliverable/linux.git] / arch / arm / mach-s3c64xx / mach-real6410.c

/* linux/arch/arm/mach-s3c64xx/mach-real6410.c
 *
 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/dm9000.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/types.h>

#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>

#include <plat/adc.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <plat/ts.h>
#include <plat/regs-fb-v4.h>

#include <video/platform_lcd.h>

#include "common.h"

#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)

static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
	[0] = {
		.hwport	= 0,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[1] = {
		.hwport	= 1,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[2] = {
		.hwport	= 2,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[3] = {
		.hwport	= 3,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
};

/* DM9000AEP 10/100 ethernet controller */

static struct resource real6410_dm9k_resource[] = {
	[0] = {
		.start	= S3C64XX_PA_XM0CSN1,
		.end	= S3C64XX_PA_XM0CSN1 + 1,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start	= S3C64XX_PA_XM0CSN1 + 4,
		.end	= S3C64XX_PA_XM0CSN1 + 5,
		.flags	= IORESOURCE_MEM
	},
	[2] = {
		.start	= S3C_EINT(7),
		.end	= S3C_EINT(7),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
	}
};

static struct dm9000_plat_data real6410_dm9k_pdata = {
	.flags		= (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
};

static struct platform_device real6410_device_eth = {
	.name		= "dm9000",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(real6410_dm9k_resource),
	.resource	= real6410_dm9k_resource,
	.dev		= {
		.platform_data	= &real6410_dm9k_pdata,
	},
};

static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = {
	.win_mode	= {	/* 4.3" 480x272 */
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 1,
		.hsync_len	= 40,
		.vsync_len	= 1,
		.xres		= 480,
		.yres		= 272,
	},
	.max_bpp	= 32,
	.default_bpp	= 16,
};

static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = {
	.win_mode	= {	/* 7.0" 800x480 */
		.left_margin	= 8,
		.right_margin	= 13,
		.upper_margin	= 7,
		.lower_margin	= 5,
		.hsync_len	= 3,
		.vsync_len	= 1,
		.xres		= 800,
		.yres		= 480,
	},
	.max_bpp	= 32,
	.default_bpp	= 16,
};

static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = {
	{
		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
		.win[0]		= &real6410_lcd_type0_fb_win,
		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	}, {
		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
		.win[0]		= &real6410_lcd_type1_fb_win,
		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	},
	{ },
};

static struct mtd_partition real6410_nand_part[] = {
	[0] = {
		.name	= "uboot",
		.size	= SZ_1M,
		.offset	= 0,
	},
	[1] = {
		.name	= "kernel",
		.size	= SZ_2M,
		.offset	= SZ_1M,
	},
	[2] = {
		.name	= "rootfs",
		.size	= MTDPART_SIZ_FULL,
		.offset	= SZ_1M + SZ_2M,
	},
};

static struct s3c2410_nand_set real6410_nand_sets[] = {
	[0] = {
		.name		= "nand",
		.nr_chips	= 1,
		.nr_partitions	= ARRAY_SIZE(real6410_nand_part),
		.partitions	= real6410_nand_part,
	},
};

static struct s3c2410_platform_nand real6410_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(real6410_nand_sets),
	.sets		= real6410_nand_sets,
};

static struct platform_device *real6410_devices[] __initdata = {
	&real6410_device_eth,
	&s3c_device_hsmmc0,
	&s3c_device_hsmmc1,
	&s3c_device_fb,
	&s3c_device_nand,
	&s3c_device_adc,
	&s3c_device_ts,
	&s3c_device_ohci,
};

static void __init real6410_map_io(void)
{
	u32 tmp;

	s3c64xx_init_io(NULL, 0);
	s3c24xx_init_clocks(12000000);
	s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));

	/* set the LCD type */
	tmp = __raw_readl(S3C64XX_SPCON);
	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
	__raw_writel(tmp, S3C64XX_SPCON);

	/* remove the LCD bypass */
	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	tmp &= ~MIFPCON_LCD_BYPASS;
	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}

/*
 * real6410_features string
 *
 * 0-9 LCD configuration
 *
 */
static char real6410_features_str[12] __initdata = "0";

static int __init real6410_features_setup(char *str)
{
	if (str)
		strlcpy(real6410_features_str, str,
			sizeof(real6410_features_str));
	return 1;
}

__setup("real6410=", real6410_features_setup);

#define FEATURE_SCREEN (1 << 0)

struct real6410_features_t {
	int done;
	int lcd_index;
};

static void real6410_parse_features(
		struct real6410_features_t *features,
		const char *features_str)
{
	const char *fp = features_str;

	features->done = 0;
	features->lcd_index = 0;

	while (*fp) {
		char f = *fp++;

		switch (f) {
		case '0'...'9':	/* tft screen */
			if (features->done & FEATURE_SCREEN) {
				printk(KERN_INFO "REAL6410: '%c' ignored, "
					"screen type already set\n", f);
			} else {
				int li = f - '0';
				if (li >= ARRAY_SIZE(real6410_lcd_pdata))
					printk(KERN_INFO "REAL6410: '%c' out "
						"of range LCD mode\n", f);
				else {
					features->lcd_index = li;
				}
			}
			features->done |= FEATURE_SCREEN;
			break;
		}
	}
}

static void __init real6410_machine_init(void)
{
	u32 cs1;
	struct real6410_features_t features = { 0 };

	printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
			real6410_features_str);

	/* Parse the feature string */
	real6410_parse_features(&features, real6410_features_str);

	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);

	s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]);
	s3c_nand_set_platdata(&real6410_nand_info);
	s3c24xx_ts_set_platdata(NULL);

	/* configure nCS1 width to 16 bits */

	cs1 = __raw_readl(S3C64XX_SROM_BW) &
		~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
			S3C64XX_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S3C64XX_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */

	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
		(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
		(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
		(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
		(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
		(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
		(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);

	gpio_request(S3C64XX_GPF(15), "LCD power");

	platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
}

MACHINE_START(REAL6410, "REAL6410")
	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
	.atag_offset	= 0x100,

	.init_irq	= s3c6410_init_irq,
	.handle_irq	= vic_handle_irq,
	.map_io		= real6410_map_io,
	.init_machine	= real6410_machine_init,
	.timer		= &s3c24xx_timer,
	.restart	= s3c64xx_restart,
MACHINE_END
Commit	Line	Data
eab5cfa0 DA	1	/* linux/arch/arm/mach-s3c64xx/mach-real6410.c
	2	*
	3	* Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
	4	* Copyright 2008 Openmoko, Inc.
	5	* Copyright 2008 Simtec Electronics
	6	* Ben Dooks <ben@simtec.co.uk>
	7	* http://armlinux.simtec.co.uk/
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
c115f67c	15	#include <linux/init.h>
eab5cfa0	16	#include <linux/interrupt.h>
c115f67c DA	17	#include <linux/fb.h>
	18	#include <linux/gpio.h>
	19	#include <linux/kernel.h>
eab5cfa0	20	#include <linux/list.h>
ff266c0c	21	#include <linux/dm9000.h>
88fbadea DA	22	#include <linux/mtd/mtd.h>
88fbadea DA	23	#include <linux/mtd/partitions.h>
eab5cfa0	24	#include <linux/platform_device.h>
c115f67c DA	25	#include <linux/serial_core.h>
	26	#include <linux/types.h>
	27
774b51f8	28	#include <asm/hardware/vic.h>
eab5cfa0 DA	29	#include <asm/mach-types.h>
	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/map.h>
c115f67c	32
eab5cfa0	33	#include <mach/map.h>
c115f67c DA	34	#include <mach/regs-gpio.h>
c115f67c DA	35	#include <mach/regs-modem.h>
ff266c0c	36	#include <mach/regs-srom.h>
c115f67c	37
4374c456	38	#include <plat/adc.h>
eab5cfa0	39	#include <plat/cpu.h>
ce611d7b	40	#include <plat/devs.h>
c115f67c	41	#include <plat/fb.h>
88fbadea	42	#include <plat/nand.h>
eab5cfa0	43	#include <plat/regs-serial.h>
4374c456	44	#include <plat/ts.h>
49965e65	45	#include <plat/regs-fb-v4.h>
eab5cfa0	46
c115f67c	47	#include <video/platform_lcd.h>
eab5cfa0	48
b024043b KK	49	#include "common.h"
b024043b KK	50
8b8c87de	51	#define UCON S3C2410_UCON_DEFAULT
591cd25e DA	52	#define ULCON (S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB)
591cd25e DA	53	#define UFCON (S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE)
eab5cfa0 DA	54
	55	static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
	56	[0] = {
591cd25e DA	57	.hwport = 0,
	58	.flags = 0,
	59	.ucon = UCON,
	60	.ulcon = ULCON,
	61	.ufcon = UFCON,
eab5cfa0 DA	62	},
eab5cfa0 DA	63	[1] = {
591cd25e DA	64	.hwport = 1,
	65	.flags = 0,
	66	.ucon = UCON,
	67	.ulcon = ULCON,
	68	.ufcon = UFCON,
eab5cfa0 DA	69	},
eab5cfa0 DA	70	[2] = {
591cd25e DA	71	.hwport = 2,
	72	.flags = 0,
	73	.ucon = UCON,
	74	.ulcon = ULCON,
	75	.ufcon = UFCON,
eab5cfa0 DA	76	},
eab5cfa0 DA	77	[3] = {
591cd25e DA	78	.hwport = 3,
	79	.flags = 0,
	80	.ucon = UCON,
	81	.ulcon = ULCON,
	82	.ufcon = UFCON,
eab5cfa0 DA	83	},
	84	};
	85
ff266c0c DA	86	/* DM9000AEP 10/100 ethernet controller */
	87
	88	static struct resource real6410_dm9k_resource[] = {
591cd25e DA	89	[0] = {
	90	.start = S3C64XX_PA_XM0CSN1,
	91	.end = S3C64XX_PA_XM0CSN1 + 1,
	92	.flags = IORESOURCE_MEM
	93	},
	94	[1] = {
	95	.start = S3C64XX_PA_XM0CSN1 + 4,
	96	.end = S3C64XX_PA_XM0CSN1 + 5,
	97	.flags = IORESOURCE_MEM
	98	},
	99	[2] = {
	100	.start = S3C_EINT(7),
	101	.end = S3C_EINT(7),
4d89ecaa	102	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL
591cd25e	103	}
ff266c0c DA	104	};
	105
	106	static struct dm9000_plat_data real6410_dm9k_pdata = {
591cd25e	107	.flags = (DM9000_PLATF_16BITONLY \| DM9000_PLATF_NO_EEPROM),
ff266c0c DA	108	};
	109
	110	static struct platform_device real6410_device_eth = {
591cd25e DA	111	.name = "dm9000",
	112	.id = -1,
	113	.num_resources = ARRAY_SIZE(real6410_dm9k_resource),
	114	.resource = real6410_dm9k_resource,
	115	.dev = {
	116	.platform_data = &real6410_dm9k_pdata,
	117	},
ff266c0c DA	118	};
ff266c0c DA	119
884924be TA	120	static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = {
	121	.win_mode = { /* 4.3" 480x272 */
	122	.left_margin = 3,
	123	.right_margin = 2,
	124	.upper_margin = 1,
	125	.lower_margin = 1,
	126	.hsync_len = 40,
	127	.vsync_len = 1,
	128	.xres = 480,
	129	.yres = 272,
c115f67c	130	},
884924be TA	131	.max_bpp = 32,
884924be TA	132	.default_bpp = 16,
c115f67c DA	133	};
c115f67c DA	134
884924be TA	135	static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = {
	136	.win_mode = { /* 7.0" 800x480 */
	137	.left_margin = 8,
	138	.right_margin = 13,
	139	.upper_margin = 7,
	140	.lower_margin = 5,
	141	.hsync_len = 3,
	142	.vsync_len = 1,
	143	.xres = 800,
	144	.yres = 480,
	145	},
	146	.max_bpp = 32,
	147	.default_bpp = 16,
	148	};
	149
	150	static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = {
	151	{
	152	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
	153	.win[0] = &real6410_lcd_type0_fb_win,
	154	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	155	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	156	}, {
	157	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
	158	.win[0] = &real6410_lcd_type1_fb_win,
	159	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	160	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	161	},
	162	{ },
c115f67c DA	163	};
c115f67c DA	164
88fbadea DA	165	static struct mtd_partition real6410_nand_part[] = {
	166	[0] = {
	167	.name = "uboot",
	168	.size = SZ_1M,
	169	.offset = 0,
	170	},
	171	[1] = {
	172	.name = "kernel",
	173	.size = SZ_2M,
	174	.offset = SZ_1M,
	175	},
	176	[2] = {
	177	.name = "rootfs",
	178	.size = MTDPART_SIZ_FULL,
	179	.offset = SZ_1M + SZ_2M,
	180	},
	181	};
	182
	183	static struct s3c2410_nand_set real6410_nand_sets[] = {
	184	[0] = {
	185	.name = "nand",
	186	.nr_chips = 1,
	187	.nr_partitions = ARRAY_SIZE(real6410_nand_part),
	188	.partitions = real6410_nand_part,
	189	},
	190	};
	191
	192	static struct s3c2410_platform_nand real6410_nand_info = {
	193	.tacls = 25,
	194	.twrph0 = 55,
	195	.twrph1 = 40,
	196	.nr_sets = ARRAY_SIZE(real6410_nand_sets),
	197	.sets = real6410_nand_sets,
	198	};
	199
ff266c0c DA	200	static struct platform_device *real6410_devices[] __initdata = {
ff266c0c DA	201	&real6410_device_eth,
ce611d7b DA	202	&s3c_device_hsmmc0,
ce611d7b DA	203	&s3c_device_hsmmc1,
c115f67c	204	&s3c_device_fb,
88fbadea	205	&s3c_device_nand,
4374c456 DA	206	&s3c_device_adc,
4374c456 DA	207	&s3c_device_ts,
10dcc7a2	208	&s3c_device_ohci,
4374c456 DA	209	};
4374c456 DA	210
eab5cfa0 DA	211	static void __init real6410_map_io(void)
eab5cfa0 DA	212	{
c115f67c DA	213	u32 tmp;
c115f67c DA	214
eab5cfa0 DA	215	s3c64xx_init_io(NULL, 0);
	216	s3c24xx_init_clocks(12000000);
	217	s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
c115f67c DA	218
	219	/* set the LCD type */
	220	tmp = __raw_readl(S3C64XX_SPCON);
	221	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	222	tmp \|= S3C64XX_SPCON_LCD_SEL_RGB;
	223	__raw_writel(tmp, S3C64XX_SPCON);
	224
	225	/* remove the LCD bypass */
	226	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	227	tmp &= ~MIFPCON_LCD_BYPASS;
	228	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
	229	}
	230
	231	/*
	232	* real6410_features string
	233	*
	234	* 0-9 LCD configuration
	235	*
	236	*/
	237	static char real6410_features_str[12] __initdata = "0";
	238
	239	static int __init real6410_features_setup(char *str)
	240	{
	241	if (str)
	242	strlcpy(real6410_features_str, str,
	243	sizeof(real6410_features_str));
	244	return 1;
	245	}
	246
	247	__setup("real6410=", real6410_features_setup);
	248
	249	#define FEATURE_SCREEN (1 << 0)
	250
	251	struct real6410_features_t {
	252	int done;
	253	int lcd_index;
	254	};
	255
	256	static void real6410_parse_features(
	257	struct real6410_features_t *features,
	258	const char *features_str)
	259	{
	260	const char *fp = features_str;
	261
	262	features->done = 0;
	263	features->lcd_index = 0;
	264
	265	while (*fp) {
	266	char f = *fp++;
	267
	268	switch (f) {
	269	case '0'...'9': /* tft screen */
	270	if (features->done & FEATURE_SCREEN) {
	271	printk(KERN_INFO "REAL6410: '%c' ignored, "
	272	"screen type already set\n", f);
	273	} else {
	274	int li = f - '0';
884924be	275	if (li >= ARRAY_SIZE(real6410_lcd_pdata))
c115f67c DA	276	printk(KERN_INFO "REAL6410: '%c' out "
	277	"of range LCD mode\n", f);
	278	else {
	279	features->lcd_index = li;
	280	}
	281	}
	282	features->done \|= FEATURE_SCREEN;
	283	break;
	284	}
	285	}
eab5cfa0 DA	286	}
	287
	288	static void __init real6410_machine_init(void)
	289	{
ff266c0c	290	u32 cs1;
c115f67c DA	291	struct real6410_features_t features = { 0 };
	292
	293	printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
	294	real6410_features_str);
	295
	296	/* Parse the feature string */
	297	real6410_parse_features(&features, real6410_features_str);
	298
c115f67c	299	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
884924be TA	300	real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
884924be TA	301	real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
c115f67c	302
884924be	303	s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]);
88fbadea	304	s3c_nand_set_platdata(&real6410_nand_info);
0804765a	305	s3c24xx_ts_set_platdata(NULL);
ff266c0c DA	306
	307	/* configure nCS1 width to 16 bits */
	308
	309	cs1 = __raw_readl(S3C64XX_SROM_BW) &
	310	~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	311	cs1 \|= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) \|
	312	(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) \|
	313	(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
	314	S3C64XX_SROM_BW__NCS1__SHIFT;
	315	__raw_writel(cs1, S3C64XX_SROM_BW);
	316
	317	/* set timing for nCS1 suitable for ethernet chip */
	318
	319	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) \|
591cd25e DA	320	(6 << S3C64XX_SROM_BCX__TACP__SHIFT) \|
	321	(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) \|
	322	(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) \|
	323	(13 << S3C64XX_SROM_BCX__TACC__SHIFT) \|
	324	(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) \|
	325	(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
ff266c0c	326
c115f67c DA	327	gpio_request(S3C64XX_GPF(15), "LCD power");
c115f67c DA	328
ff266c0c	329	platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
eab5cfa0 DA	330	}
	331
	332	MACHINE_START(REAL6410, "REAL6410")
	333	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
170a5908	334	.atag_offset = 0x100,
eab5cfa0 DA	335
eab5cfa0 DA	336	.init_irq = s3c6410_init_irq,
774b51f8	337	.handle_irq = vic_handle_irq,
eab5cfa0 DA	338	.map_io = real6410_map_io,
	339	.init_machine = real6410_machine_init,
	340	.timer = &s3c24xx_timer,
ff84ded2	341	.restart = s3c64xx_restart,
eab5cfa0	342	MACHINE_END