ARM: S3C24XX: Add samsung-time support for s3c24xx
[deliverable/linux.git] / arch / arm / mach-s3c64xx / mach-smdk6410.c
CommitLineData
431107ea 1/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
5718df9d
BD
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
290d0983 20#include <linux/input.h>
5718df9d
BD
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
096941ed 24#include <linux/i2c.h>
a7a81d0b 25#include <linux/leds.h>
438a5d42
BD
26#include <linux/fb.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
3056ea0a 29#include <linux/smsc911x.h>
42015c13 30#include <linux/regulator/fixed.h>
628e7eb5 31#include <linux/regulator/machine.h>
075d1089 32#include <linux/pwm_backlight.h>
126625e1 33#include <linux/platform_data/s3c-hsotg.h>
438a5d42 34
ecc558ac
MB
35#ifdef CONFIG_SMDK6410_WM1190_EV1
36#include <linux/mfd/wm8350/core.h>
37#include <linux/mfd/wm8350/pmic.h>
38#endif
438a5d42 39
60f9101a 40#ifdef CONFIG_SMDK6410_WM1192_EV1
a7a81d0b 41#include <linux/mfd/wm831x/core.h>
60f9101a
MB
42#include <linux/mfd/wm831x/pdata.h>
43#endif
44
438a5d42 45#include <video/platform_lcd.h>
5a213a55 46#include <video/samsung_fimd.h>
5718df9d
BD
47
48#include <asm/mach/arch.h>
49#include <asm/mach/map.h>
50#include <asm/mach/irq.h>
51
52#include <mach/hardware.h>
53#include <mach/map.h>
54
55#include <asm/irq.h>
56#include <asm/mach-types.h>
57
58#include <plat/regs-serial.h>
3501c9ae 59#include <mach/regs-gpio.h>
436d42c6
AB
60#include <linux/platform_data/ata-samsung_cf.h>
61#include <linux/platform_data/i2c-s3c2410.h>
438a5d42 62#include <plat/fb.h>
3056ea0a 63#include <plat/gpio-cfg.h>
5718df9d 64
5718df9d
BD
65#include <plat/clock.h>
66#include <plat/devs.h>
67#include <plat/cpu.h>
85b14a3f 68#include <plat/adc.h>
436d42c6 69#include <linux/platform_data/touchscreen-s3c2410.h>
290d0983 70#include <plat/keypad.h>
96d78686 71#include <plat/backlight.h>
5718df9d 72
b024043b 73#include "common.h"
a81c1970 74#include "regs-modem.h"
8eba8ea2 75#include "regs-srom.h"
f2bfd174 76#include "regs-sys.h"
b024043b 77
5718df9d
BD
78#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
79#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
80#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
81
82static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
83 [0] = {
84 .hwport = 0,
85 .flags = 0,
bd258e52
MH
86 .ucon = UCON,
87 .ulcon = ULCON,
88 .ufcon = UFCON,
5718df9d
BD
89 },
90 [1] = {
91 .hwport = 1,
92 .flags = 0,
bd258e52
MH
93 .ucon = UCON,
94 .ulcon = ULCON,
95 .ufcon = UFCON,
96 },
97 [2] = {
98 .hwport = 2,
99 .flags = 0,
100 .ucon = UCON,
101 .ulcon = ULCON,
102 .ufcon = UFCON,
103 },
104 [3] = {
105 .hwport = 3,
106 .flags = 0,
107 .ucon = UCON,
108 .ulcon = ULCON,
109 .ufcon = UFCON,
5718df9d
BD
110 },
111};
112
438a5d42
BD
113/* framebuffer and LCD setup. */
114
115/* GPF15 = LCD backlight control
116 * GPF13 => Panel power
117 * GPN5 = LCD nRESET signal
118 * PWM_TOUT1 => backlight brightness
119 */
120
121static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
122 unsigned int power)
123{
124 if (power) {
125 gpio_direction_output(S3C64XX_GPF(13), 1);
438a5d42
BD
126
127 /* fire nRESET on power up */
128 gpio_direction_output(S3C64XX_GPN(5), 0);
129 msleep(10);
130 gpio_direction_output(S3C64XX_GPN(5), 1);
131 msleep(1);
132 } else {
438a5d42
BD
133 gpio_direction_output(S3C64XX_GPF(13), 0);
134 }
135}
136
137static struct plat_lcd_data smdk6410_lcd_power_data = {
138 .set_power = smdk6410_lcd_power_set,
139};
140
141static struct platform_device smdk6410_lcd_powerdev = {
142 .name = "platform-lcd",
143 .dev.parent = &s3c_device_fb.dev,
144 .dev.platform_data = &smdk6410_lcd_power_data,
145};
146
147static struct s3c_fb_pd_win smdk6410_fb_win0 = {
438a5d42
BD
148 .max_bpp = 32,
149 .default_bpp = 16,
79d3c41a
TA
150 .xres = 800,
151 .yres = 480,
001ca74f
BD
152 .virtual_y = 480 * 2,
153 .virtual_x = 800,
438a5d42
BD
154};
155
79d3c41a
TA
156static struct fb_videomode smdk6410_lcd_timing = {
157 .left_margin = 8,
158 .right_margin = 13,
159 .upper_margin = 7,
160 .lower_margin = 5,
161 .hsync_len = 3,
162 .vsync_len = 1,
163 .xres = 800,
164 .yres = 480,
165};
166
438a5d42
BD
167/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
168static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
169 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
79d3c41a 170 .vtiming = &smdk6410_lcd_timing,
438a5d42
BD
171 .win[0] = &smdk6410_fb_win0,
172 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
173 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
174};
175
a4e94694
AG
176/*
177 * Configuring Ethernet on SMDK6410
178 *
179 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
180 * The constant address below corresponds to nCS1
181 *
182 * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
183 * 2) CFG6 needs to be switched to "LAN9115" side
184 */
185
3056ea0a 186static struct resource smdk6410_smsc911x_resources[] = {
c858fd5f
TB
187 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, SZ_64K),
188 [1] = DEFINE_RES_NAMED(S3C_EINT(10), 1, NULL, IORESOURCE_IRQ \
189 | IRQ_TYPE_LEVEL_LOW),
3056ea0a
MB
190};
191
192static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
193 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
194 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
195 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
196 .phy_interface = PHY_INTERFACE_MODE_MII,
197};
198
199
200static struct platform_device smdk6410_smsc911x = {
201 .name = "smsc911x",
202 .id = -1,
203 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
204 .resource = &smdk6410_smsc911x_resources[0],
205 .dev = {
206 .platform_data = &smdk6410_smsc911x_pdata,
207 },
208};
209
42015c13 210#ifdef CONFIG_REGULATOR
b5930b83
MB
211static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = {
212 REGULATOR_SUPPLY("PVDD", "0-001b"),
213 REGULATOR_SUPPLY("AVDD", "0-001b"),
42015c13
MB
214};
215
216static struct regulator_init_data smdk6410_b_pwr_5v_data = {
217 .constraints = {
218 .always_on = 1,
219 },
220 .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
221 .consumer_supplies = smdk6410_b_pwr_5v_consumers,
222};
223
224static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
225 .supply_name = "B_PWR_5V",
226 .microvolts = 5000000,
227 .init_data = &smdk6410_b_pwr_5v_data,
d3cf4489 228 .gpio = -EINVAL,
42015c13
MB
229};
230
231static struct platform_device smdk6410_b_pwr_5v = {
232 .name = "reg-fixed-voltage",
233 .id = -1,
234 .dev = {
235 .platform_data = &smdk6410_b_pwr_5v_pdata,
236 },
237};
238#endif
239
0ab0b6d2
AK
240static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = {
241 .setup_gpio = s3c64xx_ide_setup_gpio,
242};
243
290d0983
NKC
244static uint32_t smdk6410_keymap[] __initdata = {
245 /* KEY(row, col, keycode) */
246 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
247 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
248 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
249 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
250};
251
252static struct matrix_keymap_data smdk6410_keymap_data __initdata = {
253 .keymap = smdk6410_keymap,
254 .keymap_size = ARRAY_SIZE(smdk6410_keymap),
255};
256
257static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
258 .keymap_data = &smdk6410_keymap_data,
259 .rows = 2,
260 .cols = 8,
261};
262
027191a8 263static struct map_desc smdk6410_iodesc[] = {};
5718df9d
BD
264
265static struct platform_device *smdk6410_devices[] __initdata = {
b24636cf 266#ifdef CONFIG_SMDK6410_SD_CH0
39057f23 267 &s3c_device_hsmmc0,
b24636cf
BD
268#endif
269#ifdef CONFIG_SMDK6410_SD_CH1
270 &s3c_device_hsmmc1,
271#endif
d85fa24c 272 &s3c_device_i2c0,
d7ea3743 273 &s3c_device_i2c1,
438a5d42 274 &s3c_device_fb,
b813248c 275 &s3c_device_ohci,
06fa1d37 276 &s3c_device_usb_hsotg,
1f100868 277 &s3c64xx_device_iisv4,
290d0983 278 &samsung_device_keypad,
42015c13
MB
279
280#ifdef CONFIG_REGULATOR
281 &smdk6410_b_pwr_5v,
282#endif
438a5d42 283 &smdk6410_lcd_powerdev,
3056ea0a
MB
284
285 &smdk6410_smsc911x,
85b14a3f 286 &s3c_device_adc,
0ab0b6d2 287 &s3c_device_cfcon,
9bbf4a63 288 &s3c_device_rtc,
85b14a3f 289 &s3c_device_ts,
b351c4a1 290 &s3c_device_wdt,
5718df9d
BD
291};
292
60f9101a
MB
293#ifdef CONFIG_REGULATOR
294/* ARM core */
295static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
b5930b83 296 REGULATOR_SUPPLY("vddarm", NULL),
60f9101a
MB
297};
298
299/* VDDARM, BUCK1 on J5 */
300static struct regulator_init_data smdk6410_vddarm = {
ecc558ac 301 .constraints = {
60f9101a
MB
302 .name = "PVDD_ARM",
303 .min_uV = 1000000,
304 .max_uV = 1300000,
305 .always_on = 1,
306 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
307 },
308 .num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
309 .consumer_supplies = smdk6410_vddarm_consumers,
310};
311
312/* VDD_INT, BUCK2 on J5 */
313static struct regulator_init_data smdk6410_vddint = {
314 .constraints = {
315 .name = "PVDD_INT",
316 .min_uV = 1000000,
ecc558ac
MB
317 .max_uV = 1200000,
318 .always_on = 1,
60f9101a 319 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
ecc558ac
MB
320 },
321};
322
60f9101a
MB
323/* VDD_HI, LDO3 on J5 */
324static struct regulator_init_data smdk6410_vddhi = {
ecc558ac 325 .constraints = {
60f9101a 326 .name = "PVDD_HI",
ecc558ac 327 .always_on = 1,
ecc558ac
MB
328 },
329};
330
60f9101a
MB
331/* VDD_PLL, LDO2 on J5 */
332static struct regulator_init_data smdk6410_vddpll = {
333 .constraints = {
334 .name = "PVDD_PLL",
335 .always_on = 1,
42015c13
MB
336 },
337};
338
60f9101a
MB
339/* VDD_UH_MMC, LDO5 on J5 */
340static struct regulator_init_data smdk6410_vdduh_mmc = {
ecc558ac 341 .constraints = {
18b52ca5 342 .name = "PVDD_UH+PVDD_MMC",
ecc558ac
MB
343 .always_on = 1,
344 },
345};
346
60f9101a
MB
347/* VCCM3BT, LDO8 on J5 */
348static struct regulator_init_data smdk6410_vccmc3bt = {
349 .constraints = {
350 .name = "PVCCM3BT",
351 .always_on = 1,
352 },
e3980b6a
MB
353};
354
60f9101a
MB
355/* VCCM2MTV, LDO11 on J5 */
356static struct regulator_init_data smdk6410_vccm2mtv = {
ecc558ac 357 .constraints = {
60f9101a
MB
358 .name = "PVCCM2MTV",
359 .always_on = 1,
360 },
361};
362
363/* VDD_LCD, LDO12 on J5 */
364static struct regulator_init_data smdk6410_vddlcd = {
365 .constraints = {
366 .name = "PVDD_LCD",
367 .always_on = 1,
368 },
369};
370
371/* VDD_OTGI, LDO9 on J5 */
372static struct regulator_init_data smdk6410_vddotgi = {
373 .constraints = {
374 .name = "PVDD_OTGI",
375 .always_on = 1,
376 },
377};
378
379/* VDD_OTG, LDO14 on J5 */
380static struct regulator_init_data smdk6410_vddotg = {
381 .constraints = {
382 .name = "PVDD_OTG",
ecc558ac
MB
383 .always_on = 1,
384 },
5718df9d
BD
385};
386
60f9101a
MB
387/* VDD_ALIVE, LDO15 on J5 */
388static struct regulator_init_data smdk6410_vddalive = {
ecc558ac
MB
389 .constraints = {
390 .name = "PVDD_ALIVE",
60f9101a
MB
391 .always_on = 1,
392 },
393};
394
395/* VDD_AUDIO, VLDO_AUDIO on J5 */
396static struct regulator_init_data smdk6410_vddaudio = {
397 .constraints = {
398 .name = "PVDD_AUDIO",
399 .always_on = 1,
400 },
401};
402#endif
403
404#ifdef CONFIG_SMDK6410_WM1190_EV1
405/* S3C64xx internal logic & PLL */
406static struct regulator_init_data wm8350_dcdc1_data = {
407 .constraints = {
18b52ca5 408 .name = "PVDD_INT+PVDD_PLL",
ecc558ac
MB
409 .min_uV = 1200000,
410 .max_uV = 1200000,
411 .always_on = 1,
412 .apply_uV = 1,
413 },
414};
415
60f9101a
MB
416/* Memory */
417static struct regulator_init_data wm8350_dcdc3_data = {
ecc558ac 418 .constraints = {
60f9101a
MB
419 .name = "PVDD_MEM",
420 .min_uV = 1800000,
421 .max_uV = 1800000,
f53aee29 422 .always_on = 1,
60f9101a
MB
423 .state_mem = {
424 .uV = 1800000,
425 .mode = REGULATOR_MODE_NORMAL,
426 .enabled = 1,
427 },
428 .initial_state = PM_SUSPEND_MEM,
ecc558ac
MB
429 },
430};
431
60f9101a
MB
432/* USB, EXT, PCM, ADC/DAC, USB, MMC */
433static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
b5930b83 434 REGULATOR_SUPPLY("DVDD", "0-001b"),
60f9101a
MB
435};
436
437static struct regulator_init_data wm8350_dcdc4_data = {
ecc558ac 438 .constraints = {
18b52ca5 439 .name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV",
ecc558ac
MB
440 .min_uV = 3000000,
441 .max_uV = 3000000,
f53aee29 442 .always_on = 1,
ecc558ac 443 },
60f9101a
MB
444 .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
445 .consumer_supplies = wm8350_dcdc4_consumers,
ecc558ac
MB
446};
447
448/* OTGi/1190-EV1 HPVDD & AVDD */
449static struct regulator_init_data wm8350_ldo4_data = {
450 .constraints = {
18b52ca5 451 .name = "PVDD_OTGI+HPVDD+AVDD",
ecc558ac
MB
452 .min_uV = 1200000,
453 .max_uV = 1200000,
454 .apply_uV = 1,
f53aee29 455 .always_on = 1,
ecc558ac
MB
456 },
457};
458
459static struct {
460 int regulator;
461 struct regulator_init_data *initdata;
462} wm1190_regulators[] = {
463 { WM8350_DCDC_1, &wm8350_dcdc1_data },
464 { WM8350_DCDC_3, &wm8350_dcdc3_data },
465 { WM8350_DCDC_4, &wm8350_dcdc4_data },
60f9101a
MB
466 { WM8350_DCDC_6, &smdk6410_vddarm },
467 { WM8350_LDO_1, &smdk6410_vddalive },
468 { WM8350_LDO_2, &smdk6410_vddotg },
469 { WM8350_LDO_3, &smdk6410_vddlcd },
ecc558ac
MB
470 { WM8350_LDO_4, &wm8350_ldo4_data },
471};
472
473static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
474{
475 int i;
476
a3323b72
MB
477 /* Configure the IRQ line */
478 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
479
ecc558ac
MB
480 /* Instantiate the regulators */
481 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
482 wm8350_register_regulator(wm8350,
483 wm1190_regulators[i].regulator,
484 wm1190_regulators[i].initdata);
485
486 return 0;
487}
488
489static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
490 .init = smdk6410_wm8350_init,
db9256f3 491 .irq_high = 1,
9fca8786 492 .irq_base = IRQ_BOARD_START,
ecc558ac
MB
493};
494#endif
495
60f9101a 496#ifdef CONFIG_SMDK6410_WM1192_EV1
a7a81d0b
MB
497static struct gpio_led wm1192_pmic_leds[] = {
498 {
499 .name = "PMIC:red:power",
500 .gpio = GPIO_BOARD_START + 3,
501 .default_state = LEDS_GPIO_DEFSTATE_ON,
502 },
503};
504
505static struct gpio_led_platform_data wm1192_pmic_led = {
506 .num_leds = ARRAY_SIZE(wm1192_pmic_leds),
507 .leds = wm1192_pmic_leds,
508};
509
510static struct platform_device wm1192_pmic_led_dev = {
511 .name = "leds-gpio",
512 .id = -1,
513 .dev = {
514 .platform_data = &wm1192_pmic_led,
515 },
516};
517
60f9101a
MB
518static int wm1192_pre_init(struct wm831x *wm831x)
519{
a7a81d0b
MB
520 int ret;
521
60f9101a
MB
522 /* Configure the IRQ line */
523 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
524
a7a81d0b
MB
525 ret = platform_device_register(&wm1192_pmic_led_dev);
526 if (ret != 0)
527 dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret);
528
60f9101a
MB
529 return 0;
530}
531
532static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
533 .isink = 1,
534 .max_uA = 27554,
535};
536
537static struct regulator_init_data wm1192_dcdc3 = {
538 .constraints = {
18b52ca5 539 .name = "PVDD_MEM+PVDD_GPS",
60f9101a
MB
540 .always_on = 1,
541 },
542};
543
544static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
b5930b83 545 REGULATOR_SUPPLY("DVDD", "0-001b"), /* WM8580 */
60f9101a
MB
546};
547
548static struct regulator_init_data wm1192_ldo1 = {
549 .constraints = {
18b52ca5 550 .name = "PVDD_LCD+PVDD_EXT",
60f9101a
MB
551 .always_on = 1,
552 },
553 .consumer_supplies = wm1192_ldo1_consumers,
554 .num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
555};
556
557static struct wm831x_status_pdata wm1192_led7_pdata = {
558 .name = "LED7:green:",
559};
560
561static struct wm831x_status_pdata wm1192_led8_pdata = {
562 .name = "LED8:green:",
563};
564
565static struct wm831x_pdata smdk6410_wm1192_pdata = {
566 .pre_init = wm1192_pre_init,
60f9101a
MB
567
568 .backlight = &wm1192_backlight_pdata,
569 .dcdc = {
570 &smdk6410_vddarm, /* DCDC1 */
571 &smdk6410_vddint, /* DCDC2 */
572 &wm1192_dcdc3,
573 },
a7a81d0b 574 .gpio_base = GPIO_BOARD_START,
60f9101a
MB
575 .ldo = {
576 &wm1192_ldo1, /* LDO1 */
577 &smdk6410_vdduh_mmc, /* LDO2 */
578 NULL, /* LDO3 NC */
579 &smdk6410_vddotgi, /* LDO4 */
580 &smdk6410_vddotg, /* LDO5 */
581 &smdk6410_vddhi, /* LDO6 */
582 &smdk6410_vddaudio, /* LDO7 */
583 &smdk6410_vccm2mtv, /* LDO8 */
584 &smdk6410_vddpll, /* LDO9 */
585 &smdk6410_vccmc3bt, /* LDO10 */
586 &smdk6410_vddalive, /* LDO11 */
587 },
588 .status = {
589 &wm1192_led7_pdata,
590 &wm1192_led8_pdata,
591 },
592};
593#endif
594
096941ed
BD
595static struct i2c_board_info i2c_devs0[] __initdata = {
596 { I2C_BOARD_INFO("24c08", 0x50), },
77897479 597 { I2C_BOARD_INFO("wm8580", 0x1b), },
ecc558ac 598
60f9101a
MB
599#ifdef CONFIG_SMDK6410_WM1192_EV1
600 { I2C_BOARD_INFO("wm8312", 0x34),
601 .platform_data = &smdk6410_wm1192_pdata,
602 .irq = S3C_EINT(12),
603 },
604#endif
605
ecc558ac
MB
606#ifdef CONFIG_SMDK6410_WM1190_EV1
607 { I2C_BOARD_INFO("wm8350", 0x1a),
608 .platform_data = &smdk6410_wm8350_pdata,
609 .irq = S3C_EINT(12),
610 },
611#endif
096941ed
BD
612};
613
614static struct i2c_board_info i2c_devs1[] __initdata = {
615 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
5718df9d
BD
616};
617
96d78686
BG
618/* LCD Backlight data */
619static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = {
620 .no = S3C64XX_GPF(15),
621 .func = S3C_GPIO_SFN(2),
622};
623
624static struct platform_pwm_backlight_data smdk6410_bl_data = {
625 .pwm_id = 1,
626};
627
99f6e1f5
JS
628static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
629
5718df9d
BD
630static void __init smdk6410_map_io(void)
631{
d6662c35
BD
632 u32 tmp;
633
5718df9d
BD
634 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
635 s3c24xx_init_clocks(12000000);
636 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
d6662c35
BD
637
638 /* set the LCD type */
639
640 tmp = __raw_readl(S3C64XX_SPCON);
641 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
642 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
643 __raw_writel(tmp, S3C64XX_SPCON);
644
645 /* remove the lcd bypass */
646 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
647 tmp &= ~MIFPCON_LCD_BYPASS;
648 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
5718df9d
BD
649}
650
651static void __init smdk6410_machine_init(void)
652{
f01fdac0
AG
653 u32 cs1;
654
d85fa24c 655 s3c_i2c0_set_platdata(NULL);
d7ea3743 656 s3c_i2c1_set_platdata(NULL);
438a5d42 657 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
99f6e1f5 658 s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
096941ed 659
290d0983
NKC
660 samsung_keypad_set_platdata(&smdk6410_keypad_data);
661
0804765a 662 s3c24xx_ts_set_platdata(NULL);
85b14a3f 663
f01fdac0
AG
664 /* configure nCS1 width to 16 bits */
665
666 cs1 = __raw_readl(S3C64XX_SROM_BW) &
667 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
668 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
669 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
670 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
671 S3C64XX_SROM_BW__NCS1__SHIFT;
672 __raw_writel(cs1, S3C64XX_SROM_BW);
673
674 /* set timing for nCS1 suitable for ethernet chip */
675
676 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
677 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
678 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
679 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
680 (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
681 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
682 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
683
b7f9a94b
MB
684 gpio_request(S3C64XX_GPN(5), "LCD power");
685 gpio_request(S3C64XX_GPF(13), "LCD power");
b7f9a94b 686
096941ed
BD
687 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
688 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
689
0ab0b6d2
AK
690 s3c_ide_set_platdata(&smdk6410_ide_pdata);
691
96d78686
BG
692 samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
693
5718df9d
BD
694 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
695}
696
697MACHINE_START(SMDK6410, "SMDK6410")
afdd225d 698 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
170a5908 699 .atag_offset = 0x100,
5718df9d
BD
700
701 .init_irq = s3c6410_init_irq,
702 .map_io = smdk6410_map_io,
703 .init_machine = smdk6410_machine_init,
cc8f252b 704 .init_late = s3c64xx_init_late,
6bb27d73 705 .init_time = s3c24xx_timer_init,
ff84ded2 706 .restart = s3c64xx_restart,
5718df9d 707MACHINE_END
This page took 0.237137 seconds and 5 git commands to generate.