[deliverable/linux.git] / arch / arm / mach-s3c64xx / pm.c

/* linux/arch/arm/plat-s3c64xx/pm.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C64XX CPU PM support.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/serial_core.h>
#include <linux/io.h>

#include <mach/map.h>
#include <mach/irqs.h>

#include <plat/pm.h>
#include <plat/wakeup-mask.h>

#include <mach/regs-sys.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-syscon-power.h>
#include <mach/regs-gpio-memport.h>

#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
void s3c_pm_debug_smdkled(u32 set, u32 clear)
{
	unsigned long flags;
	int i;

	local_irq_save(flags);
	for (i = 0; i < 4; i++) {
		if (clear & (1 << i))
			gpio_set_value(S3C64XX_GPN(12 + i), 0);
		if (set & (1 << i))
			gpio_set_value(S3C64XX_GPN(12 + i), 1);
	}
	local_irq_restore(flags);
}
#endif

static struct sleep_save core_save[] = {
	SAVE_ITEM(S3C_APLL_LOCK),
	SAVE_ITEM(S3C_MPLL_LOCK),
	SAVE_ITEM(S3C_EPLL_LOCK),
	SAVE_ITEM(S3C_CLK_SRC),
	SAVE_ITEM(S3C_CLK_DIV0),
	SAVE_ITEM(S3C_CLK_DIV1),
	SAVE_ITEM(S3C_CLK_DIV2),
	SAVE_ITEM(S3C_CLK_OUT),
	SAVE_ITEM(S3C_HCLK_GATE),
	SAVE_ITEM(S3C_PCLK_GATE),
	SAVE_ITEM(S3C_SCLK_GATE),
	SAVE_ITEM(S3C_MEM0_GATE),

	SAVE_ITEM(S3C_EPLL_CON1),
	SAVE_ITEM(S3C_EPLL_CON0),

	SAVE_ITEM(S3C64XX_MEM0DRVCON),
	SAVE_ITEM(S3C64XX_MEM1DRVCON),

#ifndef CONFIG_CPU_FREQ
	SAVE_ITEM(S3C_APLL_CON),
	SAVE_ITEM(S3C_MPLL_CON),
#endif
};

static struct sleep_save misc_save[] = {
	SAVE_ITEM(S3C64XX_AHB_CON0),
	SAVE_ITEM(S3C64XX_AHB_CON1),
	SAVE_ITEM(S3C64XX_AHB_CON2),
	
	SAVE_ITEM(S3C64XX_SPCON),

	SAVE_ITEM(S3C64XX_MEM0CONSTOP),
	SAVE_ITEM(S3C64XX_MEM1CONSTOP),
	SAVE_ITEM(S3C64XX_MEM0CONSLP0),
	SAVE_ITEM(S3C64XX_MEM0CONSLP1),
	SAVE_ITEM(S3C64XX_MEM1CONSLP),
};

void s3c_pm_configure_extint(void)
{
	__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
}

void s3c_pm_restore_core(void)
{
	__raw_writel(0, S3C64XX_EINT_MASK);

	s3c_pm_debug_smdkled(1 << 2, 0);

	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
}

void s3c_pm_save_core(void)
{
	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
}

/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
 * put the per-cpu code in here until any new cpu comes along and changes
 * this.
 */

static int s3c64xx_cpu_suspend(unsigned long arg)
{
	unsigned long tmp;

	/* set our standby method to sleep */

	tmp = __raw_readl(S3C64XX_PWR_CFG);
	tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
	tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
	__raw_writel(tmp, S3C64XX_PWR_CFG);

	/* clear any old wakeup */

	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
		     S3C64XX_WAKEUP_STAT);

	/* set the LED state to 0110 over sleep */
	s3c_pm_debug_smdkled(3 << 1, 0xf);

	/* issue the standby signal into the pm unit. Note, we
	 * issue a write-buffer drain just in case */

	tmp = 0;

	asm("b 1f\n\t"
	    ".align 5\n\t"
	    "1:\n\t"
	    "mcr p15, 0, %0, c7, c10, 5\n\t"
	    "mcr p15, 0, %0, c7, c10, 4\n\t"
	    "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));

	/* we should never get past here */

	panic("sleep resumed to originator?");
}

/* mapping of interrupts to parts of the wakeup mask */
static struct samsung_wakeup_mask wake_irqs[] = {
	{ .irq = IRQ_RTC_ALARM,	.bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
	{ .irq = IRQ_RTC_TIC,	.bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
	{ .irq = IRQ_PENDN,	.bit = S3C64XX_PWRCFG_TS_DISABLE, },
	{ .irq = IRQ_HSMMC0,	.bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
	{ .irq = IRQ_HSMMC1,	.bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
	{ .irq = IRQ_HSMMC2,	.bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_BATF_DISABLE},
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_MSM_DISABLE },
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_HSI_DISABLE },
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_MSM_DISABLE },
};

static void s3c64xx_pm_prepare(void)
{
	samsung_sync_wakemask(S3C64XX_PWR_CFG,
			      wake_irqs, ARRAY_SIZE(wake_irqs));

	/* store address of resume. */
	__raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);

	/* ensure previous wakeup state is cleared before sleeping */
	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
}

static int s3c64xx_pm_init(void)
{
	pm_cpu_prep = s3c64xx_pm_prepare;
	pm_cpu_sleep = s3c64xx_cpu_suspend;
	pm_uart_udivslot = 1;

#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
	gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
	gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
	gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
	gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
	gpio_direction_output(S3C64XX_GPN(12), 0);
	gpio_direction_output(S3C64XX_GPN(13), 0);
	gpio_direction_output(S3C64XX_GPN(14), 0);
	gpio_direction_output(S3C64XX_GPN(15), 0);
#endif

	return 0;
}

arch_initcall(s3c64xx_pm_init);
Commit	Line	Data
bd117bd1 BD	1	/* linux/arch/arm/plat-s3c64xx/pm.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C64XX CPU PM support.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/suspend.h>
	17	#include <linux/serial_core.h>
	18	#include <linux/io.h>
	19
	20	#include <mach/map.h>
fda22577	21	#include <mach/irqs.h>
bd117bd1 BD	22
bd117bd1 BD	23	#include <plat/pm.h>
fda22577 BD	24	#include <plat/wakeup-mask.h>
fda22577 BD	25
3501c9ae BD	26	#include <mach/regs-sys.h>
	27	#include <mach/regs-gpio.h>
	28	#include <mach/regs-clock.h>
	29	#include <mach/regs-syscon-power.h>
	30	#include <mach/regs-gpio-memport.h>
bd117bd1 BD	31
bd117bd1 BD	32	#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
bd117bd1 BD	33	void s3c_pm_debug_smdkled(u32 set, u32 clear)
	34	{
	35	unsigned long flags;
31858479	36	int i;
bd117bd1 BD	37
bd117bd1 BD	38	local_irq_save(flags);
31858479 JS	39	for (i = 0; i < 4; i++) {
	40	if (clear & (1 << i))
	41	gpio_set_value(S3C64XX_GPN(12 + i), 0);
	42	if (set & (1 << i))
	43	gpio_set_value(S3C64XX_GPN(12 + i), 1);
	44	}
bd117bd1 BD	45	local_irq_restore(flags);
	46	}
	47	#endif
	48
	49	static struct sleep_save core_save[] = {
	50	SAVE_ITEM(S3C_APLL_LOCK),
	51	SAVE_ITEM(S3C_MPLL_LOCK),
	52	SAVE_ITEM(S3C_EPLL_LOCK),
	53	SAVE_ITEM(S3C_CLK_SRC),
	54	SAVE_ITEM(S3C_CLK_DIV0),
	55	SAVE_ITEM(S3C_CLK_DIV1),
	56	SAVE_ITEM(S3C_CLK_DIV2),
	57	SAVE_ITEM(S3C_CLK_OUT),
	58	SAVE_ITEM(S3C_HCLK_GATE),
	59	SAVE_ITEM(S3C_PCLK_GATE),
	60	SAVE_ITEM(S3C_SCLK_GATE),
	61	SAVE_ITEM(S3C_MEM0_GATE),
	62
	63	SAVE_ITEM(S3C_EPLL_CON1),
	64	SAVE_ITEM(S3C_EPLL_CON0),
	65
	66	SAVE_ITEM(S3C64XX_MEM0DRVCON),
	67	SAVE_ITEM(S3C64XX_MEM1DRVCON),
	68
	69	#ifndef CONFIG_CPU_FREQ
	70	SAVE_ITEM(S3C_APLL_CON),
	71	SAVE_ITEM(S3C_MPLL_CON),
	72	#endif
	73	};
	74
	75	static struct sleep_save misc_save[] = {
	76	SAVE_ITEM(S3C64XX_AHB_CON0),
	77	SAVE_ITEM(S3C64XX_AHB_CON1),
	78	SAVE_ITEM(S3C64XX_AHB_CON2),
	79
	80	SAVE_ITEM(S3C64XX_SPCON),
	81
	82	SAVE_ITEM(S3C64XX_MEM0CONSTOP),
	83	SAVE_ITEM(S3C64XX_MEM1CONSTOP),
	84	SAVE_ITEM(S3C64XX_MEM0CONSLP0),
	85	SAVE_ITEM(S3C64XX_MEM0CONSLP1),
	86	SAVE_ITEM(S3C64XX_MEM1CONSLP),
	87	};
	88
	89	void s3c_pm_configure_extint(void)
	90	{
	91	__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
	92	}
	93
bd117bd1 BD	94	void s3c_pm_restore_core(void)
	95	{
	96	__raw_writel(0, S3C64XX_EINT_MASK);
	97
	98	s3c_pm_debug_smdkled(1 << 2, 0);
	99
	100	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
	101	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
	102	}
	103
	104	void s3c_pm_save_core(void)
	105	{
	106	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
	107	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
	108	}
	109
	110	/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
	111	* put the per-cpu code in here until any new cpu comes along and changes
	112	* this.
	113	*/
	114
29cb3cd2	115	static int s3c64xx_cpu_suspend(unsigned long arg)
bd117bd1 BD	116	{
	117	unsigned long tmp;
	118
	119	/* set our standby method to sleep */
	120
	121	tmp = __raw_readl(S3C64XX_PWR_CFG);
	122	tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
	123	tmp \|= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
	124	__raw_writel(tmp, S3C64XX_PWR_CFG);
	125
	126	/* clear any old wakeup */
	127
	128	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
	129	S3C64XX_WAKEUP_STAT);
	130
	131	/* set the LED state to 0110 over sleep */
	132	s3c_pm_debug_smdkled(3 << 1, 0xf);
	133
	134	/* issue the standby signal into the pm unit. Note, we
	135	* issue a write-buffer drain just in case */
	136
	137	tmp = 0;
	138
	139	asm("b 1f\n\t"
	140	".align 5\n\t"
	141	"1:\n\t"
	142	"mcr p15, 0, %0, c7, c10, 5\n\t"
	143	"mcr p15, 0, %0, c7, c10, 4\n\t"
	144	"mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
	145
	146	/* we should never get past here */
	147
	148	panic("sleep resumed to originator?");
	149	}
	150
fda22577 BD	151	/* mapping of interrupts to parts of the wakeup mask */
	152	static struct samsung_wakeup_mask wake_irqs[] = {
	153	{ .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
	154	{ .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
	155	{ .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
	156	{ .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
	157	{ .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
	158	{ .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
	159	{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
	160	{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
	161	{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
	162	{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
	163	};
	164
bd117bd1 BD	165	static void s3c64xx_pm_prepare(void)
bd117bd1 BD	166	{
fda22577 BD	167	samsung_sync_wakemask(S3C64XX_PWR_CFG,
	168	wake_irqs, ARRAY_SIZE(wake_irqs));
	169
bd117bd1 BD	170	/* store address of resume. */
	171	__raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
	172
	173	/* ensure previous wakeup state is cleared before sleeping */
	174	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
	175	}
	176
	177	static int s3c64xx_pm_init(void)
	178	{
	179	pm_cpu_prep = s3c64xx_pm_prepare;
	180	pm_cpu_sleep = s3c64xx_cpu_suspend;
	181	pm_uart_udivslot = 1;
31858479 JS	182
	183	#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
	184	gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
	185	gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
	186	gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
	187	gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
	188	gpio_direction_output(S3C64XX_GPN(12), 0);
	189	gpio_direction_output(S3C64XX_GPN(13), 0);
	190	gpio_direction_output(S3C64XX_GPN(14), 0);
	191	gpio_direction_output(S3C64XX_GPN(15), 0);
	192	#endif
	193
bd117bd1 BD	194	return 0;
	195	}
	196
	197	arch_initcall(s3c64xx_pm_init);