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8eba8ea2 | 1 | /* |
a7c9194c AG |
2 | * Copyright 2009 Andy Green <andy@warmcat.com> |
3 | * | |
4 | * S3C64XX SROM definitions | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
8eba8ea2 KK |
11 | #ifndef __MACH_S3C64XX_REGS_SROM_H |
12 | #define __MACH_S3C64XX_REGS_SROM_H __FILE__ | |
a7c9194c AG |
13 | |
14 | #define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) | |
15 | ||
16 | #define S3C64XX_SROM_BW S3C64XX_SROMREG(0) | |
17 | #define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4) | |
18 | #define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8) | |
19 | #define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc) | |
20 | #define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10) | |
21 | #define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14) | |
22 | #define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18) | |
23 | ||
24 | /* | |
25 | * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4 | |
26 | */ | |
27 | ||
28 | #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 | |
29 | #define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 | |
30 | #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 | |
8eba8ea2 | 31 | #define S3C64XX_SROM_BW__CS_MASK 0xf |
a7c9194c AG |
32 | |
33 | #define S3C64XX_SROM_BW__NCS0__SHIFT 0 | |
34 | #define S3C64XX_SROM_BW__NCS1__SHIFT 4 | |
35 | #define S3C64XX_SROM_BW__NCS2__SHIFT 8 | |
36 | #define S3C64XX_SROM_BW__NCS3__SHIFT 0xc | |
37 | #define S3C64XX_SROM_BW__NCS4__SHIFT 0x10 | |
38 | ||
39 | /* | |
40 | * applies to same to BCS0 - BCS4 | |
41 | */ | |
42 | ||
43 | #define S3C64XX_SROM_BCX__PMC__SHIFT 0 | |
44 | #define S3C64XX_SROM_BCX__PMC__MASK 3 | |
45 | #define S3C64XX_SROM_BCX__TACP__SHIFT 4 | |
46 | #define S3C64XX_SROM_BCX__TACP__MASK 0xf | |
47 | #define S3C64XX_SROM_BCX__TCAH__SHIFT 8 | |
48 | #define S3C64XX_SROM_BCX__TCAH__MASK 0xf | |
49 | #define S3C64XX_SROM_BCX__TCOH__SHIFT 12 | |
50 | #define S3C64XX_SROM_BCX__TCOH__MASK 0xf | |
51 | #define S3C64XX_SROM_BCX__TACC__SHIFT 16 | |
52 | #define S3C64XX_SROM_BCX__TACC__MASK 0x1f | |
53 | #define S3C64XX_SROM_BCX__TCOS__SHIFT 24 | |
54 | #define S3C64XX_SROM_BCX__TCOS__MASK 0xf | |
55 | #define S3C64XX_SROM_BCX__TACS__SHIFT 28 | |
56 | #define S3C64XX_SROM_BCX__TACS__MASK 0xf | |
57 | ||
8eba8ea2 | 58 | #endif /* __MACH_S3C64XX_REGS_SROM_H */ |