projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 431107ea | 1 | /* linux/arch/arm/mach-s3c64xx/cpu.c |
| a6925c1c BD |
2 | * |
| 3 | * Copyright 2009 Simtec Electronics | |
| 4 | * Ben Dooks <ben@simtec.co.uk> | |
| 5 | * http://armlinux.simtec.co.uk/ | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #include <linux/kernel.h> | |
| 13 | #include <linux/types.h> | |
| 14 | #include <linux/interrupt.h> | |
| 15 | #include <linux/list.h> | |
| 16 | #include <linux/timer.h> | |
| 17 | #include <linux/init.h> | |
| 18 | #include <linux/clk.h> | |
| 19 | #include <linux/io.h> | |
| 4a858cfc | 20 | #include <linux/device.h> |
| a6925c1c BD |
21 | #include <linux/serial_core.h> |
| 22 | #include <linux/platform_device.h> | |
| 23 | ||
| 24 | #include <asm/mach/arch.h> | |
| 25 | #include <asm/mach/map.h> | |
| 26 | #include <asm/mach/irq.h> | |
| 27 | ||
| 28 | #include <mach/hardware.h> | |
| 29 | #include <asm/irq.h> | |
| 30 | ||
| 31 | #include <plat/cpu-freq.h> | |
| 32 | #include <plat/regs-serial.h> | |
| 3501c9ae | 33 | #include <mach/regs-clock.h> |
| a6925c1c BD |
34 | |
| 35 | #include <plat/cpu.h> | |
| 36 | #include <plat/devs.h> | |
| 37 | #include <plat/clock.h> | |
| 38 | #include <plat/sdhci.h> | |
| 39 | #include <plat/iic-core.h> | |
| 999304be | 40 | #include <plat/onenand-core.h> |
| b024043b KK |
41 | |
| 42 | #include "common.h" | |
| a6925c1c BD |
43 | |
| 44 | void __init s3c6400_map_io(void) | |
| 45 | { | |
| 4faf6867 BD |
46 | /* setup SDHCI */ |
| 47 | ||
| 48 | s3c6400_default_sdhci0(); | |
| 49 | s3c6400_default_sdhci1(); | |
| 92b118f6 | 50 | s3c6400_default_sdhci2(); |
| 4faf6867 BD |
51 | |
| 52 | /* the i2c devices are directly compatible with s3c2440 */ | |
| a6925c1c | 53 | s3c_i2c0_setname("s3c2440-i2c"); |
| 14077ea6 PK |
54 | |
| 55 | s3c_device_nand.name = "s3c6400-nand"; | |
| 999304be MS |
56 | |
| 57 | s3c_onenand_setname("s3c6400-onenand"); | |
| 58 | s3c64xx_onenand1_setname("s3c6400-onenand"); | |
| a6925c1c BD |
59 | } |
| 60 | ||
| 61 | void __init s3c6400_init_clocks(int xtal) | |
| 62 | { | |
| 55bf9267 | 63 | s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK); |
| b024043b | 64 | s3c64xx_setup_clocks(); |
| a6925c1c BD |
65 | } |
| 66 | ||
| 67 | void __init s3c6400_init_irq(void) | |
| 68 | { | |
| 69 | /* VIC0 does not have IRQS 5..7, | |
| 70 | * VIC1 is fully populated. */ | |
| 71 | s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); | |
| 72 | } | |
| 73 | ||
| 4a858cfc KS |
74 | static struct bus_type s3c6400_subsys = { |
| 75 | .name = "s3c6400-core", | |
| 76 | .dev_name = "s3c6400-core", | |
| a6925c1c BD |
77 | }; |
| 78 | ||
| 4a858cfc KS |
79 | static struct device s3c6400_dev = { |
| 80 | .bus = &s3c6400_subsys, | |
| a6925c1c BD |
81 | }; |
| 82 | ||
| 83 | static int __init s3c6400_core_init(void) | |
| 84 | { | |
| 4a858cfc | 85 | return subsys_system_register(&s3c6400_subsys, NULL); |
| a6925c1c BD |
86 | } |
| 87 | ||
| 88 | core_initcall(s3c6400_core_init); | |
| 89 | ||
| 90 | int __init s3c6400_init(void) | |
| 91 | { | |
| 92 | printk("S3C6400: Initialising architecture\n"); | |
| 93 | ||
| 4a858cfc | 94 | return device_register(&s3c6400_dev); |
| a6925c1c | 95 | } |