projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 431107ea | 1 | /* linux/arch/arm/mach-s3c64xx/s3c6410.c |
| d626aeed BD |
2 | * |
| 3 | * Copyright 2008 Simtec Electronics | |
| 4 | * Copyright 2008 Simtec Electronics | |
| 5 | * Ben Dooks <ben@simtec.co.uk> | |
| 6 | * http://armlinux.simtec.co.uk/ | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/kernel.h> | |
| 14 | #include <linux/types.h> | |
| 15 | #include <linux/interrupt.h> | |
| 16 | #include <linux/list.h> | |
| 17 | #include <linux/timer.h> | |
| 18 | #include <linux/init.h> | |
| 19 | #include <linux/clk.h> | |
| 20 | #include <linux/io.h> | |
| 21 | #include <linux/sysdev.h> | |
| 22 | #include <linux/serial_core.h> | |
| 23 | #include <linux/platform_device.h> | |
| 24 | ||
| 25 | #include <asm/mach/arch.h> | |
| 26 | #include <asm/mach/map.h> | |
| 27 | #include <asm/mach/irq.h> | |
| 28 | ||
| 29 | #include <mach/hardware.h> | |
| 30 | #include <asm/irq.h> | |
| 31 | ||
| 32 | #include <plat/cpu-freq.h> | |
| 33 | #include <plat/regs-serial.h> | |
| 3501c9ae | 34 | #include <mach/regs-clock.h> |
| d626aeed BD |
35 | |
| 36 | #include <plat/cpu.h> | |
| 37 | #include <plat/devs.h> | |
| 38 | #include <plat/clock.h> | |
| 5cc7fd88 | 39 | #include <plat/sdhci.h> |
| 0ab0b6d2 | 40 | #include <plat/ata-core.h> |
| 50e9769a | 41 | #include <plat/adc-core.h> |
| 4f507d19 | 42 | #include <plat/iic-core.h> |
| 999304be | 43 | #include <plat/onenand-core.h> |
| 3cd7b62b KK |
44 | #include <plat/s3c6400.h> |
| 45 | #include <plat/s3c6410.h> | |
| d626aeed | 46 | |
| d626aeed BD |
47 | void __init s3c6410_map_io(void) |
| 48 | { | |
| 5cc7fd88 BD |
49 | /* initialise device information early */ |
| 50 | s3c6410_default_sdhci0(); | |
| a2205cd2 | 51 | s3c6410_default_sdhci1(); |
| 92b118f6 | 52 | s3c6410_default_sdhci2(); |
| 4f507d19 BD |
53 | |
| 54 | /* the i2c devices are directly compatible with s3c2440 */ | |
| 55 | s3c_i2c0_setname("s3c2440-i2c"); | |
| 56 | s3c_i2c1_setname("s3c2440-i2c"); | |
| 14077ea6 | 57 | |
| 50e9769a | 58 | s3c_adc_setname("s3c64xx-adc"); |
| 14077ea6 | 59 | s3c_device_nand.name = "s3c6400-nand"; |
| 999304be MS |
60 | s3c_onenand_setname("s3c6410-onenand"); |
| 61 | s3c64xx_onenand1_setname("s3c6410-onenand"); | |
| 0ab0b6d2 | 62 | s3c_cfcon_setname("s3c64xx-pata"); |
| d626aeed BD |
63 | } |
| 64 | ||
| 65 | void __init s3c6410_init_clocks(int xtal) | |
| 66 | { | |
| 39669f59 | 67 | printk(KERN_DEBUG "%s: initialising clocks\n", __func__); |
| 55bf9267 | 68 | s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK); |
| cf18acf0 | 69 | s3c6400_setup_clocks(); |
| d626aeed BD |
70 | } |
| 71 | ||
| d9b79fb5 BD |
72 | void __init s3c6410_init_irq(void) |
| 73 | { | |
| 74 | /* VIC0 is missing IRQ7, VIC1 is fully populated. */ | |
| 75 | s3c64xx_init_irq(~0 & ~(1 << 7), ~0); | |
| 76 | } | |
| 77 | ||
| d626aeed BD |
78 | struct sysdev_class s3c6410_sysclass = { |
| 79 | .name = "s3c6410-core", | |
| 80 | }; | |
| 81 | ||
| 82 | static struct sys_device s3c6410_sysdev = { | |
| 83 | .cls = &s3c6410_sysclass, | |
| 84 | }; | |
| 85 | ||
| 86 | static int __init s3c6410_core_init(void) | |
| 87 | { | |
| 88 | return sysdev_class_register(&s3c6410_sysclass); | |
| 89 | } | |
| 90 | ||
| 91 | core_initcall(s3c6410_core_init); | |
| 92 | ||
| 93 | int __init s3c6410_init(void) | |
| 94 | { | |
| 95 | printk("S3C6410: Initialising architecture\n"); | |
| 96 | ||
| 97 | return sysdev_register(&s3c6410_sysdev); | |
| 98 | } |