projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b7db51be KK |
1 | /* linux/arch/arm/mach-s5p6440/include/mach/irqs.h |
| 2 | * | |
| 3 | * Copyright 2009 Samsung Electronics Co., Ltd. | |
| 4 | * http://www.samsung.com/ | |
| 5 | * | |
| 6 | * S5P6440 - IRQ definitions | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __ASM_ARCH_S5P_IRQS_H | |
| 14 | #define __ASM_ARCH_S5P_IRQS_H __FILE__ | |
| 15 | ||
| 16 | #include <plat/irqs.h> | |
| 17 | ||
| 18 | /* VIC0 */ | |
| 19 | ||
| 20 | #define IRQ_EINT0_3 S5P_IRQ_VIC0(0) | |
| 21 | #define IRQ_EINT4_11 S5P_IRQ_VIC0(1) | |
| 22 | #define IRQ_RTC_TIC S5P_IRQ_VIC0(2) | |
| 23 | #define IRQ_IIC1 S5P_IRQ_VIC0(5) | |
| 24 | #define IRQ_I2SV40 S5P_IRQ_VIC0(6) | |
| 25 | #define IRQ_GPS S5P_IRQ_VIC0(7) | |
| 26 | #define IRQ_POST0 S5P_IRQ_VIC0(9) | |
| 27 | #define IRQ_2D S5P_IRQ_VIC0(11) | |
| 28 | #define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) | |
| 29 | #define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) | |
| 30 | #define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25) | |
| 31 | #define IRQ_WDT S5P_IRQ_VIC0(26) | |
| 32 | #define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27) | |
| 33 | #define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28) | |
| 34 | #define IRQ_DISPCON0 S5P_IRQ_VIC0(29) | |
| 35 | #define IRQ_DISPCON1 S5P_IRQ_VIC0(30) | |
| 36 | #define IRQ_DISPCON2 S5P_IRQ_VIC0(31) | |
| 37 | ||
| 38 | /* VIC1 */ | |
| 39 | ||
| 40 | #define IRQ_EINT12_15 S5P_IRQ_VIC1(0) | |
| 41 | #define IRQ_PCM0 S5P_IRQ_VIC1(2) | |
| 42 | #define IRQ_UART0 S5P_IRQ_VIC1(5) | |
| 43 | #define IRQ_UART1 S5P_IRQ_VIC1(6) | |
| 44 | #define IRQ_UART2 S5P_IRQ_VIC1(7) | |
| 45 | #define IRQ_UART3 S5P_IRQ_VIC1(8) | |
| 46 | #define IRQ_DMA0 S5P_IRQ_VIC1(9) | |
| 47 | #define IRQ_NFC S5P_IRQ_VIC1(13) | |
| 48 | #define IRQ_SPI0 S5P_IRQ_VIC1(16) | |
| 49 | #define IRQ_SPI1 S5P_IRQ_VIC1(17) | |
| 50 | #define IRQ_IIC S5P_IRQ_VIC1(18) | |
| 51 | #define IRQ_DISPCON3 S5P_IRQ_VIC1(19) | |
| 52 | #define IRQ_FIMGVG S5P_IRQ_VIC1(20) | |
| 53 | #define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) | |
| 54 | #define IRQ_PMUIRQ S5P_IRQ_VIC1(23) | |
| 55 | #define IRQ_HSMMC0 S5P_IRQ_VIC1(24) | |
| 56 | #define IRQ_HSMMC1 S5P_IRQ_VIC1(25) | |
| 57 | #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ | |
| 58 | #define IRQ_OTG S5P_IRQ_VIC1(26) | |
| 59 | #define IRQ_DSI S5P_IRQ_VIC1(27) | |
| 60 | #define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) | |
| 61 | #define IRQ_TSI S5P_IRQ_VIC1(29) | |
| 62 | #define IRQ_PENDN S5P_IRQ_VIC1(30) | |
| 63 | #define IRQ_TC IRQ_PENDN | |
| 64 | #define IRQ_ADC S5P_IRQ_VIC1(31) | |
| 65 | ||
| 66 | /* | |
| 67 | * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined | |
| 68 | * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place | |
| 69 | * after the pair of VICs. | |
| 70 | */ | |
| 71 | ||
| 72 | #define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6) | |
| 73 | ||
| 74 | #define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) | |
| 75 | #define IRQ_EINT(x) S5P_EINT(x) | |
| 76 | ||
| 77 | /* | |
| 78 | * Next the external interrupt groups. These are similar to the IRQ_EINT(x) | |
| 79 | * that they are sourced from the GPIO pins but with a different scheme for | |
| 80 | * priority and source indication. | |
| 81 | * | |
| 82 | * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO | |
| 83 | * interrupts, but for historical reasons they are kept apart from these | |
| 84 | * next interrupts. | |
| 85 | * | |
| 86 | * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the | |
| 87 | * machine specific support files. | |
| 88 | */ | |
| 89 | ||
| 90 | /* Actually, #6 and #7 are missing in the EINT_GROUP1 */ | |
| 91 | #define IRQ_EINT_GROUP1_NR (15) | |
| 92 | #define IRQ_EINT_GROUP2_NR (8) | |
| 93 | #define IRQ_EINT_GROUP5_NR (7) | |
| 94 | #define IRQ_EINT_GROUP6_NR (10) | |
| 95 | /* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */ | |
| 96 | #define IRQ_EINT_GROUP8_NR (11) | |
| 97 | ||
| 98 | #define IRQ_EINT_GROUP_BASE S5P_EINT(16) | |
| 99 | #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0) | |
| 100 | #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) | |
| 101 | #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) | |
| 102 | #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) | |
| 103 | #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) | |
| 104 | ||
| 105 | #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) | |
| 106 | ||
| 107 | /* Set the default NR_IRQS */ | |
| 108 | ||
| 109 | #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) | |
| 110 | ||
| 111 | #endif /* __ASM_ARCH_S5P_IRQS_H */ |