projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 461859db KK |
1 | /* linux/arch/arm/mach-s5p6442/mach-smdk6442.c |
| 2 | * | |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
| 4 | * http://www.samsung.com/ | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | ||
| 11 | #include <linux/kernel.h> | |
| 12 | #include <linux/types.h> | |
| 13 | #include <linux/init.h> | |
| 14 | #include <linux/serial_core.h> | |
| c204fb15 | 15 | #include <linux/i2c.h> |
| 461859db KK |
16 | |
| 17 | #include <asm/mach/arch.h> | |
| 18 | #include <asm/mach/map.h> | |
| 19 | #include <asm/setup.h> | |
| 20 | #include <asm/mach-types.h> | |
| 21 | ||
| 22 | #include <mach/map.h> | |
| 23 | #include <mach/regs-clock.h> | |
| 24 | ||
| 25 | #include <plat/regs-serial.h> | |
| 26 | #include <plat/s5p6442.h> | |
| 27 | #include <plat/devs.h> | |
| 28 | #include <plat/cpu.h> | |
| c204fb15 | 29 | #include <plat/iic.h> |
| 461859db KK |
30 | |
| 31 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | |
| c8def085 | 32 | #define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 461859db KK |
33 | S3C2410_UCON_RXILEVEL | \ |
| 34 | S3C2410_UCON_TXIRQMODE | \ | |
| 35 | S3C2410_UCON_RXIRQMODE | \ | |
| 36 | S3C2410_UCON_RXFIFO_TOI | \ | |
| 37 | S3C2443_UCON_RXERR_IRQEN) | |
| 38 | ||
| c8def085 | 39 | #define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8 |
| 461859db | 40 | |
| c8def085 | 41 | #define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
| 461859db KK |
42 | S5PV210_UFCON_TXTRIG4 | \ |
| 43 | S5PV210_UFCON_RXTRIG4) | |
| 44 | ||
| 45 | static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { | |
| 46 | [0] = { | |
| 47 | .hwport = 0, | |
| 48 | .flags = 0, | |
| c8def085 KK |
49 | .ucon = SMDK6442_UCON_DEFAULT, |
| 50 | .ulcon = SMDK6442_ULCON_DEFAULT, | |
| 51 | .ufcon = SMDK6442_UFCON_DEFAULT, | |
| 461859db KK |
52 | }, |
| 53 | [1] = { | |
| 54 | .hwport = 1, | |
| 55 | .flags = 0, | |
| c8def085 KK |
56 | .ucon = SMDK6442_UCON_DEFAULT, |
| 57 | .ulcon = SMDK6442_ULCON_DEFAULT, | |
| 58 | .ufcon = SMDK6442_UFCON_DEFAULT, | |
| 461859db KK |
59 | }, |
| 60 | [2] = { | |
| 61 | .hwport = 2, | |
| 62 | .flags = 0, | |
| c8def085 KK |
63 | .ucon = SMDK6442_UCON_DEFAULT, |
| 64 | .ulcon = SMDK6442_ULCON_DEFAULT, | |
| 65 | .ufcon = SMDK6442_UFCON_DEFAULT, | |
| 461859db KK |
66 | }, |
| 67 | }; | |
| 68 | ||
| 69 | static struct platform_device *smdk6442_devices[] __initdata = { | |
| c204fb15 | 70 | &s3c_device_i2c0, |
| 2fe4f0cb | 71 | &samsung_asoc_dma, |
| 78a36823 | 72 | &s5p6442_device_iis0, |
| b46de63d | 73 | &s3c_device_wdt, |
| 461859db KK |
74 | }; |
| 75 | ||
| c204fb15 JB |
76 | static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = { |
| 77 | { I2C_BOARD_INFO("wm8580", 0x1b), }, | |
| 78 | }; | |
| 79 | ||
| 461859db KK |
80 | static void __init smdk6442_map_io(void) |
| 81 | { | |
| 82 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | |
| 83 | s3c24xx_init_clocks(12000000); | |
| 84 | s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs)); | |
| 85 | } | |
| 86 | ||
| 87 | static void __init smdk6442_machine_init(void) | |
| 88 | { | |
| c204fb15 JB |
89 | s3c_i2c0_set_platdata(NULL); |
| 90 | i2c_register_board_info(0, smdk6442_i2c_devs0, | |
| 91 | ARRAY_SIZE(smdk6442_i2c_devs0)); | |
| 461859db KK |
92 | platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices)); |
| 93 | } | |
| 94 | ||
| 95 | MACHINE_START(SMDK6442, "SMDK6442") | |
| 96 | /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ | |
| 461859db KK |
97 | .boot_params = S5P_PA_SDRAM + 0x100, |
| 98 | .init_irq = s5p6442_init_irq, | |
| 99 | .map_io = smdk6442_map_io, | |
| 100 | .init_machine = smdk6442_machine_init, | |
| 101 | .timer = &s3c24xx_timer, | |
| 102 | MACHINE_END |